Introduction to
Programmable Logic
John Coughlan
RAL Technology Department
Electronics Division
PPD Lectures

Data Transport

Triggering

Computers interacting with Hardware (VME Bus)

Silicon Trackers (Millions of Data Channels)

Programmable Logic is Key Underlying Technology.

Commercial Devices. Driven by Industry.
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The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Particle Physics Electronics
CMS
Custom Electronics Chips
Radn Hard, Low Power
CERN LHC
Electronics “Counting” Room(s)
Trigger Systems. DAQ Systems.
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Purpose Built Digital Processing Boards
In VME Bus Crates
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Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Particle Physics Electronics

Special Dedicated Logic Functions (not possible in CPUs)


Ultra Fast Trigger Systems (Trigger Algorithms) Clock Accurate
Timing
Massively Parallel Data Processing (Silicon Trackers with Millions of
Channels)
Custom Designed
Printed Circuit Boards PCBs.
Commercial
Programmable Logic
Devices
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The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Lecture Outline

Programmable Logic Devices



Field Programmable Gate Arrays (FPGAs)


Architecture
Design Flow



Basics
Evolution
Design Tools
Hardware Description Languages
Industry Trends
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Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Digital Logic
Digital Logic Function
Product AND (&)
Sum OR (|)
3 Inputs
Black Box
Truth Table
SUM of PRODUCTS
Boolean Logic Minimisation
Connect Standard Logic Chips
Very Simple Glue Logic
FIXED Logic
Transistor Switches
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Devices, Tools, and Flows. ISBN 0750676043
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Programmable Logic Devices
PLDs
Un-programmed State
Different Types
 SUM of PRODUCTS
 Prefabricated
 Programmble Links
 Reconfigurable

Planes of
ANDs, ORs
Logic Function
Inputs
Sums
ANDs
OR
Programmed PLD
Product Terms
Sum of Products
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Devices, Tools, and Flows. ISBN 0750676043
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Complex PLDs
CPLDs
 Programmable PLD Blocks
 Programmable Interconnects
 Electrically Erasable links

CPLD Architecture
Feedback Outputs
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Devices, Tools, and Flows. ISBN 0750676043
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Application Specific Integrated Circuits
ASICs
PLDs
SPLDs
Prefabricated
Programmed
CPLDs
ASICs
The
GAP
Gate Arrays
Custom Fabricated
Design from Scratch
Structured ASICs*
Standard Cell
Full Custom
*Not available circa early 1980s
Limited Complexity
Thousands of Gates
Cheap
Easy to Design
Reprogrammable.
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Large Complex Functions . Millions of Gates
Customised for Extremes of Speed, Low Power, Radiation
Hard
(Very) Expensive (in small quantities) > $1 Million mask set
(Very) Hard to Design.
Long Design cycles.
NOT Reprogrammable. High Risk
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Application Specific Integrated Circuits
ASICs
PLDs
SPLDs
ASICs
The
GAP
CPLDs
Gate Arrays
Structured ASICs*
FPGA
Standard Cell
Full Custom
*Not available circa early 1980s
Large Complex Functions
Inexpensive
Easy to Design
Reprogrammable.
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The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Field Programmable Gate Arrays
FPGA

Field Programmable Gate Array



New Architecture
‘Simple’ Programmable Logic Blocks
Massive Fabric of Programmable Interconnects
Large Number of Logic Block ‘Islands’
1,000 … 100,000+
in a ‘Sea’ of Interconnects
FPGA Architecture
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Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Logic Blocks



Logic Functions implemented in Lookup Table LUTs
Multiplexers (select 1 of N inputs)
Flip-Flops. Registers. Clocked Storage elements.
16-bit SR
16x1 RAM
a
b
c
d
4-input
LUT
y
mux
flip-flop
q
e
clock
clock enable
set/reset
FPGA Fabric
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Logic Block
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Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Lookup Tables LUTs




LUT contains Memory Cells to implement small logic functions
Each cell holds ‘0’ or ‘1’ .
Programmed with outputs of Truth Table
Inputs select content of one of the cells as output
3 Inputs LUT -> 8 Memory Cells
16-bit SR
16x1 RAM
3 – 6 Inputs
a
b
c
d
4-input
LUT
y
mux
flip-flop
q
e
clock
clock enable
set/reset
SRAM
SRAM
Multiplexer MUX
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Static Random Access Memory
SRAM cells
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Logic Blocks

Larger Logic Functions built up by connecting many Logic
Blocks together
16-bit SR
16x1 RAM
a
b
c
d
e
4-input
LUT
y
mux
flip-flop
q
clock
clock enable
set/reset
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Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Clocked Logic




Flip Flops on outputs. CLOCKED storage elements.
Sequential Logic Functions (cf Combinational Logic LUTs)
Pipelines. Synchronous Logic Design
FPGA Fabric driven by Global Clock (e.g. BX frequency)
16-bit SR
16x1 RAM
a
b
c
d
e
4-input
LUT
y
mux
flip-flop
q
clock
clock enable
set/reset
FPGA Fabric
Clock
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Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
FPGA Design Synchronous Logic


Pipelining Logic
Combinational Logic
Combinational
Logic
Combinational
Logic
Data In
Combinational
Logic
etc.
Result
Three levels of logic
AND
From previous
bank of registers
&
OR
|
NOR
To next bank
of registers
|
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Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
FPGA Design Synchronous Logic



Pipelining Logic
Combinational Logic Stored in Registers.
Clocked Logic (e.g. at LHC BX 40 MHz)
Combinational
Logic
Combinational
Logic
Combinational
Logic
Data In
etc.
Registers
Combinational
Logic
Registers
Combinational
Logic
Registers
Data In
etc.
Once Pipeline Full
New Result every Clock Period
Clock
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Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
FPGA Design Synchronous Logic



Pipelining
Combinational and Sequential Logic.
Clocked Logic (e.g. at LHC BX 40 MHz)
Combinational
Logic
Combinational
Logic
Combinational
Logic
Data In
etc.
Registers
Combinational
Logic
Registers
Combinational
Logic
Registers
16-bit SR
16x1 RAM
a
b
c
d
Data In
etc.
e
4-input
LUT
y
mux
flip-flop
q
clock
clock enable
set/reset
Clock
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Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Clocked Logic

FPGA Fabric driven by Global Clock (e.g. BX frequency)
Registers
Combinational
Logic
Registers
Combinational
Logic
Registers
Register Transfer Logic RTL
Data In
etc.
Clock
16-bit SR
16x1 RAM
a
b
c
d
e
4-input
LUT
y
mux
flip-flop
q
clock
clock enable
set/reset
FPGA Fabric
Clock
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Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Routing


Connections Routing signals between Logic Blocks
Determined by SRAM cells
SRAM
Special Routing for Clocks
Around Fabric Edges Configurable Input Output I/O Blocks
100’s – 1,000 Pins
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Configuring an FPGA




Millions of SRAM cells holding LUTs and Interconnect Routing
Volatile Memory. Loses configuration when board power is
turned off.
Keep Bit Pattern describing the SRAM cells in non-Volatile
Memory e.g. ROM or Digital Camera card
Configuration takes ~ secs
JTAG Port
Configuration data in
Configuration data out
= I/O pin/pad
Programming
Bit File
= SRAM cell
SRAM
JTAG Testing
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Devices, Tools, and Flows. ISBN 0750676043
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Designing Logic with FPGAs

High level Description of Logic Design

Hardware Description Language (Textual)

Compile (Synthesise) into Netlist.
Boolean Logic Gates.

Target FPGA Fabric




Mapping
Routing
Bit File for FPGA
Design Flow
Schematic
capture
Gate-level
netlist
BEGIN CIRCUIT=TEST
INPUT SET_A, SET-B,
DATA, CLOCK,
CLEAR_A, CLEAR_B;
OUTPUT Q, N_Q;
WIRE
SET, N_DATA, CLEAR;
GATE G1=NAND (IN1=SET_A,
IN2=SET_B,
OUT1=SET);
GATE G2=NOT (IN1=DATA,
OUT1=N_DATA);
GATE G3=OR
(IN1=CLEAR_A,
IN2=CLEAR_B,
OUT1=CLEAR);
GATE G4=DFF (IN1=SET, IN2=N_DATA,
IN3=CLOCK, IN4=CLEAR,
OUT1=Q, OUT2=N_Q);
END CIRCUIT=TEST;
Mapping
Packing


Commercial CAE Tools
(Complex & Expensive)
Logic Simulation
Place-andRoute
Fully-routed physical
(CLB-level) netlist
Timing analysis
and timing report
Gate-level netlist
for simulation
SDF (timing info)
for simulation
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Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Hardware Description Languages

High Level Description of Logic






Program Statements. Loops. If Statements …etc
Describing Mixture of Combinational and Sequential (Clocked) Logic and
Signals between.
Register Transfer Level Description
Program Describes how to construct Hardware logic.
Unlike conventional Programming Language generating machine code for
Sequential Processor
In practice often closely tied to Hardware (like Assembly Language)

Non Portable

Electronics Engineers call code “Firmware”

VHDL (VHSIC Hardware Description Language)


Very High Speed Integrated Circuit
VERILOG Language
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Devices, Tools, and Flows. ISBN 0750676043
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VHDL Firmware
architecture Behavioral of dpmbufctrl is
signal acount
signal dcount
signal bram_addr_i
Architecture
: std_logic_vector(31 downto 0);
: std_logic_vector(31 downto 0);
: std_logic_vector(31 downto 0);
Signals
begin
bram_en <='1';
bram_rst <= '0';
--bit order reverse address and data buses to match EDK scheme
bram_addr(0 to 31) <= bram_addr_i(31 downto 0);
Cf High Level Software Language
C, Pascal
--N.B. EDK DOCM addresses are byte orientated count in 4s for whole words
g1 : process(clk, rst)
Functions
Parallel Processes
variable state : integer range 0 to 3;
variable buf_zone: integer range 0 to 1;
begin
Variables
Code Blocks
if clk'event and clk = '1' then
if rst = '1' then
buf_zone:=0;
acount <= (others => '0');
dcount <= (others => '0');
bram_wen <= (others => '0');
bram_addr_i <= X"00001FFC"; -bram_dout_i <= (others => '0');
state:=0;
elsif state = 0 then
--wait for din(0) at address 1FFC to be set to zero
--what about pipeline of BRAM - need to wait before polling?
bram_wen <= (others => '0');
acount <= (others => '0');
bram_addr_i <= X"00001FFC";
bram_dout_i <= (others => '0');
dcount <= dcount;
if bram_din_i = X"00000000" then
state := 1;
else
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state := 0;
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end if;
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Flip Flop Registers
Signal Assignments
If Else Blocks
Multiplexers
Field Programmable Gate Arrays
FPGA











Large Complex Functions
Programmability, Flexibility.
Massively Parallel Architecture
Processing many channels simultaneously cf MicroProcessor
sequential processing
Fast Turnaround Designs
SRAM Based. Standard IC Manufacturing Processes (Memory Chips)
Leading Edge of Moore’s Law
Mass produced. Inexpensive.
Many variants. Sizes. Features.
Not Radiation Hard
Power Hungry
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Trends

State of Art is 65nm on 300 mm wafers
Top of range 100,000+ Logic Blocks
1,000 pins (Fine Pitched Ball Grid Arrays)

Logic Block cost ~ 1$ in 1990 ; $0.002 in 2005

Challenges





Power. Leakage currents.
Signal Integrity
Design Gap

CAE Tools
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Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Summary

Programmable Logic Devices



Field Programmable Gate Arrays (FPGAs)


Basics
Evolution
Architecture
Design Flow


Hardware Description Languages
Design Tools

Trends

Importance for Particle Physics Experiments
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The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
Highly Recommended Books









Bebop to the Boolean Algebra
Clive Maxfield
Published by Newnes
The Design Warrior’s Guide to FPGAs
Clive Maxfield
Published by Newnes
Fundamentals of Digital Logic with VHDL
Stephen Brown, Zvonko Vranesic
Published by McGraw Hill
[email protected]
The Design Warrior’s Guide to FPGAs
Devices, Tools, and Flows. ISBN 0750676043
Copyright © 2004 Mentor Graphics Corp. (www.mentor.com)
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Introduction to FPGAs