FPGAs and VHDL
Lecture L12.1
FPGAs and VHDL
• Field Programmable Gate Arrays (FPGAs)
• VHDL
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2 x 1 MUX
4 x 1 MUX
An Adder
Binary-to-BCD Converter
A Register
Fibonacci Sequence Generator
Block diagram of Xilinx Spartan IIE FPGA
Each Spartan IIE CLB contains
two of these CLB slices
Look Up Tables
• Combinatorial Logic is stored in 16x1 SRAM Look Up
Tables (LUTs) in a CLB
Look Up Table
4-bit address
• Example:
Combinatorial Logic
A B C D
A
B
Z
C
D
 Capacity is limited by number of
inputs, not complexity
 Choose to use each function
generator as 4 input logic (LUT) or
as high speed sync.dual port
WE
RAM
G4
G3
G2
G1
G
Func.
Gen.
0
0
0
0
0
0
0
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
Z
0
0
0
1
1
1
. . .
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
0
0
1
4
(2 )
2
= 64K !
Introduction to VHDL
• VHDL is an acronym for VHSIC (Very
High Speed Integrated Circuit) Hardware
Description Language
• IEEE standard specification language (IEEE
1076-1993) for describing digital hardware
used by industry worldwide
• VHDL enables hardware modeling from the
gate level to the system level
Combinational Circuit Example
8-line 2-to-1 Multiplexer
a(7:0)
b(7:0)
8-line
2 x 1 MUX
sel
y(7:0)
sel
0
1
y
a
b
An 8-line 2 x 1 MUX
a(7:0)
library IEEE;
use IEEE.std_logic_1164.all;
b(7:0)
8-line
2x1
MUX
entity mux2 is
sel
port (
a: in STD_LOGIC_VECTOR(7 downto 0);
b: in STD_LOGIC_VECTOR(7 downto 0);
sel: in STD_LOGIC;
y: out STD_LOGIC_VECTOR(7 downto 0)
);
end mux2;
y(7:0)
Entity
library IEEE;
use IEEE.std_logic_1164.all;
Each entity must
begin with these
library and use
statements
entity mux2 is
port (
a: in STD_LOGIC_VECTOR(7 downto 0);
b: in STD_LOGIC_VECTOR(7 downto 0);
sel: in STD_LOGIC;
y: out STD_LOGIC_VECTOR(7 downto 0)
);
end mux2;
port statement defines
inputs and outputs
Entity
library IEEE;
use IEEE.std_logic_1164.all;
Mode: in or out
entity mux2 is
port (
a: in STD_LOGIC_VECTOR(7 downto 0);
b: in STD_LOGIC_VECTOR(7 downto 0);
sel: in STD_LOGIC;
y: out STD_LOGIC_VECTOR(7 downto 0)
);
end mux2;
Data type: STD_LOGIC,
STD_LOGIC_VECTOR(7 downto 0);
Architecture
architecture mux2_arch of mux2 is
begin
mux2_1: process(a, b, sel)
begin
a(7:0)
if sel = '0' then
y <= a;
b(7:0)
else
y <= b;
end if;
end process mux2_1;
end mux2_arch;
8-line
2x1
MUX
y(7:0)
sel
Note: <= is signal assignment
Architecture
entity name
process sensitivity
list
architecture mux2_arch of mux2 is
begin
mux2_1: process(a, b, sel)
begin
Sequential statements
if sel = '0' then
(if…then…else) must
y <= a;
be in a process
else
y <= b;
end if;
end process mux2_1;
end mux2_arch;
Note begin…end
in architecture
Note begin…end
in process
An 8-line 4 x 1 multiplexer
a(7:0)
b(7:0)
c(7:0)
d(7:0)
8-line
4x1
MUX
sel(1:0)
y(7:0)
Sel
“00”
“01”
“10”
“11”
y
a
b
c
d
An 8-line 4 x 1 multiplexer
library IEEE;
use IEEE.std_logic_1164.all;
entity mux4 is
port (
a: in STD_LOGIC_VECTOR (7 downto 0);
b: in STD_LOGIC_VECTOR (7 downto 0);
c: in STD_LOGIC_VECTOR (7 downto 0);
d: in STD_LOGIC_VECTOR (7 downto 0);
sel: in STD_LOGIC_VECTOR (1 downto 0);
y: out STD_LOGIC_VECTOR (7 downto 0)
);
end mux4;
Example of case statement
architecture mux4_arch of mux4 is
begin
Note implies operator =>
process (sel, a, b, c, d)
begin
case sel is
Sel
y
when "00"
=> y <= a;
“00”
a
when "01"
=> y <= b;
“01”
b
when "10"
=> y <= c;
when others => y <= d;
“10”
c
end case;
“11”
d
end process;
end mux4_arch;
Must include ALL posibilities
in case statement
An Adder
-- Title: adder
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
b (n -1 :0 )
a (n -1 :0 )
adder
entity adder is
generic(width:positive);
y(n -1 :0 )
port (
a: in STD_LOGIC_VECTOR(width-1 downto 0);
b: in STD_LOGIC_VECTOR(width-1 downto 0);
y: out STD_LOGIC_VECTOR(width-1 downto 0)
);
end adder;
architecture adder_arch of adder is
begin
add1: process(a, b)
begin
y <= a + b;
end process add1;
end adder_arch;
Note: + sign synthesizes
an n-bit full adder!
Binary-to-BCD Converter
-- Title: Binary-to-BCD Converter
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity binbcd is
port (
B: in STD_LOGIC_VECTOR (7 downto 0);
P: out STD_LOGIC_VECTOR (9 downto 0)
);
end binbcd;
rchitecture binbcd_arch of binbcd is
egin
bcd1: process(B)
variable z: STD_LOGIC_VECTOR (17 downto 0);
begin
for i in 0 to 17 loop
z(i) := '0';
end loop;
z(10 downto 3) := B;
for i in 0 to 4 loop
if z(11 downto 8) > 4 then
z(11 downto 8) := z(11 downto 8) + 3;
end if;
if z(15 downto 12) > 4 then
z(15 downto 12) := z(15 downto 12) + 3;
end if;
z(17 downto 1) := z(16 downto 0);
end loop;
P <= z(17 downto 8);
end process bcd1;
nd binbcd_arch;
A Register
d (n -1 :0 )
-- A width-bit register
library IEEE;
use IEEE.std_logic_1164.all;
clr
re g
clk
entity reg is
q (n -1 :0 )
generic(width: positive);
port (
d: in STD_LOGIC_VECTOR (width-1 downto 0);
load: in STD_LOGIC;
clr: in STD_LOGIC;
clk: in STD_LOGIC;
q: out STD_LOGIC_VECTOR (width-1 downto 0)
);
end reg;
lo a d
Register architecture
d (n -1 :0 )
architecture reg_arch of reg is
clr
begin
re g
process(clk, clr)
clk
begin
if clr = '1' then
for i in width-1 downto 0 loop
q (n -1 :0 )
q(i) <= '0';
end loop;
elsif (clk'event and clk = '1') then
if load = '1' then
q <= d;
end if;
end if;
Infers a flip-flop for
end process;
outputs (q)
end reg_arch;
lo a d
all
Fibonacci Sequence
r
1
8
r
t
8
B
-- Title: Fibonacci Sequence
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_unsigned.all;
se t
clr
clk
R1
A
+
S
s
1
8
se t
clr
W
clk
entity fib is
port(
r
8
clr : in std_logic;
clk : in std_logic;
P : out std_logic_vector(9 downto 0)
);
end fib;
hunds
te n s
u n its
b in b cd
P
architecture fib_arch of fib is
Declare
components
component adder
generic(
width : POSITIVE);
port(
a : in std_logic_vector((width-1) downto 0);
b : in std_logic_vector((width-1) downto 0);
y : out std_logic_vector((width-1) downto 0));
end component;
component reg
generic(
width : POSITIVE);
port(
d : in std_logic_vector((width-1) downto 0);
load : in std_logic;
clr : in std_logic;
set : in std_logic;
clk : in std_logic;
q : out std_logic_vector((width-1) downto 0));
end component;
component binbcd
port(
B : in std_logic_vector(7 downto 0);
P : out std_logic_vector(9 downto 0));
end component;
signal r, s, t: std_logic_vector(7 downto 0);
signal one, zero: std_logic;
r
constant bus_width: positive := 8;
1
8
se t
clr
clk
R1
r
t
8
B
A
+
S
s
1
8
se t
clr
W
clk
r
8
b in b cd
hunds
te n s
u n its
begin
one <= '1';
zero <= '0';
U1: adder generic map(width => bus_width) port map
(a => t, b => r, y => s);
R1: reg generic map(width => bus_width) port map
(d => r, load =>one, clr => zero, set => clr,
clk =>clk, q => t);
W: reg generic map(width => bus_width) port map
(d => s, load => one, clr => clr, set => zero,
clk =>clk, q => r);
r
U2: binbcd port map
(B => r, P => P);
end fib_arch;
1
8
se t
clr
clk
R1
r
t
8
B
A
+
S
s
Wire up the circuit
1
8
se t
clr
W
clk
r
8
b in b cd
hunds
te n s
u n its
Fibonacci Sequence Works!
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