Computer-Aided Design of ASICs
Concept to Silicon
Victor P. Nelson
ASIC Design Flow
Behavioral
Model
Verify
Function
VHDL/Verilog
Front-End
Design
Synthesis
DFT/BIST
& ATPG
Gate-Level
Netlist
Full-custom IC
Test vectors
Standard Cell IC
& FPGA/CPLD
DRC & LVS
Verification
Verify
Function
Transistor-Level
Netlist
Physical
Layout
Map/Place/Route
Verify Function
& Timing
Back-End
Design
Verify
Timing
IC Mask Data/FPGA Configuration File
ASIC CAD tools available in ECE
 Modeling and Simulation
 Modelsim, ADVance MS/Questa, Eldo, Mach TA/ADiT (Mentor Graphics)
 Verilog-XL, NC_Verilog, Spectre (Cadence)
 Design Synthesis (digital)
 Leonardo Spectrum, Precision RTL (Mentor Graphics)
 Design Compiler (Synopsys), RTL Compiler (Cadence)
 Design for Test and Automatic Test Pattern Generation
 DFT Advisor, Fastscan, Flextest (Mentor Graphics)
 Schematic Capture & Design Integration
 Design Architect-IC (Mentor Graphics)
 Design Framework II (DFII) - Composer (Cadence)
 Physical Layout
 IC Station (Mentor Graphics)
 SOC Encounter, Virtuoso (Cadence)
 Design Verification
 Calibre (Mentor Graphics)
 Diva, Assura (Cadence)
Mentor Graphics Analog/Mixed-Signal
IC Design Flow
Mentor Graphics CAD Tools
(select from “eda” list in user-setup on the Sun network)
 ICFlow** – For custom & standard cell IC designs
 IC flow tools (Design Architect-IC, IC Station, Calibre)
 Digital/analog/mixed simulation (Modelsim,ADVance MS,Eldo,MachTA)
 HDL Synthesis (Leonardo)
 ASIC Design Kit (ADK)** Support files for various technologies
 DFT
 ATPG/DFT/BIST tools (DFT Advisor, Flextest, Fastscan)
 Modelsim** (HDL Simulation)
 FPGA (FPGA Advantage, Modelsim, Leonardo)
 *Xilinx/ISE (Xilinx FPGA/CPLD - back end design)
 *QuartusII (Altera FPGA/CPLD - back end design)
 *Ims/6.2
(IMS chip tester)
** Installed on both Solaris and Linux servers
* Vendor-Provided (Not Mentor Graphics) Tools
Mentor Graphics ASIC Design Kit (ADK)
 Technology files & standard cell libraries
 AMI: ami12, ami05 (1.2, 0.5 μm)
 TSMC: tsmc035, tsmc025, tsmc018 (0.35, 0.25, 0.18 μm)
 IC flow & DFT tool support files:
 Simulation
 VHDL/Verilog/Mixed-Signal models (Modelsim SE/ADVance MS)
 Analog (SPICE) models (Eldo/Accusim)
 Post-layout timing (Mach TA)
 Digital schematic (Quicksim II, Quicksim Pro) (except tsmc025,tsmc018)
 Synthesis to standard cells (LeonardoSpectrum)
 Design for test & ATPG (DFT Advisor, Flextest/Fastscan)
 Schematic capture (Design Architect-IC)
 IC physical design (standard cell & custom)
 Floorplan, place & route (IC Station)
 Design rule check, layout vs schematic, parameter extraction (Calibre)
We also have ADK’s for Cadence tools for several technologies
Xilinx/Altera FPGA/CPLD Design Tools
 Simulate designs in Modelsim
 Behavioral models (VHDL,Verilog)
 Synthesized netlists (VHDL, Verilog)
 Requires “primitives” library for the target technology
 Synthesize netlist from behavioral model
 Leonardo (Levels 1,2,3) has libraries for most FPGAs (ASIC-only version currently installed)
 Xilinx ISE has its own synthesis tool
 Vendor tools for back-end design
 Map, place, route, configure device, timing analysis, generate timing models
 Xilinx Integrated Software Environment (ISE)
 Altera Quartus II & Max+Plus2
 Higher level tools for system design & management
 Mentor Graphics FPGA Advantage
 Xilinx Platform Studio : SoC design, IP management, HW/SW codesign
Behavioral Design & Verification
VHDL
Verilog
SystemC
Modelsim
(digital)
VHDL-AMS
Verilog-A
Create Behavioral/RTL
HDL Model(s)
Simulate to Verify
Functionality
Synopsys Design Compiler
Leonardo Spectrum,
Xilinx ISE (digital)
ADVance MS
(analog/mixed signal)
Synthesize
Circuit
Design Constraints
Simulate to Verify
Function/Timing
Technology-Specific Netlist
to Back-End Tools
Technology
Libraries
VITAL
Library
ADVance MS
Digital, Analog, Mixed-Signal Simulation
VHDL,Verilog,
VHDL-AMS, Verilog-A,
SPICE Netlists
Working
Library
Simulation
Setup
Eldo,
Eldo RF
Analog Mach TA
(SPICE) Mach PA
Design_1
Design_2
VITAL
SPICE
Xilinx
models SIMPRIMS
IEEE 1164 Resource
Libraries
ADVance MS
EZwave
or Xelga
View Results
Input
Stimuli
Modelsim
Digital
(VHDL,Verilog)
Mixed Signal
(VHDL-AMS,
Verilog-A)
ADVance MS : mixed-signal simulation
A/D converter
digital
analog
VHDL-AMS
ADVance MS: mixed Verilog-SPICE
Verilog top
(test bench)
SPICE
subcircuit
Questa ADMS (replaces ADVance MS)
 Four simulation engines integrated for SoC designs




Questa –VHDL/Verilog/SystemC digital simulation
Eldo – analog (SPICE) simulation
ADiT – accelerated transistor-level (Fast-SPICE) simulation (replaces Mach TA)
Eldo RF
 Engines and languages can be mixed in a simulation








IEEE 1497 Standard Delay File Format (SDF)
IEEE 1076.1 VHDL-AMS
IEEE 1076 VHDL
IEEE 1364 Verilog
IEEE 1800 SystemVerilog
IEEE 1666 SystemC
Accellera standard Verilog-AMS Language
SPICE Eldo, HSPICE, and Spectre dialects.
Questa ADMS
Example: 4-bit binary counter
 VHDL model (count4.vhd)
 Create working library: vlib work
vmap work work
 Compile: vcom count4.vhd
 Simulate: vsim count4(rtl)
 ModelSim simulation-control inputs
 ModelSim “Macro” (count4_rtl.do)
 OR, VHDL testbench
 ModelSim results
 listing or waveform
-- count4.vhd
4-bit parallel-load synchronous counter
LIBRARY ieee;
USE ieee.std_logic_1164.all; USE ieee.numeric_std.all; --synthesis libraries
ENTITY count4 IS
PORT (clock,clear,enable,load_count : IN STD_LOGIC;
D: IN unsigned(3 downto 0);
Q: OUT unsigned(3 downto 0));
END count4;
ARCHITECTURE rtl OF count4 IS
SIGNAL int : unsigned(3 downto 0);
BEGIN
PROCESS(clear, clock, enable)
BEGIN
IF (clear = '1') THEN
int <= "0000";
ELSIF (clock'EVENT AND clock='1') THEN
IF (enable = '1') THEN
IF (load_count = '1') THEN
int <= D;
ELSE
int <= int + "01";
END IF;
END IF;
END IF;
END PROCESS;
Q <= int;
END rtl;
Test stimulus:
Modelsim “do” file: count4_rtl.do
add wave /clock /clear /enable /load_count /D /Q
add list /clock /clear /enable /load_count /D /Q
force /clock 0 0, 1 10 -repeat 20
force /clear 0 0, 1 5, 0 10
force /enable 0 0, 1 25
force /load_count 0 0, 1 20, 0 35, 1 330, 0 350
force /D 10#5 0, 10#9 300
run 400
Testbench: count4_bench.vhd
LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.numeric_std.all;
ENTITY count4_bench is end count4_bench;
ARCHITECTURE test of count4_bench is
component count4
PORT (clock,clear,enable,load_count : IN STD_LOGIC;
D: IN unsigned(3 downto 0);
Q: OUT unsigned(3 downto 0));
end component;
for all: count4 use entity work.count4(behavior);
signal clk : STD_LOGIC := '0';
signal clr, en, ld: STD_LOGIC;
signal din, qout: unsigned(3 downto 0);
begin
UUT: count4 port map(clk,clr,en,ld,din,qout);
clk <= not clk after 10 ns;
P1: process
begin
din <= "0101"; clr <= '1'; en <= '1'; ld <= '1';
wait for 10 ns;
clr <= '0';
wait for 20 ns;
ld <= '0';
wait for 200 ns;
end process;
end;
Alternative
to “do” file
Could also check results &
“assert” error messages
Count4 – Simulation waveform
Clear
Counting
Parallel
Load
Automated Synthesis with
Leonardo Spectrum
Technology
Synthesis
Libraries
FPGA
VHDL/Verilog
Behavioral/RTL Models
Leonardo Spectrum
(Level 3)
Design
Constraints
ASIC
ADK
AMI 0.5, 1.2
TSMC 0.35, 0.25
TechnologySpecific
Netlist
VHDL, Verilog, SDF,
EDIF, XNF
Level 1 – FPGA
Level 2 – FPGA + Timing
Level 3 – ASIC + FPGA
(we have Level 3 ASIC only)
Automated Synthesis with
Synopsys Design Compiler
Technology
Synthesis
Libraries
ASIC
VHDL/Verilog
Behavioral/RTL Models
Design Compiler (shell)
Design Vision (GUI)
DW
Synopsys
DesignWare
Component
Library
TechnologySpecific
Netlist
Verilog, SDF, DDC database,
SDC constraints, REP report
Design
Constraints
Leonardo – ASIC Synthesis Flow
Synthesize
generic gates
& modules
Read &
check HDL
Map to technology
cells & optimize
Write netlist,
SDF, reports
Leonardo synthesis procedure
Invoke leonardo
Select & load a technology library (ASIC or FPGA)
1.
2.

ASIC > ADK > TSMC 0.35 micron
Read input VHDL/Verilog file(s): count4.vhd
Enter design constraints (clock freq, delays, etc.)
Optimize for area/delays/effort level
Write output file(s)
3.
4.
5.
6.




count4_0.vhd
count4.v
count4.sdf
count4.edf
-VHDL netlist
-Verilog netlist (for IC layout)
- Standard delay format file (for timing)
- EDIF netlist (for Xilinx/Altera FPGA)
Leonardo-synthesized netlist count4_0.vhd
library IEEE; use IEEE.STD_LOGIC_1164.all;
library adk; use adk.adk_components.all; -- ADDED BY VPN
entity count4 is
port (
clock : IN std_logic ; clear : IN std_logic ; enable : IN std_logic ; load_count : IN std_logic ;
D : IN std_logic_vector (3 DOWNTO 0) ; Q : OUT std_logic_vector (3 DOWNTO 0)) ;
end count4 ;
architecture netlist of count4 is
-- rtl changed to netlist by VPN
signal Q_3_EXMPLR, Q_2_EXMPLR, Q_1_EXMPLR, Q_0_EXMPLR, nx8, nx14, nx22,
nx28, nx48, nx54, nx62, nx126, nx136, nx146, nx156, nx169, nx181,
nx183, nx185, nx187, nx189: std_logic ;
begin
Q(3) <= Q_3_EXMPLR ; Q(2) <= Q_2_EXMPLR ; Q(1) <= Q_1_EXMPLR ; Q(0) <= Q_0_EXMPLR ;
Q_0_EXMPLR_EXMPLR : dffr port map ( Q=>Q_0_EXMPLR, QB=>OPEN, D=>nx126, CLK=>clock, R=>clear);
ix127 : mux21_ni port map ( Y=>nx126, A0=>Q_0_EXMPLR, A1=>nx8, S0=>enable );
ix9 : oai21 port map ( Y=>nx8, A0=>load_count, A1=>Q_0_EXMPLR, B0=>nx169 );
ix170 : nand02 port map ( Y=>nx169, A0=>D(0), A1=>load_count);
Q_1_EXMPLR_EXMPLR : dffr port map ( Q=>Q_1_EXMPLR, QB=>OPEN, D=>nx136,
CLK=>clock, R=>clear);
ix137 : mux21_ni port map ( Y=>nx136, A0=>Q_1_EXMPLR, A1=>nx28, S0=> enable);
ix29 : ao22 port map ( Y=>nx28, A0=>D(1), A1=>load_count, B0=>nx14, B1=> nx22);
ix15 : or02 port map ( Y=>nx14, A0=>Q_0_EXMPLR, A1=>Q_1_EXMPLR);
ix23 : aoi21 port map ( Y=>nx22, A0=>Q_1_EXMPLR, A1=>Q_0_EXMPLR, B0=> load_count);
Q_2_EXMPLR_EXMPLR : dffr port map ( Q=>Q_2_EXMPLR, QB=>OPEN, D=>nx146, CLK=>clock, R=>clear);
ix147 : mux21_ni port map ( Y=>nx146, A0=>Q_2_EXMPLR, A1=>nx48, S0=> enable);
ix49 : oai21 port map ( Y=>nx48, A0=>nx181, A1=>nx183, B0=>nx189);
ix182 : aoi21 port map ( Y=>nx181, A0=>Q_1_EXMPLR, A1=>Q_0_EXMPLR, B0=> Q_2_EXMPLR);
ix184 : nand02 port map ( Y=>nx183, A0=>nx185, A1=>nx187);
ix186 : inv01 port map ( Y=>nx185, A=>load_count);
ix188 : nand03 port map ( Y=>nx187, A0=>Q_2_EXMPLR, A1=>Q_1_EXMPLR, A2=> Q_0_EXMPLR);
ix190 : nand02 port map ( Y=>nx189, A0=>D(2), A1=>load_count);
Q_3_EXMPLR_EXMPLR : dffr port map ( Q=>Q_3_EXMPLR, QB=>OPEN, D=>nx156, CLK=>clock, R=>clear);
ix157 : mux21_ni port map ( Y=>nx156, A0=>Q_3_EXMPLR, A1=>nx62, S0=> enable);
ix63 : mux21_ni port map ( Y=>nx62, A0=>nx54, A1=>D(3), S0=>load_count);
ix55 : xnor2 port map ( Y=>nx54, A0=>Q_3_EXMPLR, A1=>nx187);
end netlist ;
// Verilog description for cell count4, LeonardoSpectrum Level 3, 2005a.82
module count4 ( clock, clear, enable, load_count, D, Q ) ;
input clock ;
input clear ;
input enable ;
input load_count ;
input [3:0]D ;
output [3:0]Q ;
wire nx8, nx14, nx22, nx28, nx48, nx54, nx62, nx126, nx136, nx146, nx156, nx169, nx181, nx183, nx185, nx187, nx189;
wire [3:0] \$dummy ;
dffr Q_0__rename_rename (.Q (Q[0]), .QB (\$dummy [0]), .D (nx126), .CLK (clock), .R (clear)) ;
mux21_ni ix127 (.Y (nx126), .A0 (Q[0]), .A1 (nx8), .S0 (enable)) ;
oai21 ix9 (.Y (nx8), .A0 (load_count), .A1 (Q[0]), .B0 (nx169)) ;
nand02 ix170 (.Y (nx169), .A0 (D[0]), .A1 (load_count)) ;
dffr Q_1__rename_rename (.Q (Q[1]), .QB (\$dummy [1]), .D (nx136), .CLK (clock), .R (clear)) ;
mux21_ni ix137 (.Y (nx136), .A0 (Q[1]), .A1 (nx28), .S0 (enable)) ;
ao22 ix29 (.Y (nx28), .A0 (D[1]), .A1 (load_count), .B0 (nx14), .B1 (nx22) ) ;
or02 ix15 (.Y (nx14), .A0 (Q[0]), .A1 (Q[1])) ;
aoi21 ix23 (.Y (nx22), .A0 (Q[1]), .A1 (Q[0]), .B0 (load_count)) ;
dffr Q_2__rename_rename (.Q (Q[2]), .QB (\$dummy [2]), .D (nx146), .CLK (clock), .R (clear)) ;
mux21_ni ix147 (.Y (nx146), .A0 (Q[2]), .A1 (nx48), .S0 (enable)) ;
oai21 ix49 (.Y (nx48), .A0 (nx181), .A1 (nx183), .B0 (nx189)) ;
aoi21 ix182 (.Y (nx181), .A0 (Q[1]), .A1 (Q[0]), .B0 (Q[2])) ;
nand02 ix184 (.Y (nx183), .A0 (nx185), .A1 (nx187)) ;
inv01 ix186 (.Y (nx185), .A (load_count)) ;
nand03 ix188 (.Y (nx187), .A0 (Q[2]), .A1 (Q[1]), .A2 (Q[0])) ;
nand02 ix190 (.Y (nx189), .A0 (D[2]), .A1 (load_count)) ;
dffr Q_3__rename_rename (.Q (Q[3]), .QB (\$dummy [3]), .D (nx156), .CLK (clock), .R (clear)) ;
mux21_ni ix157 (.Y (nx156), .A0 (Q[3]), .A1 (nx62), .S0 (enable)) ;
mux21_ni ix63 (.Y (nx62), .A0 (nx54), .A1 (D[3]), .S0 (load_count)) ;
xnor2 ix55 (.Y (nx54), .A0 (Q[3]), .A1 (nx187)) ;
endmodule
Post-synthesis simulation
(Leonardo-generated netlist)
 Verify synthesized netlist matches behavioral model
 Create library of std cell simulation primitives:
>vlib adk
>vcom $ADK/technology/adk.vhd
>vcom $ADK/technology/adk_comp.vhd
VITAL models
of ADK std cells
 Insert library/package declaration into netlist
library adk;
use adk.adk_components.all;
 Simulate in Modelsim, using “do file” or test bench from original
behavioral simulation
 results should match
Post-synthesis timing analysis
 Leonardo can generate SDF (std. delay format) file with technology-
specific, VITAL-compliant timing parameters (from cell library)
(CELLTYPE "dffr")
(INSTANCE Q_0_EXMPLR_EXMPLR)
(DELAY
(ABSOLUTE
(PORT D (::0.00) (::0.00))
(PORT CLK (::0.00) (::0.00))
(PORT R (::0.00) (::0.00))
(IOPATH CLK Q (::0.40) (::0.47))
(IOPATH R Q (::0.00) (::0.55))
(IOPATH CLK QB (::0.45) (::0.36))
(IOPATH R QB (::0.53) (::0.00))))
(TIMINGCHECK
(SETUP D (posedge CLK) (0.47))
(HOLD D (posedge CLK) (-0.06))))
Delays lumped
at pins
Path delays
(min:typ:max)
Constraints
VITAL Model (1)
library IEEE; use IEEE.STD_LOGIC_1164.all;
use IEEE.VITAL_Primitives.all; use IEEE.VITAL_Timing.all;
entity and02 is
generic (
tipd_A0 : VitalDelayType01Z := VitalZeroDelay01Z;
tipd_A1 : VitalDelayType01Z := VitalZeroDelay01Z;
tpd_A0_Y : VitalDelayType01Z := VitalZeroDelay01Z;
tpd_A1_Y : VitalDelayType01Z := VitalZeroDelay01Z
);
port (
A0 : in STD_LOGIC;
A1 : in STD_LOGIC;
Y : out STD_LOGIC
);
attribute VITAL_LEVEL0 of and02 : entity is TRUE;
end and02;
Delays from
SDF file
VITAL Model (2)
architecture and02_arch of and02 is
attribute VITAL_LEVEL1 of and02_arch : architecture is TRUE;
signal A0_ipd : STD_LOGIC := 'X';
signal A1_ipd : STD_LOGIC := 'X';
begin
WireDelay : Block
begin
Determine input
VitalWireDelay (A0_ipd, A0, tipd_A0);
pin delays
VitalWireDelay (A1_ipd, A1, tipd_A1);
end Block;
VitalBehavior : Process (A0_ipd, A1_ipd)
VARIABLE INT_RES_0 : STD_LOGIC := 'X';
VARIABLE GlitchData_Y : VitalGlitchDataType;
begin
-- FUNCTIONALITY SECTION -INT_RES_0 := VitalAnd2 (A0_ipd, A1_ipd);
Ideal (zero-delay)
AND function
VITAL Model (3)
-PATH DELAY SECTION
-VitalPathDelay01Z (
OutSignal => Y,
Determine delay along
OutSignalName => "Y",
each input-output path
OutTemp => INT_RES_0,
Paths => (
0 => ( InputChangeTime => A0_ipd'LAST_EVENT,
PathDelay => tpd_A0_Y,
PathCondition => TRUE
),
1 => ( InputChangeTime => A1_ipd'LAST_EVENT,
PathDelay => tpd_A1_Y,
PathCondition => TRUE
)
),
GlitchData => GlitchData_Y,
Mode => OnDetect,
MsgOn => TRUE, Xon => TRUE,
MsgSeverity => WARNING
Design for test & test generation
 Consider test during the design phase
 Test design more difficult after design frozen
 Basic steps:
 Design for test (DFT) – insert test points, scan chains, etc. to
improve testability
 Insert built-in self-test (BIST) circuits
 Generate test patterns (ATPG)
 Determine fault coverage (Fault Simulation)
DFT & test design flow
Memory
& Logic
BIST
Boundary
Scan
Internal
Scan Design
ATPG
DFTadvisor/FastScan Design Flow
count4.vhd
Leonardo
DFT/ATPG
Library:
count4_0.vhd
count4.v
count4_scan.v
adk.atpg
Source: FlexTest Manual
ASIC DFT Flow
Synthesized VHDL/Verilog Netlist
ATPG Library
DFT Advisor
Insert Internal
Scan Circuitry
VHDL/Verilog
Netlist With
Scan Elements
Fastscan/
Flextest
Generate/Verify
Test Vectors
Test Pattern File
adk.atpg
Example DFTadvisor session
 Invoke:
 dftadvisor –verilog count4.v –lib $ADK/technology/adk.atpg
 Implement scan with defaults:
(full scan, mux-DFF scan elements)
 set system mode setup
 analyze control signals –auto
 set system mode dft
 run
 insert test logic
 write netlist count4_scan.v –verilog
 write atpg setup count4_scan
(creates count4_scan.dofile for ATPG in Fastscan)
count4 – without scan design
count4 – scan inserted by DFTadvisor
ATPG with FastScan
(full-scan circuit)
 Invoke:
 fastscan –verilog count4.v –lib $ADK/technology/adk.atpg
 Generate test pattern file in FastScan:
 dofile count4_scan.dofile (defines scan path & procedure) **
 set system mode atpg
 create patterns –auto
(generate test patterns)
 save patterns
** “count4_scan.dofile” was created by DFTadvisor
Test file: scan chain definition and
load/unload procedures
scan_group "grp1" =
scan_chain "chain1" =
scan_in = "/scan_in1";
scan_out = "/output[3]";
length = 4;
end;
procedure shift "grp1_load_shift" =
force_sci "chain1" 0;
force "/clock" 1 20;
force "/clock" 0 30;
period 40;
end;
procedure shift "grp1_unload_shift" =
measure_sco "chain1" 10;
force "/clock" 1 20;
force "/clock" 0 30;
period 40;
end;
procedure load "grp1_load" =
force "/clear" 0 0;
force "/clock" 0 0;
force "/scan_en" 1 0;
apply "grp1_load_shift" 4 40;
end;
procedure unload "grp1_unload" =
force "/clear" 0 0;
force "/clock" 0 0;
force "/scan_en" 1 0;
apply "grp1_unload_shift" 4 40;
end;
end;
Generated scan-based test
// send a pattern through the scan chain
CHAIN_TEST =
pattern = 0;
apply "grp1_load" 0 =
(use grp1_load procedure)
chain "chain1" = "0011"; (pattern to scan in)
end;
apply "grp1_unload" 1 =
(use grp1_unload procedure)
chain "chain1" = "1100"; (pattern scanned out)
end;
end;
// one of 14 patterns for the counter circuit
pattern = 0;
(pattern #)
apply "grp1_load" 0 =
(load scan chain)
chain "chain1" = "1000"; (scan-in pattern)
end;
force "PI" "00110" 1;
(PI pattern)
measure "PO" "0010" 2;
(expected POs)
pulse "/clock" 3;
(normal op. cycle)
apply "grp1_unload" 4 =
(read scan chain)
chain "chain1" = "0110"; (expected pattern)
end;
ASIC Physical Design (Standard Cell)
(can also do full custom layout)
Component-Level Netlist (EDDM format)
Std. Cell
Layouts
Floorplan
Chip/Block
Libraries
Mentor Graphics
“IC Station”
(adk_ic)
ICblocks
Process Data
Place & Route
Std. Cells
Design Rules
Generate
Mask Data
Design Rule
Check
Calibre
IC Mask Data
Backannotate
Schematic
Calibre
Layout vs.
Schematic
Check
Calibre
Mach TA/Eldo Simulation Model
Cell-Based IC
I/O pads
Cell-Based Block
Basic standard
Cell layout
Source: Weste “CMOS VLSI Design”
Preparation for Layout
Use Design Architect-IC to convert Verilog netlist to Mentor
Graphics EDDM netlist format
1.


Invoke Design Architect-IC (adk_daic)
On menu bar, select File > ImportVerilog



Netlist file: count4.v (theVerilog netlist)
Output directory: count4 (for the EDDM netlist)
Mapping file $ADK/technology/adk_map.vmp
Open the generated schematic for viewing
2.



Click Schematic in DA-IC palette
Select schematic in directory named above (see next slide)
Click Update LVS in the schematic palette to create a netlist to be used later by
“Calibre”
Create design viewpoints for ICstation tools
3.

adk_dve count4 –t tsmc035
(V.P’s: layout, lvs, sdl, tsmc035)
Can also create gate/transistor schematics directly in DA-IC using
components from the ADK library
DA-IC generated schematic
Eldo simulation from DA-IC
 Run simulations from within DA-IC
 Eldo, ADVance MS, Mach TA
 DA-IC invokes a “netlister” to create a circuit model from the
schematic
 SPICE model for Eldo & Mach TA
 Eldo analyses, forces, probes, etc. same as SPICE
 View results in EZwave
Eldo input and output files
-Netlist
-Simulation cmds
-Stimulus
SPICE “circuit” file generated by DA-IC
From ADK
library
Force values (created interactively)
SPICE netlist for modulo7 counter
Force functions (1)
 DC value
 Vsigname A 0 DC 5
V indicates
voltage
Force
name
Between circuit nodes
A and GND (node 0)
Value (volts)
Force functions (2)
 Pulse/square wave
 Vsigname B 0 pulse 0 5 0 0.1N 0.1N 20N 40N
Nodes
Initial
Pulsed
Voltage
Voltage
v1
v2
tp
v2
v1
td
tr tw tf
Rise Fall
time time
tr
tf
Pulse Period
width tp
tw
Delay from start of period
for waveform to begin - td
Force functions (3)
 Pattern wave (for logic 0 & 1 values)
Vname B 0 pattern 5 0 5n 0.1n 0.1n 10n 011010 R
Bit pattern
Rise & Fall
Time between
Logic 1 & 0
voltages Delay tochanges
Duration of
bit value
waveform
Between circuit
Nodes B & GND
(node 0)
begin
1
0
delay
1
1
0
pattern
0
Repeat
the pattern
(optional)
Eldo simulation of modulo7 counter
(transient analysis)
Create a std-cell based logic block in IC
Station
 Invoke: adk_ic
 In IC Station palette, select: Create Cell
 Cell name: count4
 Attach cell library: $ADK/technology/ic/process/tsmc035
 Process data: $ADK/technology/ic/process/tsmc035
 Design rules: $ADK/technology/ic/process/tsmc035.rules
 Angle mode: 45
 Cell type: block
 Select With connectivity (use imported schematic)
 EDDM schematic viewpoint: count4/layout
 Logic loading options: flat
Create Cell dialog box
Auto-”floorplan” the block
place & route > autofp
Auto-place the std cells
Autoplc > StdCel
Auto-place ports (signal connections on cell boundaries)
Autoplc > Ports
AutoRoute all nets
(hand-route any unrouted “overflows”)
Then: Add > Port Text to copy port names from schematic – for Calibre
Layout design rule check (DRC)
 Technology-specific design rules specify minimum sizes,
spacing, etc. of features to ensure reliable fabrication
 Design rules file specified at startup
Ex. tsmc035.rules
 From main palette, select ICrules
 Click Check and then OK in prompt box
(can optionally select a specific area to check)
 Rules checked in numeric order
Common errors detected by DRC
 To fix, click on First in palette to highlight first error
 Error is highlighted in the layout
 Click View to zoom in to the error (see next)
 Example: DRC9_2: Metal2 spacing = 3L
 Fix by drawing a rectangle of metal2 to fill in the gap between
contacts that should be connected
 Click Next to go to next error, until all are fixed
NOTE: There can be no DRC errors if MOSIS is to
fabricate the chip – they will run their own DRC.
Sample error: DRC9_2 metal2 spacing = 3L
Draw
rectangle
of metal2
to fill gap
It also called contact-to-contact metal 2 spacing DRC9_2 error
Layout vs schematic check using
Calibre Interactive LVS
 Compare extracted transistor-level netlist against netlist saved
in DA-IC
 From ICstation menu: Calibre > Run LVS
 In popup, Calibre location: $MGC_HOME/../Calibre
 Rules: $ADK/technology/ic/process/tsmc035.calibre.rules
 Input: count4.src.net (previously created in DA-IC)
 H-cells: $ADK/technology/adk.hcell (hierarchical cells)
 Extracted file: count4.lay.net
Post-layout parameter extraction via
Calibre Interactive PEX
 Extract Spice netlist, including parasitic RC
 Simulate in Eldo or MachTA
 ICstation menu: Calibre>Run PEX
 Options similar to Calibre LVS
 Extraction options:
 lumped C + coupling cap’s
 distributed RC
 distributed RC + coupling cap’s
 Output file: count4.pex.netlist
Post-layout simulation with MachTA
 MachTA is an accelerated Spice simulator
 Digital & mixed-signal circuits
 Analyze timing effects pre- and post-layout
 SPICE netlists with parasitic R/C
 Execute test vector file to verify functionality
 Algorithms support large designs
 Partition design, simulate only partitions with changes
 Combine time-driven & event-driven operation
 Solves linearized models using a proprietary high-performance,
graph-theory based, matrix solution algorithm
Mach TA flow diagram
SPICE
netlist
$ADK/technology/mta/tsmc035
Prepare Calibre-extracted netlist for Mach
TA (file.pex.netlist)
 In file.pex.netlist, insert model definitions and VDD/GND voltage source
functions after comment header:
* File: m7.pex.netlist
* Created: Thu Nov 15 15:25:56 2007
* Program "Calibre xRC"
* Version "v2005.2_9.14"
.model n nmos
.model p pmos
Vvdd VDD 0 5
Vgnd GND 0 0
 Delete (or comment out with * in 1st column) .subcircuit statement and
any continuation lines (for long statement):
*.subckt modulo7 CLK Q[1] CLEARBAR I[1] Q[0] I[0] Q[2]
*+ L_CBAR I[2] GND VDD
 Change .ends to .END near end of file
Post-layout simulation with Mach TA
 Invoke Mach TA:
ana - command file to initialize Anacad SW
mta –ezw –t $ADK/technology/mta/tsmc035 count4.sp
Transistor calibration files for this technology
Generate waveform database & display in EZwave
Netlist, modified as
on previous slide
Other options:
-do file (execute commands from file.do – instead of design.spdo
-donot (run without simulating – compile only)
-b
(run in batch mode – no GUI – output to console)
Sample Mach TA “dofile”
(transient analysis)
plot v(clk) v(q[2]) v(q[1]) v(q[0])
Signals to observe in EZwave
measure rising TRIG v(clk) VAL=2.5v RISE=1 TARG v(q[0]) VAL=2.5v
l load
l reset
h count
Measure time from rising edge of clk (TRIGger)
l clk
to 1st rising edge of q[0] (TARGet) - voltages
run 5 ns
h reset
h clk
Drive signals low/high (Lsim format)
run 5 ns
l clk
Simulate for 5 ns
run 5 ns
h clk
run 5 ns
Command to execute: dofile file.do
EZwave waveform viewer
(results for previous dofile)
Double-click
signal name
to display.
Alternative Mach TA “dofile”
(same result as previous example)
plot v(clk) v(q[2]) v(q[1]) v(q[0])
measure rising TRIG v(clk) VAL=2.5v RISE=1 TARG v(q[0])
VAL=2.5v
vpulseVclk clk 0 pulse(0 3.3 10n .05n .05n 10n 20n)
v-levels delay rise fall width period
l load
l reset
Nodes to which
h count
source connected
Periodic pulses
run 5 ns
h reset
Voltage source name
run 200 ns
Mach TA – test vector file
 Verify design functionality/behavior
 apply test vectors
 capture outputs
 compare outputs to expected result
 use vectors/outputs from behavioral simulation
 Command to execute a test vector file:
run –tvend tvfile.tv
test vector file (next slide)
Test vector file format
# Test vector file for modulo7 counter
CODEFILE
UNITS ps
RISE_TIME 50
signal order within vectors
Header
FALL_TIME 50
INPUTS clk,reset,load,count,i[2],i[1],i[0];
OUTPUTS q[2] (to=max),q[1] (to=max),q[0] (to=max);
CODING(ROM)
Vector format
RADIX <11113>3;
@0 <01105>X;
Sample 5 fs before next vector
@2000 <00105>0;
@7000 <01105>0;
@10000 <11105>5;
@20000 <01015>5;
Vectors: @time <input_vector>expected_output
@30000 <11015>6;
@40000 <01015>6;
@50000 <11015>0;
@60000 <01015>0;
…..
END
Test vectors derived from behavioral simulation results
Behavioral simulation listing
Corresponding Mach TA test vector file
Alternate test vector file
(clock generated separately by voltage source)
vpulse vclk clk 0
pulse(0 3.3 10n .5n .5n 10n 20n)
Can mix other simulation
commands with test vector
application.
Mach TA has been replaced by ADiT
• Fast-SPICE simulator
• Analog & mixed-signal
• 10X to 100X faster than
other SPICE simulators
• Integrated with Questa
Top level layout design flow**
 Create a symbol for each core block (adk_daic)
 Create a chip-level schematic from core blocks and pads
(adk_daic)
 Generate design viewpoints (adk_dve)
 Create a layout cell for the chip(adk_ic)





Place core logic blocks from the schematic
Generate a pad frame
Move/alter core blocks to simplify routing
Route pads to core blocks
Design rule check & fix problems
 Generate mask data
** Refer to on-line tutorials by Yan/Xu and by Dixit/Poladia
Chip-level schematic (1)
 Generate a symbol for each “core” logic block
 In DA-IC, open the schematic (eg. modulo7)
 Select: Miscellaneous > Generate Symbol
 Add “phy_comp” property to the symbol
 Select the body of the symbol
 From the popup menu: Properties > Add
 Enter property name: phy_comp
 Enter property value: mod7b
(layout cell name for the block created in IC Station)
 Check & save
Example on next slide
Symbol with phy_comp property
Layout
cell is
“mod7b”
for logic
schematic
“modulo7”
Chip-level schematic (2)
 In DA-IC, create a schematic for the chip
 Instantiate core blocks
 Menu pallete: Add > Instance
 Select and place generated symbol
 Add pads from ADK Library>Std. Cells>Pads >tsmc035 : In, Out,
BiDir, VDD, GND
 Wire pads to logic blocks and connectors
 Assign pin numbers, if known
 Change pad instance name to PINdd (dd = 2-digit pin #)
 Check & save
 Create design viewpoints with adk_dve
Example on next slide
Assigning PAD pin numbers
Change instance name property on pads to PINxx
xx = 2-digit pin number (01 – 40 for Tiny Chip package)
Place pad on
chip pin 01
Default
instance
names
Top-level schematic for “modulo7” chip
VDD/GND
Pads
Hierarchical
connectors
on “Pad” pins
Instance
name =
PINxx
(chip pin #)
Core block
Wire block I/O pins
to pad signal pins
Chip layout
 Start IC Station (adk_ic) & create a new layout cell
 enter cell name
 logic source is “layout” viewpoint of chip schematic
 same library, process file, rules file, and options as standard cell layout
 Open the schematic
 ADK Edit menu: Logic Source > Open
 In the schematic, select all core cells (but not pads)
 Place the cells: Place > Inst
 Generate the pad frame
 Top menu bar: ADK > Generate Padframe > tsmc035
Chip layout (2)
 Move, rotate, flip core logic cells as desired to make routing
easier
 BUT - DO NOT EDIT OR MOVE PAD CELLS
 Autoroute all connections
 Select autoroute all on P&R menu
 Click “options” on prompt bar, and unselect “Expand Channels”
(prevents pads from being moved)
 Add missing VDD/GND wires, if necessary
 Autorouter might only route 1 VDD/GND wire, even if multiple
VDD/GND pads
 Manually add others: Objects>Add>Path
 VDD/GND net width = 50
 VDD/GND net vias = 6x6 (copy an existing via)
Modulo-7 counter in pad frame
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Mentor Graphics ASIC Design Flow