Algorithms for VLSI Design
Automation
Instructor D. Zhou
[email protected]
Phone: 972 883 4392
Office: ECN 4.610
Outline
History and the road map
Traditional design flow
Physical design fundamentals
Performance issues
System on chip
2015/10/3
Dragon Star Shot Course
2
History and the road map
The history of IC



The invention of transistor
The invention of integrated circuit
IC has changed our life
Moore’s Law

IC performance and complexity have been
doubled in every two years
Road Map
2015/10/3
Dragon Star Shot Course
3
The invention of transistor
John Bardeen, Walter Brattain & Wiliam
Shockley in vented “The first transistor”
in 1947.
2015/10/3
Dragon Star Shot Course
4
The invention of integrated circuit
Jack Kilby & Robert Noyce inveted “The
Integrated Circuit” in 1958.
2015/10/3
Dragon Star Shot Course
5
Moore’s Law

In 1965, Gordon Moore predicted that the number of
transistors that can be integrated on a die would double
every 18 to 14 months (i.e., grow exponentially with
time).

Amazingly visionary – million transistor/chip barrier was
crossed in the 1980’s.




2300 transistors, 1 MHz clock (Intel 4004) - 1971
16 Million transistors (Ultra Sparc III)
42 Million, 2 GHz clock (Intel P4) - 2001
140 Million transistor (HP PA-8500)
CSE477 L01 Introduction.6
Irwin&Vijay, PSU, 2002
Intel 4004 Microprocessor
CSE477 L01 Introduction.7
Irwin&Vijay, PSU, 2002
Intel Pentium (IV) Microprocessor
CSE477 L01 Introduction.8
Irwin&Vijay, PSU, 2002
Moore’s Law in Microprocessors
Transistors on lead microprocessors double every 2 years
1000
2X growth in 1.96 years!
Transistors (MT)
100
10
486
1
386
286
0.1
0.01
8086
8080
8008
4004
8085
0.001
1970
CSE477 L01 Introduction.9
P6
Pentium® proc
1980
1990
Year
Courtesy, Intel
2000
2010
Irwin&Vijay, PSU, 2002
Evolution in DRAM Chip Capacity
human memory
human DNA
100000000
10000000
64,000,000
4X growth every 3 years!
16,000,000
Kbit capacity/chip
4,000,000
1000000
1,000,000
book
100000
256,000
64,000
16,000
10000
4,000
1000
1,000
256
100
64
10
1980
0.07 m
0.1 m
0.13 m
0.18-0.25 m
0.35-0.4 m
0.5-0.6 m
0.7-0.8 m
1.0-1.2 m
encyclopedia
2 hrs CD audio
30 sec HDTV
1.6-2.4 m
page
1983
1986
1989
1992
1995
1998
2001
2004
2007
2010
Year
CSE477 L01 Introduction.10
Irwin&Vijay, PSU, 2002
Die Size Growth
Die size grows by 14% to satisfy Moore’s Law
Die size (mm)
100
P6
486 Pentium ® proc
10
386
8080
8008
4004
8086
8085
286
~7% growth per year
~2X growth in 10 years
1
1970
CSE477 L01 Introduction.11
1980
1990
Year
Courtesy, Intel
2000
2010
Irwin&Vijay, PSU, 2002
Clock Frequency
Lead microprocessors frequency doubles every 2 years
10000
2X every 2 years
Frequency (Mhz)
1000
P6
Pentium ® proc
100
486
10
8085
1
0.1
1970
CSE477 L01 Introduction.12
8086 286
386
8080
8008
4004
1980
1990
Year
Courtesy, Intel
2000
2010
Irwin&Vijay, PSU, 2002
Power Dissipation
Lead Microprocessors power continues to increase
Power (Watts)
100
P6
Pentium ® proc
10
8086 286
1
8008
4004
486
386
8085
8080
0.1
1971
1974
1978
1985
1992
2000
Year
Power delivery and dissipation will be prohibitive
CSE477 L01 Introduction.13
Courtesy, Intel
Irwin&Vijay, PSU, 2002
Power Density
Power Density (W/cm2)
10000
Rocket
Nozzle
1000
Nuclear
Reactor
100
8086
Hot Plate
10 4004
P6
8008 8085
Pentium® proc
386
286
486
8080
1
1970
1980
1990
Year
2000
2010
Power density too high to keep junctions at low temp
CSE477 L01 Introduction.14
Courtesy, Intel
Irwin&Vijay, PSU, 2002
Technology Trend
International Technology Roadmap
for Semiconductors (ITRS)
Production year
2002 2003 2004 2005 2006 2007
MPU Gate length (nm) 75
65
53
45
40
35
Clock (GHz)
2.3
3.1
4.0
5.2
5.6
6.7
Metal layers
8
8
8
9
9
9
Supply voltage (V)
1.0
1.0
1.0
0.9
0.9
0.7
Microelectronics Department, Fudan University
Traditional design flow
Traditional design flow (see slides designflow)
What has not been addressed in depth



2015/10/3
Understand application
Architecture synthesis
Verification is not complete
Dragon Star Shot Course
16
2015/10/3
Dragon Star Shot Course
17
Microelectronics Department, Fudan University
Performance issues
Speed
Noise
Clock distribution
Power distribution
Low power
2015/10/3
Dragon Star Shot Course
19
SOC
A low cost solution
Challenges





2015/10/3
Modeling
Simulation
Mixed signal
Different processing
Timing
Dragon Star Shot Course
20
Agenda
Dealing with technology



Masks
Front-end manufacturing
Back-end manufacturing
Application requirements
Putting it all together
2015/10/3
Dragon Star Shot Course
21
Agenda
Dealing with technology



Masks
Front-end manufacturing
Back-end manufacturing
Application requirements
Putting it all together
2015/10/3
Dragon Star Shot Course
22
Semiconductor Process Flow
Systems
$1050B
• Computers
• Communications
• Consumer
• Industrial, Military…
EDA
Design
$3.6B
EDA
$2.7B
Comp
Platforms
Mask Data
Masks
Front-End Manufacturing $24B
Embedded SW
$0.8B
IP
$0.9B
Semiconductors $119B
• Micros, DSP
• Memory
• ASIC, ASSP
• Analog, Discrete
Masks
$2.8B
• Manufacturing $2.3B
• Tools
$0.5B
$45B
$25B
$25B
$25B
Wafer
$4B
• Process Auto
• Lithography
• Etch/Doping
• Diffusion
• Deposition
• Other (CMP, Ion,
Photoresist, etc.)
$1B
$6B
$6B
$1B
$5B
$5B
Back-End Manufacturing $6B
Chips
2015/10/3
Market size for 2001 Sources: Thomas WeiselDragon
Dataquest,
ICI, Shot
Synopsys
Estimates
Star
Course
• Bonding
• Packaging
• Test equipment
$1B
$2B
$3B
23
Exploding Mask Costs
Year
Node
Cost
Data
1999
2002
.18µm
.13µm
$200-400K $500K-1M
16GB
64GB
2004
.9µm
$800K1.2M
256GB
2007
.065µm
$1-2M
1024GB
Raster scan patterning exposure time for a
110mm x 110 mm mask is 6.5 hrs and 20 hrs with
fine granularities (60nm vs. 120nm pixel size)
Largest cost contribution to mask making is mask
exposure time (capital cost ~$20M)
RET is being absorbed by CAD vendors into
layout verification / tape-out suites.
RET may move up Dragon
into Star
routing,
placement
Shot Course
Source:2015/10/3
Thomas Weisel Partners
24
Front-End Processing
Systems
$1050B
• Computers
• Communications
• Consumer
• Industrial, Military…
EDA
Design
$3.6B
EDA
$2.7B
Comp
Platforms
Masks
Front-End Manufacturing $24B
Embedded SW
$0.8B
IP
$0.9B
Semiconductors $119B
• Micros, DSP
• Memory
• ASIC, ASSP
• Analog, Discrete
Mask Data
Masks
$2.8B
• Manufacturing $2.3B
• Tools
$0.5B
$45B
$25B
$25B
$25B
Wafer
$4B
• Process Auto
• Lithography
• Etch/Doping
• Diffusion
• Deposition
• Other (CMP, Ion,
Photoresist, etc.)
$1B
$6B
$6B
$1B
$5B
$5B
Back-End Manufacturing $6B
Chips
• Bonding
• Packaging
• Test equipment
$1B
$2B
$3B
Market size for 2001 Sources: Thomas Weisel Dataquest, ICI, Synopsys Estimates
2015/10/3
Dragon Star Shot Course
25
Interconnect
Exploding number of metal layers, mask
cost
Large number of vias diminishes yield
Increasingly complex process rules • Include pattern density

Via
& shape management
Stack
in layout, extraction
Multiple
• Limit vias / multiple
Array
vias
 Metal
Min, max, spacing, width
 Antenna
 Signal EM
Number of vias for a given load,
2015/10/3
Dragon Star Shot Course
frequency
26
CD Variation Across a Wafer
LineWidth [nm]
Wafer Map for No-DPC Horizontal Isolated
Structures
x 10-7
2.3
2.2
2.1
2.0
1.9
1.8
150
60
100
50
Wafer Y
0
0
20
40
Wafer Y
Incorporate analysis of timing
variation into extraction &
static timing analysis
Source:2015/10/3
Spanos, UCB
Dragon Star Shot Course
27
Physical design for Yield /
Reliability
Aggressive via minimization in routing
Insert redundant vias
Space / Width
Limit Current Density
2015/10/3
Dragon Star Shot Course
28
Systems
Back-End: Assembly and
Packaging Masks
$1050B
• Computers
• Communications
• Consumer
• Industrial, Military…
EDA
Design
$3.6B
EDA
$2.7B
Comp
Platforms
Masks
Front-End Manufacturing $24B
Embedded SW
$0.8B
IP
$0.9B
Semiconductors $119B
• Micros, DSP
• Memory
• ASIC, ASSP
• Analog, Discrete
Mask Data
$2.8B
• Manufacturing $2.3B
• Tools
$0.5B
$45B
$25B
$25B
$25B
Wafer
$4B
• Process Auto
• Lithography
• Etch/Doping
• Diffusion
• Deposition
• Other (CMP, Ion,
Photoresist, etc.)
$1B
$6B
$6B
$1B
$5B
$5B
Back-End Manufacturing $6B
Chips
• Bonding
• Packaging
• Test equipment
$1B
$2B
$3B
Market size for 2001 Sources: Thomas Weisel Dataquest, ICI, Synopsys Estimates
2015/10/3
Dragon Star Shot Course
29
Assembly and Packaging
The chip is assembled into a package that
provides the contact leads for the chip. A
wire-bonding machine attaches wires to
the leads of the package; or this is
achieved using flip chip die attach.
Modern packages can be very complex
The package is the bridge between silicon
and system
Differentiator: Performance, form factor, fit,
thermal conduction, reliability, and cost
2015/10/3
Dragon Star Shot Course
30
IC / Package Co-Design for Flip
Chip
Lid
Chip
Package
Pwr, Gnd
Signal
Solder
balls
Board
2015/10/3
• Design
• Analyis
• Package feasibility
• Extraction RLC
• Simulation Spice • Bump patterning, assignment
• P/G assignment
• Driver placement
• Routing
Dragon Star Shot Course
31
SoC Packaging
Trends by 2005



Cost: 0.29¢ to 2.28¢ / pin
Pins / package: 120 – 3000
Performance: 600 MHz – 2GHz
Integrating complete (sub)systems on a chip
is often driven by packaging


Less I/O, power, area, & cost
Higher on-chip speed, reliability
Complex packages and Multi-chip modules
that require routing and analysis, driven by
mixed-signal,
RF, memory integration
2015/10/3
Dragon Star Shot Course
32
Back-End: Testing and Automatic
Test Equipment
Systems
$1050B
• Computers
• Communications
• Consumer
• Industrial, Military…
EDA
Design
$3.6B
EDA
$2.7B
Comp
Platforms
Masks
Front-End Manufacturing $24B
Embedded SW
$0.8B
IP
$0.9B
Semiconductors $119B
• Micros, DSP
• Memory
• ASIC, ASSP
• Analog, Discrete
Mask Data
Masks
$2.8B
• Manufacturing $2.3B
• Tools
$0.5B
$45B
$25B
$25B
$25B
Wafer
$4B
• Process Auto
• Lithography
• Etch/Doping
• Diffusion
• Deposition
• Other (CMP, Ion,
Photoresist, etc.)
$1B
$6B
$6B
$1B
$5B
$5B
Back-End Manufacturing $6B
Chips
• Bonding
• Packaging
• Test equipment
$1B
$2B
$3B
Market size for 2001 Sources: Thomas Weisel Dataquest, ICI, Synopsys Estimates
2015/10/3
Dragon Star Shot Course
33
Key Trends
By 2005

Cost: $2-5k/pin ( high performance)

Pins / package: 1900

Performance: up to 2 GHZ
Tester timing accuracy growing at 12% per
year
ASIC speeds growing at 30% per year
IDDQ becoming less meaningful


For every 80mV of VT decrease Ioff increases 10x!!
Higher leakage currents make IDDQ values increase
dramatically as transistor density increases
More mixed-signal
testing
Dragon Star Shot Course
2015/10/3
34
Agenda
Dealing with technology



Masks
Front-end manufacturing
Back-end manufacturing
Application requirements
Putting it all together
2015/10/3
Dragon Star Shot Course
35
Application Requirements
Systems
$1050B
• Computers
• Communications
• Consumer
• Industrial, Military…
EDA
Design
$3.6B
EDA
$2.7B
Comp
Platforms
Masks
Front-End Manufacturing $24B
Embedded SW
$0.8B
IP
$0.9B
Semiconductors $119B
• Micros, DSP
• Memory
• ASIC, ASSP
• Analog, Discrete
Mask Data
Masks
$2.8B
• Manufacturing $2.3B
• Tools
$0.5B
$45B
$25B
$25B
$25B
Wafer
$4B
• Process Auto
• Lithography
• Etch/Doping
• Diffusion
• Deposition
• Other (CMP, Ion,
Photoresist, etc.)
$1B
$6B
$6B
$1B
$5B
$5B
Back-End Manufacturing $6B
Chips
• Bonding
• Packaging
• Test equipment
$1B
$2B
$3B
Market size for 2001 Sources: Thomas Weisel Dataquest, ICI, Synopsys Estimates
2015/10/3
Dragon Star Shot Course
36
Heterogeneity - SoC
Digital




Control
µP
DSP
Interfaces
Memory



2015/10/3
Dragon Star Shot Course
Analog
RF
Power
MEMs
IP
SRAM
DRAM
FLASH
37
What EDA Must Provide…
2015/10/3
System level design
Soc design&test,
verification methodology
Need hierarchy in the
design flow
Analog, digital, RF,
MEMs
IP for soc construction /
verification: processors,
memory, peripherals, etc.
Soc design for debug
(debug busses and 38
Dragon Star Shot Course
ASIC, ASSP, ASIP, GA, FPGA
ASIC & ASSP differ only by how they are sold and used,
not by how they are designed
Early market characteristics  ASICs
Late market characteristics  ASSPs
Trend toward application-specific instruction processors

Many processors on a chip
Metal Programmability (GA) gaining attention again
SW Programmable (FPGA), reconfigurable parts gaining
importance
Embedded FPGA / GA
2015/10/3
Dragon Star Shot Course
39
Power
1400
Dynamic
power
density
1200
mW/mm2
1000
800
600
Leakage
power
density
400
200
0
0.18 µm
2015/10/3
0.13 µm
Dragon Star Shot Course
0.10 µm
0.05 µm
40
Solutions for Low Power Design
Power modeling and analysis
Clock gating and clock tree optimization
Variable Vdd



Power gating
Multi - Vdd
Dynamic voltage scaling
Leakage optimization using multi-Vt
Modelling process variation
Support Asynchronous design
2015/10/3
Dragon Star Shot Course
41
180nm
Low Vt
High Vt
Dual Vt
Leakage Power
Vdd (V) Delay (ps) Min (nW) Aver (nW) Max(nW)
1.8
28
0.011
0.263
0.955
1.8
36
0.007
0.068
0.280
Big/Small
1.286
1.571
3.868
3.411
Low Vt
High Vt
Cell number [0-467]
2015/10/3
Dragon Star Shot Course
130nm
Leakage Power
Vdd (V) Delay (ps) Min (nW) Aver (nW) Max (nW)
1.2
10
1.135 30.779 233.395
1.2
16
0.002
0.043
0.580
Big/Small
1.600 567.500 715.791 402.405
Cell number [0-519]
42
From Ali Dasdan
Speed
Determined by interconnect
The primary physical effect of concern
is cross-coupled capacitance plus the
Miller effect. This may cause:

functional errors in analog
circuitry or dynamic logic
V
dd
R
DV = IR
V -DV
dd
I
R

timing errors in static digital
circuitry
V
ss
IR Drop (static leakage and dynamic
IR drop) handled in power
Other important effects & features are
Inductance, CD variation, EM
2015/10/3
Dragon Star Shot Course
43
Agenda
Dealing with technology



Masks
Front-end manufacturing
Back-end manufacturing
Application requirements
Putting it all together
2015/10/3
Dragon Star Shot Course
44
Putting it All Together: EDA
Systems
$1050B
• Computers
• Communications
• Consumer
• Industrial, Military…
EDA
Design
$3.6B
EDA
$2.7B
Comp
Platforms
Masks
Front-End Manufacturing $24B
Embedded SW
$0.8B
IP
$0.9B
Semiconductors $119B
• Micros, DSP
• Memory
• ASIC, ASSP
• Analog, Discrete
Mask Data
Masks
$2.8B
• Manufacturing $2.3B
• Tools
$0.5B
$45B
$25B
$25B
$25B
Wafer
$4B
• Process Auto
• Lithography
• Etch/Doping
• Diffusion
• Deposition
• Other (CMP, Ion,
Photoresist, etc.)
$1B
$6B
$6B
$1B
$5B
$5B
Back-End Manufacturing $6B
Chips
• Bonding
• Packaging
• Test equipment
$1B
$2B
$3B
Market size for 2001 Sources: Thomas Weisel Dataquest, ICI, Synopsys Estimates
2015/10/3
Dragon Star Shot Course
45
SoC Design
Power
Smart Verification
Extraction
Physical Verification
Languages
Assertions and Testbenches
Physical Implementation
Verification IP
Design Planning
Architecture Design
Design Database
Test
Synthesis
IP
Physical
Timing and Signal Integrity
Design Services
Mixed Signal / Analog
Mask Synthesis / OPC
2015/10/3
Dragon Star Shot Course
46
Implementation Nodes
180nm
130nm
90nm
65nm
Computing Parallelism
64 Bits
IP
IP
30%
50%
70%
90%
Flow
Hierarchy
Large designs
Database
Partial
Partial
Integrated
Integrated
API
Proprietary
Open
Open
Open
S, P&R
S, P&R
S&P - R
S&P - R
Integrated
Integrated
Handoff
Placed Gates Placed Gates
Layout
Layout
Timing
TC
SI
L for Busses
1.5GHz
1.5GHz
1.5GHz
Clocking
Cycles across Chip
1
Few
Few
Many
Clocking
Sync
Sync
Sync/Async Sync/Async
IR drop
Power
Power
Power
Power&Signal
2015/10/3
Dragon Star Shot Course
47
Implementation Nodes
Power
Test
RET
DFM
Analog
Package
2015/10/3
Clock Gating
Multi Vdd
Multi Vth (leakage)
Scan
Mem Bist
Logic Bist
Design for Debug
OPC
PSM
DR for RET
Statistical Timing
PD for DFM
P&R
Synthesis
Spice Chip/Pack.
P&R Chip/Pack.
180nm
130nm
90nm
65nm
Manual
Manual
Semi-Auto
Manual
Semi-Auto
Semi-Auto
Semi-Auto
Semi-Auto
Dragon Star Shot Course
48
Verification IP
Architecture
Design
Smart
Verification
Mixed Signal /
Analog
2015/10/3
Languages
Assertions and Testbenches
Functional Verification
Driven by complexity
Verification models (IP)
Avenues of development




Higher levels
Performance
Integration
New (formal) technologies
Emulation competes with


Prototyping (enabled by multi-million
gate FPGAs)
Compute farms (Linux)
Dragon Star Shot Course
49
Verification IP
Architecture
Design
Smart
Verification
Mixed Signal /
Analog
Languages
Assertions and Testbenches
Functional Verification 2003
Standard based IP, Star IP on AMBA
(System) Verilog for HW
SystemC for system level design (SW)
Languages for testbenches, assertions
being standardized
Integrated simulation


Testbenches



Language
Assertions (monitor)
Constraint solver
Formal verification


2015/10/3
(System)Verilog/VHDL
Fast Spice/Spice
Equivalence checking
Semi-Formal property checking
Dragon Star Shot Course
50
Summary
Dealing with technology

Masks
RET, OPC, PSM

Front-end manufacturing
Interconnect, CD variation, dishing, DFM

Back-end manufacturing
Packaging, test
Application requirements

Heterogeneity, cost, power, speed
Putting it all together

2015/10/3
Implementation flow, verification flow
Dragon Star Shot Course
51
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