‫מבנה מחשבים‬
Lecture 1
Course Introduction
Eytan Ruppin and Alon Schclar
Slides from
Randy H. Katz, John Wawrzynek and Dan Garcia
Berkeley
‫מבנה מחשבים‬
1 ‫הרצאה‬
‫‪Lecture Overview‬‬
‫‪ Introduction : Computer Architecture‬‬
‫‪ Administrative Matters‬‬
‫‪ Engineering:‬‬
‫ממוליכים וחשמל ועד פעולות בינריות בסיסיות במחשב ‪‬‬
‫מתח חשמלי •‬
‫מוליכים •‬
‫סיליקון‪ :‬מוליך למחצה •‬
‫טרנזיסטור •‬
‫פעולות בינריות ברכיבים אלקטרוניים •‬
‫הרצאה ‪ 1‬שקף ‪2‬‬
What is “Computer Architecture”?
Computer Architecture =
 Instruction Set Architecture +
 Machine Organization + …
 = ‫ ארכיטקטורה‬+ ‫הנדסה‬
3 ‫ שקף‬1 ‫הרצאה‬
The Instruction Set: a Critical Interface
software
instruction set
hardware
4 ‫ שקף‬1 ‫הרצאה‬
What are “Machine Structures”?
Application (ex: browser)
Software
Hardware
Operating
Compiler
System
Assembler (Linux, Win, ..)
Processor Memory I/O system
‫מבנה מחשבים‬
Instruction Set
Architecture
Datapath & Control
Digital Design
Circuit Design
transistors
* Coordination of many
levels (layers) of abstraction
5 ‫ שקף‬1 ‫הרצאה‬
Levels of Representation
temp = v[k];
High Level Language
Program
v[k] = v[k+1];
v[k+1] = temp;
Compiler
lw $15,
lw $16,
sw
sw
Assembly Language
Program
Assembler
Machine Language
Program
0000
1010
1100
0101
1001
1111
0110
1000
1100
0101
1010
0000
0($2)
4($2)
$16, 0($2)
$15, 4($2)
0110
1000
1111
1001
1010
0000
0101
1100
1111
1001
1000
0110
0101
1100
0000
1010
1000
0110
1001
1111
Machine Interpretation
Control Signal
Specification
°
°
ALUOP[0:3] <= InstReg[9:11] & MASK
6 ‫ שקף‬1 ‫הרצאה‬
MIPS R3000 Instruction Set Architecture
(Summary)
 Instruction Categories
Registers
• Load/Store
R0 - R31
• Computational
• Jump and Branch
• Floating Point
-
PC
HI
coprocessor
• Memory Management
LO
• Special
3 Instruction Formats: all 32 bits wide
OP
rs
rt
OP
rs
rt
OP
rd
sa
funct
immediate
jump target
Q: How many already familiar with MIPS ISA?
8 ‫ שקף‬1 ‫הרצאה‬
Execution Cycle
Instruction
Fetch
Obtain instruction from program storage
Instruction
Decode
Determine required actions and instruction size
Operand
Fetch
Locate and obtain operand data
Execute
Compute result value or status
Result
Store
Next
Instruction
Deposit results in storage for later use
Determine successor instruction
9 ‫ שקף‬1 ‫הרצאה‬
What is “Computer Architecture”?
Application
Operating
System
Compiler
Firmware
Instr. Set Proc. I/O system
Instruction Set
Architecture
Datapath & Control
Digital Design
Circuit Design
Layout
 Coordination of many levels of abstraction
 Under a rapidly changing set of forces
 Design, Measurement, and Evaluation
10 ‫ שקף‬1 ‫הרצאה‬
Anatomy: 5 components of any Computer
Personal Computer
Computer
Processor
Control
(“brain”)
Datapath
(“brawn”)
Memory
(where
programs,
data
live when
running)
Devices
Input
Output
Keyboard,
Mouse
Disk
(where
programs,
data
live when
not running)
Display,
Printer
11 ‫ שקף‬1 ‫הרצאה‬
SO
 All computers consist of five components
• Processor: (1) datapath and (2) control
• (3) Memory
• (4) Input devices and (5) Output devices
 Not all “memory” are created equally
• Cache: fast (expensive) memory are placed closer to the
processor
• Main memory: less expensive memory--we can have more
 Interfaces are where the problems are - between
functional units and between the computer and the
outside world
 Need to design against constraints of performance,
power, area and cost
12 ‫ שקף‬1 ‫הרצאה‬
Organization
 Capabilities & performance characteristics
of principal functional units
• (e.g., Registers, ALU, Shifters,
Logic Units, ...)
 Ways in which these components are
interconnected
Logic Designer's View
ISA Level
FUs & Interconnect
 Information flows between components
 Logic and means by which such
information flow is controlled
 Choreography of FUs to realize the ISA
 Register Transfer Level (RTL) Description
13 ‫ שקף‬1 ‫הרצאה‬
Forces on Computer Architecture
Technology
Programming
Languages
Applications
Computer
Architecture
Operating
Systems
Cleverness
History
14 ‫ שקף‬1 ‫הרצאה‬
Computer Architecture’s Changing Definition
 1950s to 1960s Computer Architecture Course
• Computer Arithmetic
 1970s to mid 1980s Computer Architecture Course
• Instruction Set Design, especially ISA appropriate for
compilers
 1990s Computer Architecture Course
• Design of CPU, memory system, I/O system, Multiprocessors, Networks
 2000s Computer Architecture Course:
• Special purpose architectures, Functionally reconfigurable,
Special considerations for low power/mobile processing
15 ‫ שקף‬1 ‫הרצאה‬
Technology Trends: Memory Capacity
(Single-Chip DRAM)
siz e
1000000000
100000000
B its
10000000
1000000
100000
10000
1000
1970
1975
1980
1985
1990
1995
Year
• Now 1.4X/yr, or 2X every 2 years.
• 8000X since 1980!
2000
year
1980
1983
1986
1989
1992
1996
1998
2000
2002
size (Mbit)
0.0625
0.25
1
4
16
64
128
256
512
16 ‫ שקף‬1 ‫הרצאה‬
Technology Trends: Microprocessor Complexity
100000000
Itanium 2: 410 Million
Athlon (K7): 22 Million
Alpha 21264: 15 million
Pentium Pro: 5.5 million
PowerPC 620: 6.9 million
Alpha 21164: 9.3 million
Sparc Ultra: 5.2 million
10000000
Moore’s Law
Pentium
i80486
T ran si sto rs
1000000
i80386
i80286
100000
2X transistors/Chip
Every 1.5 years
i8086
10000
i8080
i4004
1000
1970
1975
1980
1985
Year
1990
1995
2000
Called
“Moore’s Law”
17 ‫ שקף‬1 ‫הרצאה‬
Technology Trends Imply Dramatic Change
 Processor
• Logic capacity:
about 30% per year
• Clock rate:
about 20% per year
 Memory
• DRAM capacity: about 60% per year (4x every 3 years)
• Memory speed:
about 10% per year
• Cost per bit:
improves about 25% per year
 Disk
• Capacity:
about 60% per year
• Total data use:
100% per 9 months!
 Network Bandwidth
• Bandwidth increasing more than 100% per year!
18 ‫ שקף‬1 ‫הרצאה‬
Log of Performance
Performance Trends
Supercomputers
Mainframes
Minicomputers
Microprocessors
Year
1970
1975
1980
1985
1990
1995
19 ‫ שקף‬1 ‫הרצאה‬
Course Administration

Instructors:
Eytan Ruppin ([email protected])

TAs:
Alon Schcalar ([email protected])

Materials: http://www.cs.tau.ac.il/~ruppin

Books:
1.
V. C. Hamacher, Z. G. Vranesic, S. G. Zaky Computer Organization.
McGraw-Hill, 1982
2.
H. Taub Digital Circuits and Microporcessors. McGraw-Hill 1982
3. Hennessy and Patterson, Computer Organization Design, the
hardware/software interface, Morgan Kaufman 1998
20 ‫ שקף‬1 ‫הרצאה‬
Course Content
Computer Architecture and Engineering
Instruction Set Design
Computer Organization
Interfaces
Hardware Components
Compiler/System View
Logic Designer’s View
“Building Architect”
“Construction Engineer”
21 ‫ שקף‬1 ‫הרצאה‬
‫‪Grading‬‬
‫ציון‪:‬‬
‫‪ ‬מבחן סופי‬
‫‪80%‬‬
‫‪ ‬תרגילים‬
‫‪20%‬‬
‫‪ 8‬תרגילים‬
‫הרצאה ‪ 1‬שקף ‪22‬‬
Where are We Going??
Input
Multiplier
Input
Multiplicand
32
Multiplicand
Register
LoadMp
32=>34
signEx
<<1
32
34
34
32=>34
signEx
1
Arithmetic
Multi x2/x1
34
34
Sub/Add
34-bit ALU
Control
Logic
32
32
2
ShiftAll
LO register
(16x2 bits)
Prev
2
Booth
Encoder
HI register
(16x2 bits)
LO[1]
2
"LO
[0]"
34
Extra
2 bits
ENC[2]
ENC[1]
ENC[0]
LoadLO
LoadHI
2
ClearHI
Single/multicycle
Datapaths
0
34x2 MUX
32
Result[HI]
LO[1:0]
32
Result[LO]
1000
CPU
IFetchDcd
WB
Exec Mem
WB
Performance
Processor-Memory
Performance Gap:
(grows 50% / year)
10
DRAM
9%/yr.
DRAM (2X/10 yrs)
1
198
2
3
198
498
1
5
198
6
198
7
198
8
198
9
199
0
199
199
2
199
399
1
4
199
5
199
699
1
7
199
8
199
9
200
0
Exec Mem
100
198
098
1
1
198
IFetchDcd
‫מבנה‬
‫מחשבים‬
“Moore’s Law”
µProc
60%/yr.
(2X/1.5yr)
Time
IFetchDcd
Exec Mem
IFetchDcd
WB
Exec Mem
WB
Pipelining
I/O

23 ‫ שקף‬1 ‫הרצאה‬
Memory Systems
Descargar

CS151: Introduction and Five Components of a Computer