Instruction Sets
• Be able to explain the organization of the classical von Neumann machine and its
major functional components.
• Be able to demonstrate understanding of instruction set content including types
of instructions, addressing modes, and instruction formats.
• Master instruction execution.
Chapter 2
1
Instruction Set
• The repertoire of instructions of a computer
• Different computers have different instruction sets
– But with many aspects in common
• Early computers had very simple instruction sets
– Simplified implementation
• Many modern computers also have simple instruction sets
2
Stored Program Concept
• Instructions are bits
• Programs are stored in memory
— to be read or written just like data
• 4D2A 56B0 is stored at a location – how does one interpret this?
Processor
Memory
memory for data, instructions,
addresses, programs,
compilers, editors, etc.
• Fetch & Execute Cycle
–
–
–
–
–
Instructions are fetched and put into a special register
Bits in the register "control" the subsequent actions
Operand fetch
Execute
Fetch the “next” instruction and continue
3
Registers vs. Memory
• Arithmetic instructions operands must be registers,
— only 32 registers provided
• Register size – bigger the better?
• Number of registers – more the better?
• Compiler associates variables with registers
Control
Datapath
Registers
Functional
units
Input
Memory
Output
I/O
Processor
4
Compilation to execution - review
•
•
Higher Level Language
MIPS Assembly Language
– Symbolic
– More primitive than higher level languages
e.g., no sophisticated control flow
•
Assembly can provide 'pseudoinstructions'
– e.g., “move $t0, $t1” exists only in Assembly
– would be implemented using “add $t0,$t1,$zero”
•
MIPS instructions
– Very restrictive e.g., MIPS Arithmetic Instructions
– Defined registers
•
Machine Language
•
When considering performance you should count real instructions
Design goals: maximize performance and minimize cost, reduce design time
5
MIPS arithmetic
• All instructions have 3 operands
– Two inputs
– One result
– Operand order is fixed (destination first)
Example:
A = B + C
If B is in $s1 and C is in $s2 then
MIPS code:
add $s0, $s1, $s2
Result (A) is in $s0
• If B and C are in main memory, then first load the memory contents to
respective registers.
• Compilers map variables to registers.
6
Arithmetic Example
• C code:
f = (g + h) - (i + j);
• Compiled MIPS code:
add t0, g, h
add t1, i, j
sub f, t0, t1
# temp t0 = g + h
# temp t1 = i + j
# f = t0 - t1
7
Memory Operand Example 1
• C code:
g = h + A[8];
– g in $s1, h in $s2, base address of A in $s3
• Compiled MIPS code:
– Index 8 requires offset of 32
• 4 bytes per word
lw $t0, 32($s3)
# load word
add $s1, $s2, $t0
offset
base register
8
Memory Operand Example 2
• C code:
A[12] = h + A[8];
– h in $s2, base address of A in $s3
• Compiled MIPS code:
– Index 8 requires offset of 32
lw $t0, 32($s3)
# load word
add $t0, $s2, $t0
sw $t0, 48($s3)
# store word
9
§2.6 Logical Operations
Logical Operations
• Instructions for bitwise manipulation
Operation
C
Java
MIPS
Shift left
<<
<<
sll
Shift right
>>
>>>
srl
Bitwise AND
&
&
and, andi
Bitwise OR
|
|
or, ori
Bitwise NOT
~
~
nor
• Useful for extracting and inserting groups of bits in a word
10
Shift Operations
op
rs
rt
rd
shamt
funct
6 bits
5 bits
5 bits
5 bits
5 bits
6 bits
• shamt: how many positions to shift
• Shift left logical
– Shift left and fill with 0 bits
– sll by i bits multiplies by 2i
• Shift right logical
– Shift right and fill with 0 bits
– srl by i bits divides by 2i (unsigned only)
11
§2.7 Instructions for Making Decisions
Conditional Operations
• Branch to a labeled instruction if a condition is true
– Otherwise, continue sequentially
• beq rs, rt, L1
– if (rs == rt) branch to instruction labeled L1;
• bne rs, rt, L1
– if (rs != rt) branch to instruction labeled L1;
• j L1
– unconditional jump to instruction labeled L1
12
Compiling If Statements
• C code:
if (i==j) f = g+h;
else f = g-h;
– f, g, … in $s0, $s1, …
• Compiled MIPS code:
bne
add
j
Else: sub
Exit: …
$s3, $s4, Else
$s0, $s1, $s2
Exit
$s0, $s1, $s2
Assembler calculates addresses
13
MIPS Registers – Names and Functions
Name
$zero
$at
$v0
$v1
$a0-$a4
$t0-$t7
$s0-$s7
Reg
Num
0 0
0 1
02
3
4
08 to 15
Function
constant 0
reserved for assembler
expression evaluation and results of a function
expression evaluation and results of a function
procedure arguments
temporary (not preserved across call – can be overwritten by callee)
16 to 23 saved temporary (preserved across call – saved/restored by callee)
$t8-$t9
24-25
temporary (not preserved across call)
$k0
$k1
$gp
$sp
$fp
$ra
26
27
28
29
30
31
reserved for OS kernel
reserved for OS kernel
pointer to global area
stack pointer
frame pointer
return address (used by function call)
14
Memory Organization
•
•
•
Think of memory as a large, singledimensional array.
Memory address is like index of the array.
Memory reference is at the byte level.
– Retrieve a minimum of 1 byte from memory in
each access.
•
The instructions are 4 bytes long. Does this
require 4 accesses to memory?
0
8 bits of data
1
8 bits of data
2
8 bits of data
3
8 bits of data
4
8 bits of data
5
8 bits of data
6
8 bits of data
7
8 bits of data
8
8 bits of data
15
Memory Organization
•
•
Bytes are nice, but most data items use larger "words“. How many bits
in an instruction?
For MIPS, a word is 32 bits or 4 bytes.
•
•
•
0 32 bits of data
4 32 bits of data
Registers hold 32 bits of data
32
bits
of
data
8
12 32 bits of data
...
232 bytes with byte addresses from 0 to 232-1
230 words with byte addresses 0, 4, 8, ... 232-4
Words are aligned.
0
0
0
1
1
0
1
1
What are the 2 LSBs (least significant
bits) of a word address?
0
x
4
8
12
x
x
x
16
Categories of Instructions
• Data manipulation
–
–
–
–
–
Arithmetic
Logical
Shift
Comparison
add, sub, addi
• Program Manipulation
– Unconditional and conditional
branch
– Subroutine / procedure calls
– beq, bne, j, jal
• Status Management
• Data transfer
–
–
–
–
–
– Exceptions
– Interrupts
• Software / Hardware
• Interrupt processing vs
procedure call
Memory transfer
Intra CPU
I/O
Stack
lw, sw
Instruction size
• Variable
• Fixed (MIPS)
17
Typical Instructions
•
•
•
•
•
Instruction
Meaning
Data Manipulation
add $s1,$s2,$s3
sub $s1,$s2,$s3
Data Transfer
lw $s1,100($s2)
sw $s1,100($s2)
Program Manipulation
bne $s4,$s5,L
beq $s4,$s5,L
$s1 = $s2 + $s3
$s1 = $s2 – $s3
$s1 = Memory[$s2+100]
Memory[$s2+100] = $s1
Next instr. is at Label if $s4 =/ $s5
Next instr. is at Label if $s4 = $s5
Formats:
R
op
rs
rt
rd
shamt
funct
I
op
rs
rt
16 bit address
J
op
26 bit address
18
To summarize:
M IP S o p e ra n d s
Nam e
3 2 re g is te rs
2
30
E x a m p le
$s0-$s7, $t0-$t9, $zero,
F a s t lo c a tio n s fo r d a ta . In M IP S , d a ta m u s t b e in re g is te rs to p e rfo rm
$a0-$a3, $v0-$v1, $gp,
a rith m e tic . M IP S re g is te r $ z e ro a lw a y s e q u a ls 0 . R e g is te r $ a t is
$fp, $sp, $ra, $at
re s e rv e d fo r th e a s s e m b le r to h a n d le la rg e c o n s ta n ts .
M e m o ry [0 ],
A c c e s s e d o n ly b y d a ta tra n s fe r in s tru c tio n s . M IP S u s e s b y te a d d re s s e s , s o
m e m o ry M e m o ry [4 ], ...,
w o rd s
C o m m e n ts
s e q u e n tia l w o rd s d iffe r b y 4 . M e m o ry h o ld s d a ta s tru c tu re s , s u c h a s a rra y s ,
M e m o ry [4 2 9 4 9 6 7 2 9 2 ]
a n d s p ille d re g is te rs , s u c h a s th o s e s a v e d o n p ro c e d u re c a lls .
M IP S a s s e m b ly la n g u a g e
C a te g o ry
A rith m e tic
D a ta tra n s fe r
In s tru c tio n
add
E x a m p le
add $s1, $s2, $s3
M e a n in g
$s1 = $s2 + $s3
T h re e o p e ra n d s ; d a ta in re g is te rs
s u b tra c t
sub $s1, $s2, $s3
$s1 = $s2 - $s3
T h re e o p e ra n d s ; d a ta in re g is te rs
a d d im m e d ia te
addi $s1, $s2, 100
$s1 = $s2 + 100
U s e d to a d d c o n s ta n ts
lo a d w o rd
lw
$s1, 100($s2)
s to re w o rd
sw
$s1, 100($s2)
lo a d b y te
lb
$s1, 100($s2)
$ s 1 = M e m o ry [ $ s 2 + 1 0 0 ] W o rd fro m m e m o ry to re g is te r
W o rd fro m re g is te r to m e m o ry
M e m o ry [ $ s 2 + 1 0 0 ] = $ s 1
$ s 1 = M e m o ry [ $ s 2 + 1 0 0 ] B y te fro m m e m o ry to re g is te r
sb
$s1, 100($s2)
lo a d u p p e r im m e d ia te l u i $ s 1 , 1 0 0
s to re b y te
b ra n c h o n e q u a l
beq
$s1, $s2, 25
M e m o ry [ $ s 2 + 1 0 0 ] = $ s 1
$s1 = 100 * 2
16
if ( $ s 1 = = $ s 2 ) g o to
C o m m e n ts
B y te fro m re g is te r to m e m o ry
L o a d s c o n s ta n t in u p p e r 1 6 b its
E q u a l te s t; P C -re la tiv e b ra n c h
P C + 4 + 100
b ra n c h o n n o t e q u a l
bne
$s1, $s2, 25
N o t e q u a l te s t; P C -re la tiv e
P C + 4 + 100
C o n d itio n a l
b ra n c h
if ( $ s 1 ! = $ s 2 ) g o to
s e t o n le s s th a n
slt
s e t le s s th a n
slti
$s1, $s2, $s3
$s1, $s2, 100
im m e d ia te
if ( $ s 2 < $ s 3 ) $ s 1 = 1 ;
e ls e $ s 1 = 0
C o m p a re le s s th a n ; fo r b e q , b n e
if ( $ s 2 < 1 0 0 ) $ s 1 = 1 ;
e ls e $ s 1 = 0
C o m p a re le s s th a n c o n s ta n t
ju m p
j
2500
ju m p re g is te r
$ra
g o to 1 0 0 0 0
g o to $ r a
J u m p to ta rg e t a d d re s s
U n c o n d i-
jr
tio n a l ju m p
ju m p a n d lin k
jal
2500
$ r a = P C + 4 ; g o to 1 0 0 0 0
F o r p ro c e d u re c a ll
F o r s w itc h , p ro c e d u re re tu rn
2005 Morgan Kaufmann Publishers
19
MIPS Addressing Modes
1. Im m e diate a dd re s sing
op
rs
rt
Im m ed ia te
2. R eg is ter ad dr e ss in g
op
rs
rt
rd
. ..
fu nc t
R eg is te rs
R eg is ter
3. B as e ad dr es s in g
op
rs
rt
M emory
A d dr es s
+
R e gister
B y te
H a lfw or d
W o rd
4. P C -re la tive a dd re ss in g
op
rs
rt
M emory
A d dr es s
PC
+
W o rd
5. P se ud o dir e ct ad dr es s in g
op
A d d re ss
PC
M emory
W o rd
2005 Morgan Kaufmann Publishers
20
MIPS Addressing Modes
1. Im m e diate a dd re s sing
op
rs
rt
Im m ed ia te
2. R eg is ter ad dr e ss in g
op
rs
rt
rd
. ..
fu nc t
R eg is te rs
R eg is ter
3. B as e ad dr es s in g
op
rs
rt
M emory
A d dr es s
+
R e gister
B y te
H a lfw or d
W o rd
4. P C -re la tive a dd re ss in g
op
EA=PC+
(Address X 4)
rs
rt
M emory
A d dr es s
PC
+
W o rd
5. P se ud o dir e ct ad dr es s in g
op
EA=PC(31:28)||
(Address X 4)
A d d re ss
PC
M emory
W o rd
EA = Effective Address
2005 Morgan Kaufmann Publishers
21
Von Neumman Architecture
Fetch
Execute
Decode
From Wikipedia
22
What are essential ingredients of an instruction?
• Take as an example a very simple arithmetic computation
– A=B+C
• Definition of operation – op code
• Address of A
– Address of Result
• Address of B
– Address of Data Source
• Address of C
– Address of Data Source
• Address of Next Instruction
• Consider a very simple processor like 8080
– 8 bit word and 16 bit address
• Size of the instruction?
23
MIPS Instruction Execution Cycle
Instruction
Fetch
Obtain instruction from program storage
Instruction
Decode
Operand
Fetch
Execute
Result
Determine required actions and instruction size
Locate and obtain operand data
Compute result value or status
Deposit results in storage for later use
Store
Next
Instruction
Determine successor instruction
Copyright 1997 UCB
24
Reducing Instruction Length – a few approaches
•
•
•
•
•
•
Program Counter contains address of next instruction
Make destination address implicit
Make source address implicit
Make source and destination address the same
Use register addressing rather than memory addressing
Use addressing modes
– Short address in instruction
– Access to large memory space
– Step through array
25
Addressing Mode Examples
MIPS
Other Computers
•
•
•
•
•
•
•
•
•
•
•
•
Register Addressing
Base or displacement
– Effective Address =
($n) + value in instruction
•
Immediate addressing
– Operand in instruction
•
PC – relative
– Effective Address =
(PC) + value in instruction
Direct
Indirect
Immediate
Indexed
Relative
Register direct
Register indirect
Stack
Auto increment
Auto decrement
26
Guiding principles in instruction set selection
•
•
•
•
Make Common Case Fast
Smaller is faster
Simplicity favors regularity
Good design demands compromise
27
Procedure Calls
• Modern software design leads to many procedures
• Procedures help in abstraction – detail hiding
• Process
– Procedure call
– Put parameters in locations (maybe registers) accessible to the procedure
{Save registers that may change!!}
– Transfer control
– Perform the required task
– Place parameters in place accessible to the main program
– Return to the calling procedure
• Nested procedures
• How does this work
– Need to transfer to new address
– Save the “return” address
– After procedure execution return to the old “return” address
28
Example
161
jal Proc_Addr
Increment PC to point to next instruction
Save new PC in $ra (register 31)
Branch to Proc_Addr
Return achieved by
jr $31
29
Review
• Instruction set architecture
– Abstract interface between lowest level software and the hardware.
– Lets programmers think in terms of functions rather than implementation.
• Instruction set
–
–
–
–
Types of instructions.
Instruction formats.
Addressing modes.
Content analysis of instructions.
• Instructions will be too long.
• Reduce the size of the instruction.
• An approach to motivate addressing modes and some hardware components.
• Steps in executing an instruction
– Execution of individual instructions.
30
Many compilers produce
object modules directly
Static linking
31
§2.12 Translating and Starting a Program
Translation and Startup
Assembler Pseudoinstructions
• Most assembler instructions represent machine instructions one-to-one
• Pseudoinstructions: figments of the assembler’s imagination
move $t0, $t1
blt $t0, $t1, L
→
→
add $t0, $zero, $t1
slt $at, $t0, $t1
bne $at, $zero, L
– $at (register 1): assembler temporary
32
Producing an Object Module
•
•
Assembler (or compiler) translates program into machine instructions
Provides information for building a complete program from the pieces
–
–
–
–
–
–
Header: described contents of object module
Text segment: translated instructions
Static data segment: data allocated for the life of the program
Relocation info: for contents that depend on absolute location of loaded program
Symbol table: global definitions and external refs
Debug info: for associating with source code
33
Linking Object Modules
• Produces an executable image
1. Merges segments
2. Resolve labels (determine their addresses)
3. Patch location-dependent and external refs
• Could leave location dependencies for fixing by a relocating loader
– But with virtual memory, no need to do this
– Program can be loaded into absolute location in virtual memory space
34
Loading a Program
• Load from image file on disk into memory
1. Read header to determine segment sizes
2. Create virtual address space
3. Copy text and initialized data into memory
• Or set page table entries so they can be faulted in
4. Set up arguments on stack
5. Initialize registers (including $sp, $fp, $gp)
6. Jump to startup routine
• Copies arguments to $a0, … and calls main
• When main returns, do exit syscall
35
Dynamic Linking
• Only link/load library procedure when it is called
– Requires procedure code to be relocatable
– Avoids image bloat caused by static linking of all (transitively) referenced
libraries
– Automatically picks up new library versions
36
Lazy Linkage
Indirection table
Stub: Loads routine ID,
Jump to linker/loader
Linker/loader code
Dynamically
mapped code
37
§2.18 Fallacies and Pitfalls
Fallacies
•
Powerful instruction  higher performance
– Fewer instructions required
– But complex instructions are hard to implement
• May slow down all instructions, including simple ones
– Compilers are good at making fast code from simple instructions
•
Use assembly code for high performance
– But modern compilers are better at dealing with modern processors
– More lines of code  more errors and less productivity
38
Fallacies
• Backward compatibility  instruction set doesn’t change
– But they do accrete more instructions
x86 instruction set
39
Pitfalls
• Sequential words are not at sequential addresses
– Increment by 4, not by 1!
40
§2.19 Concluding Remarks
Concluding Remarks
• Design principles
1.
2.
3.
4.
Simplicity favors regularity
Smaller is faster
Make the common case fast
Good design demands good compromises
• Layers of software/hardware
– Compiler, assembler, hardware
• MIPS: typical of RISC ISAs
– c.f. x86
41
Concluding Remarks
• Measure MIPS instruction executions in benchmark programs
– Consider making the common case fast
– Consider compromises
Instruction class
MIPS examples
SPEC2006 Int
SPEC2006 FP
Arithmetic
add, sub, addi
16%
48%
Data transfer
lw, sw, lb, lbu, lh, lhu, sb,
lui
35%
36%
Logical
and, or, nor, andi, ori, sll,
srl
12%
4%
Cond. Branch
beq, bne, slt, slti, sltiu
34%
8%
Jump
j, jr, jal
2%
0%
42
Chapter 2 assignments
2.2.1, 2.3.1, 2.4.1, 2.4.4, 2.7.1, 2.7.2, 2.10.1,
2.10.2, 2.10.3, 2.11.3, 2.13.1, 2.13.2, 2.13.3,
2.15.1, 2.30.1
43
Decoding Machine Language
Decode: 00AF8020hex
0000 0000 1010 1111 1000 0000 0010 0000
opcode: 0000 00 funct: 1000 00 shamt: 00000
rs: 00101 rt: 01111 rd: 10000
add $so, $a1, $t7
44
FIGURE 2.19 MIPS instruction encoding.
This notation gives the value of a field
by row and by column. For example,
the top portion of the figure shows
load word in row number 4 (100two
for bits 31−29 of the instruction) and
column number 3 (011two for bits
28−26 of the instruction), so the
corresponding value of the op field
(bits 31−26) is 100011two. Underscore
means the field is used elsewhere.
For example, R-format in row 0 and
column 0 (op = 000000two) is defined
in the bottom part of the figure.
Hence, subtract in row 4 and column
2 of the bottom section means that
the funct field (bits 5−0) of the
instruction is 100010two and the op
field (bits 31−26) is 000000two. The
floating point value in row 2, column 1
is defined in Figure 3.18 in Chapter 3.
Bltz/gez is the opcode for four
instructions found in Appendix B: bltz,
bgez, bltzal, and bgezal. This chapter
describes instructions given in full
name using color, while Chapter 3
describes instructions given in
mnemonics using color. Appendix B
covers all instructions. Copyright ©
2009 Elsevier, Inc. All rights reserved.
45
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Instruction Sets - George Mason University