Graduate Institute of Electronics Engineering, NTU
Digital IC Design Flow
Lecturer: Huai-Yi Hsu (許槐益)
Date: 2004.02.27
ACCESS IC LAB
Graduate Institute of Electronics Engineering, NTU
Outline
Introduction
IC Design Flow
Verilog History
HDL concept
Digital IC Design Flow 2004.02.27
Huai-Yi Hsu
pp. 2
Graduate Institute of Electronics Engineering, NTU
Moore’s Law: Driving Technology Advances
 Logic capacity doubles per IC at regular intervals (1965).
 Logic capacity doubles per IC every 18 months (1975).
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Graduate Institute of Electronics Engineering, NTU
Process Technology Evolution
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Graduate Institute of Electronics Engineering, NTU
Chips Sizes
Source: IBM and Dataquest
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Graduate Institute of Electronics Engineering, NTU
Shrinking Product Cycles
PCS: Personal Communication Services
 Shrinking product cycles
 Shrinking development turnaround times
 Need for productivity increase (remember the “design gap”)
Digital IC Design Flow 2004.02.27
Huai-Yi Hsu
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Graduate Institute of Electronics Engineering, NTU
Design Productivity Crisis
 Human factors may limit design more than technology.
 Keys to solve the productivity crisis:
 Design techniques: hierarchical design, SoC design (IP reuse,
platform-based design), etc.
 CAD: algorithms & methodology
Digital IC Design Flow 2004.02.27
Huai-Yi Hsu
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Graduate Institute of Electronics Engineering, NTU
Increasing Processing Power
 Very high performance circuits in today’s
technologies.
 Gate delays: ~27ps for a 2-input Nand in CU11
 Operating frequencies: up to 500MHz for SoC/Asic, over
1GHz for custom designs
 The increase in speed/performance of circuits
allowed blocks to be reused without having to be
redesigned and tuned for each application
 Enhanced Design Tools and Techniques
 Although not enough to close the “design gap”, tools are
essential for the design of today’s high-performance chips
Digital IC Design Flow 2004.02.27
Huai-Yi Hsu
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Graduate Institute of Electronics Engineering, NTU
IP-Based SoCs
 An Evolutionary Path
 Early days
 IP/Cores not really designed for reuse (no standard
deliverables)
 Multiple Interfaces, difficult to integrate
 IPs evolved: parameterization, deliverables, verification,
synthesizable
 On-Chip bus standards began to appear (e.g, IBM, ARM)
 Reusable IP + Common on-chip bus architectures
 1998: max number of cores > 30 cores
core content between 50% and 95%
Digital IC Design Flow 2004.02.27
Huai-Yi Hsu
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Graduate Institute of Electronics Engineering, NTU
IP / Cores
 Soft Core
 Delivered as RTL verilog or VHDL source code with
synthesis script (i.e: clock generation logic)
 Customers are responsible for synthesis, timing closure, and
all front-end processing
 Firm Core
 Delivered as a netlist to be included in customer’s netlist
(with don't touch attribute)
 Possibly with placement information
 Hard Core
 Due to their complexity, they are provided as a blackbox
(GL1/GDSII). Ex. Processors, analog cores, PLLs
 Usually very tight timing constraints. Internal views not be
alterable or visible to the customer
Digital IC Design Flow 2004.02.27
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Changes in the Nature of IC Design
(IEEE Spectrum Nov,1996)
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Graduate Institute of Electronics Engineering, NTU
Chasing the Design Gap
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Graduate Institute of Electronics Engineering, NTU
Evolution of Silicon Design
Source: “Surviving the SoC revolution – A Guide to Platform-based Design,”
Henry Chang et al, Kluwer Academic Publishers, 1999
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Graduate Institute of Electronics Engineering, NTU
Methodology – Analysis and Verification
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Graduate Institute of Electronics Engineering, NTU
IC Design and Implementation
Idea
Design
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Graduate Institute of Electronics Engineering, NTU
Design Flow
Back End
Design Specification
Pre-Synthesis
Sign-Off
Cell Placement, Scan
Chain & Clock Tree
Insertion, Cell Routing
Design Partition
Synthesize and Map
Gate-Level Netlist
Verify Physical &
Electrical Design Rules
Design Entry-Verilog
Behavioral Modeling
Post-Synthesis
Design Validation
Extract Parasitics
Simulation/Functional
Verification
Post-Synthesis
Timing Verification
Post-Layout
Timing Verification
Design Integration &
Verification
Test Generation &
Fault Simulation
Design Sign-Off
Production-Ready
Masks
Front End
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Graduate Institute of Electronics Engineering, NTU
System Specification
From CIC
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Algorithm Mapping
System Level
RTL Level
From CIC
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Graduate Institute of Electronics Engineering, NTU
Gate and Circuit Level Design
From CIC
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Physical Design
From CIC
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Graduate Institute of Electronics Engineering, NTU
Behavioral Model
System
concept
Algorithm
Increasing
behavioral
abstraction
Architecture
Increasing
detailed
realization &
complexity
Register Transfer Level
Gate Level
Transistor Level
Digital IC Design Flow 2004.02.27
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Graduate Institute of Electronics Engineering, NTU
Design Domain
Behavioral
level of
abstraction
System
Algorithm
RTL
Design Model Domain
Abstract
Structural
Physical
Architecture
Synthesis
Architecture
Design
RTL level
Synthesis
Structural
Design
Verification
Gate
Logic
Design
Verification
Switch
Digital IC Design Flow 2004.02.27
Logic level
Synthesis
Layout
Design
Verification
Huai-Yi Hsu
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Graduate Institute of Electronics Engineering, NTU
Introduction to HDL
HDL – Hardware Description Language
Why use an HDL ?
Hardware is becoming very difficult to design
directly
HDL is easier and cheaper to explore different
design options
Reduce time and cost
Digital IC Design Flow 2004.02.27
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Graduate Institute of Electronics Engineering, NTU
Verilog HDL
Brief history of Verilog HDL
1985: Verilog language and related simulator
Verilog-XL were developed by Gateway
Automation
1989: Cadence Design System purchased
Gateway Automation
1990: Cadence released Verilog HDL to public
domain
1990: Open Verilog International (OVI) formed
1995: IEEE standard 1364 adopted
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Graduate Institute of Electronics Engineering, NTU
Verilog HDL
Feature
HDL has high-level programming language
constructs and constructs to describe the
connectivity of your circuit.
Ability to mix different levels of abstraction freely
One language for all aspects of design, test, and
verification
Functionality as well as timing
Concurrency perform
Support timing simulation
Digital IC Design Flow 2004.02.27
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Graduate Institute of Electronics Engineering, NTU
Compared to VHDL
 Verilog and VHDL are comparable languages
 VHDL has a slightly wider scope
 System-level modeling
 Exposes even more discrete-event machinery
 VHDL is better-behaved
 Fewer sources of non-determinism
(e.g., no shared variables ???)
 VHDL is harder to simulate quickly
 VHDL has fewer built-in facilities for hardware
modeling
 VHDL is a much more verbose language
 Most examples don’t fit on slides
Digital IC Design Flow 2004.02.27
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Graduate Institute of Electronics Engineering, NTU
The Verilog Language
 Originally a modeling language
for a very efficient event-driven digital logic simulator
 Later pushed into use as a specification language
for logic synthesis
 Now, one of the two most commonly-used languages
in digital hardware design (VHDL is the other)
 Combines structural and behavioral modeling styles
Digital IC Design Flow 2004.02.27
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Graduate Institute of Electronics Engineering, NTU
Different Levels of Abstraction
 Architectural / Algorithmic
 A model that implements a design algorithm in high-level
language constructs
 Register Transfer Logic (RTL)
 A model that describes the flow of data between registers
and how a design process these data.
 Gate
 A model that describe the logic gates and the
interconnections between them.
 Switch
 A model that describes the transistors and the
interconnections between them.
Digital IC Design Flow 2004.02.27
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Graduate Institute of Electronics Engineering, NTU
Verilog HDL Behavior Language
 Structural and procedural like the C programming
language
 Used to describe algorithm level and RTL level
Verilog models
 Key features
 Procedural constructs for conditional, if-else, case, and
looping operations.
 Arithmetic, logical, bit-wise, and reduction operations for
expressions.
 Timing control.
Digital IC Design Flow 2004.02.27
Huai-Yi Hsu
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Graduate Institute of Electronics Engineering, NTU
Verilog HDL Structural Language
Used to describe gate-level and switch-level
circuits.
Key features
A complete set set of combinational primitives
Support primitive gate delay specification
Support primitive gate output strength
specification
Digital IC Design Flow 2004.02.27
Huai-Yi Hsu
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Graduate Institute of Electronics Engineering, NTU
Language Conventions
 Case-sensitivity
 Verilog is case-sensitive.
 Some simulators are case-insensitive
 Advice: - Don’t use case-sensitive feature!
 Keywords are lower case
 Different names must be used for different items
within the same scope
 Identifier alphabet:
 Upper and lower case alphabeticals: a~z A~Z
 Decimal digits: 0~9
 Underscore: _
Digital IC Design Flow 2004.02.27
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Graduate Institute of Electronics Engineering, NTU
Language Conventions (cont’d)
 Maximum of 1024 characters in identifier
 First character not a digit
 Statement terminated by ;
 Free format within statement except for within quotes
 Comments:
 All characters after // in a line are treated as a
comment
 Multi-line comments begin with /* and end with */
 Compiler directives begin with // synopsys XXX
 Built-in system tasks or functions begin with $
 Strings enclosed in double quotes and must be on a
single line “Strings”
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Graduate Institute of Electronics Engineering, NTU
Design Encapsulation
 Encapsulate structural and functional details in a module
module my_design (ports_list);
... // Declarations of ports go here
... // Structural and functional details go here
endmodule
 Encapsulation makes the model available for instantiation in
other modules
Digital IC Design Flow 2004.02.27
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Graduate Institute of Electronics Engineering, NTU
Port Declaration
Three port types
module
Input port
input
output
reg or net net
 input a;
reg or net
inout
Output port
net
net
 output b;
Bi-direction port
 inout c;
net
Port list
module full_add (S, CO, A, B, CI) ;
output S, CO ;
input A, B, CI ;
Port Declaration
--- function description --endmodule
Digital IC Design Flow 2004.02.27
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Graduate Institute of Electronics Engineering, NTU
Two Main Data Types
 Nets represent connections between things
 Do not hold their value
 Take their value from a driver such as a gate or
other module
 Cannot be assigned in an initial or always block
 Regs represent data storage
 Behave exactly like memory in a computer
 Hold their value until explicitly assigned
in an initial or always block
 Never connected to something
 Can be used to model latches, flip-flops, etc.,
but do not correspond exactly
 Shared variables with all their attendant problems
Digital IC Design Flow 2004.02.27
Huai-Yi Hsu
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Graduate Institute of Electronics Engineering, NTU
Primitive Cells
 Primitives are simple modules
 Verilog build-in primitive gate
 not, buf:
 Variable outputs, single input (last port)
 and, or, buf, xor, nand, nor, xnor:
 Single outputs (first port), variable inputs
module full_add (S, CO, A, B, CI) ;
--- port Declaration --wire
net1, net2, net3;
xor U0(S,A,B,CI);
and U1(net1, A, B);
and U2(net2, B, CI);
and U3(net3, CI, A);
or U4(CO, net1, net2, net3);
endmodule
Digital IC Design Flow 2004.02.27
Huai-Yi Hsu
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Graduate Institute of Electronics Engineering, NTU
How Are Simulators Used?
 Testbench generates stimulus and checks response
 Coupled to model of the system
 Pair is run simultaneously
Stimulus
Testbench
Result
checker
Digital IC Design Flow 2004.02.27
System Model
Response
Huai-Yi Hsu
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Graduate Institute of Electronics Engineering, NTU
Example: Testbench
module t_full_add();
wire sum, c_out;
reg a, b, cin; // Storage containers for stimulus waveforms
full_add M1 (sum, c_out, a, b, cin); //UUT
initial begin // Time Out
#200 $finish; // Stopwatch
end
initial begin // Stimulus patterns
#10 a = 0; b = 0; cin = 0; // Statements execute in sequence
#10 a = 0; b = 1; cin = 0;
#10 a = 1; b = 0; cin = 0;
#10 a = 1; b = 1; cin = 0;
#10 a = 0; b = 0; cin = 1;
#10 a = 0; b = 1; cin = 1;
#10 a = 1; b = 0; cin = 1;
#10 a = 1; b = 1; cin = 1;
end
endmodule
Digital IC Design Flow 2004.02.27
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Graduate Institute of Electronics Engineering, NTU
Verilog Simulator
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Graduate Institute of Electronics Engineering, NTU
Event-Driven Simulation
 A change in the value of a signal (variable) during simulation is
referred to as an event
 Spice-like analog simulation is impractical for VLSI circuits
 Event-driven simulators update logic values only when signals
change
Digital IC Design Flow 2004.02.27
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Graduate Institute of Electronics Engineering, NTU
Styles
Structural - instantiation of primitives and
modules
RTL/Dataflow - continuous assignments
Behavioral - procedural assignments
Digital IC Design Flow 2004.02.27
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Graduate Institute of Electronics Engineering, NTU
Structural Modeling
When Verilog was first developed (1984)
most logic simulators operated on netlists
Netlist: list of gates and how they’re
connected
A natural representation of a digital logic
circuit
Not the most convenient way to express test
benches
Digital IC Design Flow 2004.02.27
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Graduate Institute of Electronics Engineering, NTU
Behavioral Modeling
A much easier way to write testbenches
Also good for more abstract models of circuits
Easier to write
Simulates faster
More flexible
Provides sequencing
Verilog succeeded in part because it allowed
both the model and the testbench to be
described together
Digital IC Design Flow 2004.02.27
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Graduate Institute of Electronics Engineering, NTU
Style Example - Structural
module full_add (S, CO, A, B, CI) ;
module half_add (S, C, X, Y);
output S, CO ;
input A, B, CI ;
output S, C ;
input X, Y ;
wire N1, N2, N3;
xor (S, X, Y) ;
and (C, X, Y) ;
half_add HA1 (N1, N2, A, B),
HA2 (S, N3, N1, CI);
endmodule
or P1 (CO, N3, N2);
endmodule
Digital IC Design Flow 2004.02.27
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Graduate Institute of Electronics Engineering, NTU
Style Example – Dataflow/RTL
module fa_rtl (S, CO, A, B, CI) ;
output S, CO ;
input A, B, CI ;
assign S = A ^ B ^ CI;
assign CO = A & B | A & CI | B & CI;
//continuous assignment
//continuous assignment
endmodule
Digital IC Design Flow 2004.02.27
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Graduate Institute of Electronics Engineering, NTU
Style Example – Behavioral
module fa_bhv (S, CO, A, B, CI) ;
output S, CO ;
input A, B, CI ;
reg S, CO;
// required to “hold” values between events.
always@(A or B or CI)
begin
S <= A ^ B ^ CI;
CO <= A & B | A & CI | B & CI;
end
endmodule
Digital IC Design Flow 2004.02.27
//;
// procedural assignment
// procedural assignment
Huai-Yi Hsu
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Graduate Institute of Electronics Engineering, NTU
How Verilog Is Used
 Virtually every ASIC is designed using either Verilog
or VHDL (a similar language)
 Behavioral modeling with some structural elements
 “Synthesis subset”
 Can be translated using Synopsys’ Design Compiler or
others into a netlist
 Design written in Verilog
 Simulated to death to check functionality
 Synthesized (netlist generated)
 Static timing analysis to check timing
Digital IC Design Flow 2004.02.27
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Graduate Institute of Electronics Engineering, NTU
An Example: Counter
`timescale 1ns/1ns
module counter;
reg clock;
// declare reg data type for the clock
integer count;
// declare integer data type for the count
initial
// initialize things - this executes once at start
begin
clock = 0; count = 0;
// initialize signals
#340 $finish;
// finish after 340 time ticks
end
/* an always statement to generate the clock, only one statement follows the always so we don't
need a begin and an end */
always
#10 clock = ~ clock;
// delay is set to half the clock cycle
/* an always statement to do the counting, runs at the same time (concurrently) as the other always
statement */
always
begin
// wait here until the clock goes from 1 to 0
@ (negedge clock);
// now handle the counting
if (count == 7)
count = 0;
else
count = count + 1;
$display("time = ",$time," count = ", count);
end
endmodule
Digital IC Design Flow 2004.02.27
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Graduate Institute of Electronics Engineering, NTU
An Example: Counter (cont’d)
Verilog using ModelSim








>
#
#
#
#
#
#
#
#
#
#
Assume working directory: VlogExamples/Counter
Invoke ModelSim
Change Directory to VlogExamples/Counter
Copy file counter.v to the working directory
Create a design library: vlib work
Compile counter.v: vlog counter.v
Start the simulator: vsim counter
Run the simulation: e.g., run 200ns
run 200
time =
time =
time =
time =
time =
time =
time =
time =
time =
time =
Digital IC Design Flow 2004.02.27
20
40
60
80
100
120
140
160
180
200
count
count
count
count
count
count
count
count
count
count
=
=
=
=
=
=
=
=
=
=
Huai-Yi Hsu
1
2
3
4
5
6
7
0
1
2
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Graduate Institute of Electronics Engineering, NTU
ModelSim Simulator
 Creating a Project
 Select Create a Project from the Welcome to ModelSim dialog box.
 Or select File >New > Project from the ModelSim Main window.
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Add File to Project
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Compile
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Load Design
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List Signals
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Graduate Institute of Electronics Engineering, NTU
Run Simulation
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Graduate Institute of Electronics Engineering, NTU
Silos Verilog Logic Simulator
 Free HDL simulator
 Web:http://www.simucad.com/free_verilog_simulator/index.shtm
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Edit Verilog Files
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Create New Project
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Add File to Project
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Starting Simulation
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Silos Overview
 Silos is a logic simulation environment developed for
use in the design and verification of electronic circuits
and systems.
 Silos can simulate designs at the behavioral, gate
and switch levels that are modeled with the Verilog
Hardware Description Language (HDL).
 Silos can back annotate delays specified using the
Standard Delay Format (SDF).
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Graduate Institute of Electronics Engineering, NTU
Debugging Capabilities
 The mouse cursor can be held over variables and expressions
in the source code to directly see their value at a time point.
 Drag and drop variables and expressions directly from the
source file into the Data Analyzer waveform window, or from the
Silos Explorer to the Data Analyzer window to provides easy
access to the simulation results.
 Unlimited traceback for behavioral and gate designs quickly
isolates the cause of Unknown levels.
 A graphical Finite State Machine entry, source code generation,
documentation, and debugging tool.
 Code Coverage reporting for Line reports and Operator reports
display a purple dot beside any line or operator that was not
executed by the testbench.
Digital IC Design Flow 2004.02.27
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Graduate Institute of Electronics Engineering, NTU
Summary
IC design flow
History of Verilog-HDL
Verilog simulator
Next course
Basic concept of Verilog-HDL
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Graduate Institute of Electronics Engineering, NTU
Homework #0
Download the Verilog Simulator
Setup the Verilog simulation environment.
Opening new project
Add Verilog file to project
Run simulation
Website: http://access.ee.ntu.edu.tw
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Multiplexer Built From Primitives
module mux(f, a, b, sel);
output f;
input a, b, sel;
Verilog programs built
from modules
Each module has
an interface
and
Module may contain
structure: instances of
primitives and other
modules
or
not
g1(f1, a, nsel),
g2(f2, b, sel);
g3(f, f1, f2);
g4(nsel, sel);
endmodule
a
g4
nsel
g3
b
sel
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g1
f1
g2
Huai-Yi Hsu
f
f2
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Graduate Institute of Electronics Engineering, NTU
Multiplexer Built From Primitives
module mux(f, a, b, sel);
output f;
input a, b, sel;
and
or
not
Identifiers not
explicitly defined
default to wires
g1(f1, a, nsel),
g2(f2, b, sel);
g3(f, f1, f2);
g4(nsel, sel);
endmodule
a
g4
nsel
g3
b
sel
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g1
f1
g2
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f
f2
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Graduate Institute of Electronics Engineering, NTU
Multiplexer Built With Always
module mux(f, a, b, sel);
output f;
input a, b, sel;
reg f;
always @(a or b or sel)
if (sel) f = b;
else f = a;
Modules may contain one
or more always blocks
Sensitivity list
contains signals
whose change
triggers the
execution of the
block
endmodule
a
f
b
sel
Digital IC Design Flow 2004.02.27
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Graduate Institute of Electronics Engineering, NTU
Multiplexer Built With Always
module mux(f, a, b, sel);
output f;
input a, b, sel;
reg f;
A reg behaves like memory:
holds its value until
imperatively assigned
otherwise
always @(a or b or sel)
if (sel) f = a;
else f = b;
Body of an always
block contains
traditional imperative
code
endmodule
a
f
b
sel
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Graduate Institute of Electronics Engineering, NTU
Mux with Continuous Assignment
module mux(f, a, b, sel);
output f;
input a, b, sel;
LHS is always set to the
value on the RHS
Any change on the right
causes reevaluation
assign f = sel ? a : b;
endmodule
a
f
b
sel
Digital IC Design Flow 2004.02.27
Huai-Yi Hsu
pp. 69
Graduate Institute of Electronics Engineering, NTU
Mux with User-Defined Primitive
primitive mux(f, a, b, sel);
output f;
input a, b, sel;
table
1?0 : 1;
0?0 : 0;
?11 : 1;
?01 : 0;
11? : 1;
00? : 0;
endtable
endprimitive
Behavior defined using a
truth table that includes
“don’t cares”
This is a less pessimistic
than others: when a & b
match, sel is ignored
(others produce X)
a
f
b
sel
Digital IC Design Flow 2004.02.27
Huai-Yi Hsu
pp. 70
Graduate Institute of Electronics Engineering, NTU
GLITCHES AND STATIC HAZARDS
 The output of a combinational circuit may make a transition even though the
patterns applied at its inputs do not imply a change. These unwanted switiching
transients are called "glitches."
 Glitches are a consequence of the circuit structure and the application of
patterns that cause the glitch to occur. A circuit in which a glitch may occur under
the application of appropriate inputs signals is said to have a hazard.
 A static 1-hazard occurs if an output has an initial value of 1, and an input
pattern that does not imply an output transition causes the output to change to 0
and then return to 1.
 A static 0-hazard occurs if an output has an initial value of 0, and an input
pattern that does not imply an output transition causes the output to change to 1
and then return to 0.
Digital IC Design Flow 2004.02.27
Huai-Yi Hsu
pp. 71
Graduate Institute of Electronics Engineering, NTU
STATIC HAZARDS
 Static hazards are caused by differential propagation delays on
reconvergent fanout paths.
A "minimal"realization:
F = AC + BC'
 Static hazards can be eliminated by introducing redundant cubes in the
cover of the output expression (the added cubes are called a hazard
cover).
For the hazard-free cover:
F = AC + BC' + AB
Digital IC Design Flow 2004.02.27
Huai-Yi Hsu
pp. 72
Graduate Institute of Electronics Engineering, NTU
DYNAMIC HAZARDS (Multiple glitches)
 A circuit has a dynamic hazard if an input transition is supposed
to cause a single transition in an output, but causes two or more
transitions before reached its expected value.
 Dynamic hazards are a consequence of multiple static hazards
caused by multiply reconvergent paths in a multilevel circuit.
 Dynamic hazards are not easy to eliminate.
 Elimination of all static hazards eliminates dynamic hazards.
 Approach: Transform a multilevel circuit into a two-level circuit
and eliminate all of the static hazards.
Digital IC Design Flow 2004.02.27
Huai-Yi Hsu
pp. 73
Graduate Institute of Electronics Engineering, NTU
Example
Digital IC Design Flow 2004.02.27
Huai-Yi Hsu
pp. 74
Graduate Institute of Electronics Engineering, NTU
STORAGE ELEMENTS: R-S LATCH
 Storage elements are used to store information in a binary
format (e.g. state, data, address, opcode, machine status).
 Storage elements may be clocked or unclocked.
 Two types: level-sensitive, edge-sensitive
Digital IC Design Flow 2004.02.27
Huai-Yi Hsu
pp. 75
Graduate Institute of Electronics Engineering, NTU
STORAGE ELEMENTS:
TRANSPARENT LATCHES
 Latches are level-sensitive storage elements; data storage is
dependent on the level (value ) of the input clock (or enable) signal.
The output of a transparent latch changes in response to the data input
while the latch is enabled. Changes at the input are visible at the output
data
Digital IC Design Flow 2004.02.27
Huai-Yi Hsu
pp. 76
Graduate Institute of Electronics Engineering, NTU
STORAGE ELEMENTS: FLIP-FLOPS
 Flip-flops are edge-sensitive storage elements; data storage is
synchronized to an edge of a clock. The value of data stored depends
on the data that is present at the data input(s) when the clock makes a
transition at its active (rising or falling) edge.
Digital IC Design Flow 2004.02.27
Huai-Yi Hsu
pp. 77
Graduate Institute of Electronics Engineering, NTU
MASTER-SLAVE FLIP-FLOP
Digital IC Design Flow 2004.02.27
Huai-Yi Hsu
pp. 78
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