Rapidly Prototyping DSP Extensions Using CoDeL:
The DWT Using Lifting
Nainesh Agarwal and Nikitas Dimopoulos
University of Victoria, Canada
May 3, 2005
18th Canadian Conference on Electrical and Computer Engineering
Outline
• Hardware Description Languages
– System Level Design Languages
•
•
•
•
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CoDeL
5/3 Discrete Wavelet Transform
Implementation
Conclusion
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Hardware Description Languages
• Describe the temporal and spatial behaviour of a
circuit
• Common targets: ASIC and FPGA
• VHDL and Verilog
– Design at Register Transfer Level (RTL)
• Abstraction level too low
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System Level Design Languages
• Started late 1990s
• Provide a high level of abstraction for
system development
• Categories
– Extend existing HDLs: SystemVerilog
– Extend existing software languages:
SystemC, SpecC, Handel-C, JHDL
– Newly created languages: Rosetta,
CoDeL
• Algorithmic level design
– Only CoDeL and Handel-C
HDL
(RTL)
Assembly
Language
Higher Abstraction
Fast development
Easy to learn
Platform independence
High Level
Languages:
C, Java
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SLDL
4
CoDeL - Overview
• CoDeL (Controller Description Language), targets the
specification and design at the behavioral level.
• Order of the statements implicitly represents the sequence of
activities.
• Extracts the data and control flow from the program
automatically, assigns the necessary hardware blocks and
exploits inherent parallelism.
• Similar to the C language, so easy to learn.
• Includes a library of I/O protocols that simplify (sub)system
interaction.
• Compiler produces synthesizable VHDL code which can be
targeted to any technology including FPGA or ASIC.
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CoDeL - Structure Declaration
• Hierarchical structures
• Accessed using dot
notation
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CoDeL - Module Declaration
• Module name
• Input/output ports
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CoDeL – Ports and Protocols
• CoDeL abstracts module interaction through ports
and protocols.
• Protocols define the sequence of events necessary to
transfer information from one module to another.
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CoDeL – Example Protocol
• Example of a handshake protocol
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CoDeL – Simple Counter Example
• A very simple counter
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Discrete Wavelet Transform (DWT)
• Key component in JPEG2000 image compression
• Lossy compression using MIT 9/7 wavelet
• Lossless compression using Le Gall 5/3 integer-tointeger wavelet
– Integer to integer mapping
– No quantization needed
– Exact recovery of input signal
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DWT Structure
• Successive pair of low-pass and high-pass filters, followed by
factor 2 downsampling
• Analysis stage decomposes, while synthesis reconstructs
• h0 is the low-pass filter and h1 is the high-pass filter
• Low-pass signal recursively decomposed for full, dyadic
transform
Analysis Filter Bank
h0
Synthesis Filter Bank
2
2
g0
^
x(n)
x(n)
h1
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2
2
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g1
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DWT - Lifting
• Reduction in memory and computational complexity
• In-place computation of the wavelet coefficients
• Output is identical to a direct filter bank convolution
Even samples
Input
Lazy
Transform
+
Predict
Low-pass
output
Update
High-pass
output
Odd samples
-
Predict
Update
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Implementation
Analysis Filter
Bank Module
Start
fStart
fReady
Start
Ready
StartPt
StartPt
EndPt
EndPt
Step
Step
DWT Module Pseudocode
if (Forward Transform) {
Ready
StepSize = 1
Register File
M (Rows)
N (Cols)
Size (M*N)
iStart
iReady
Start
Ready
while (StepSize < EndPt) {
perform decomposition
StepSize = StepSize * 2
}
StartPt
Forward/Inverse
} else (Inverse Transform) {
EndPt
DWT Module
Step
StepSize = (EndPt+1)/2
Synthesis Filter
Bank Module
while (StepSize > 0) {
perform synthesis
StepSize = StepSize / 2
}
}
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Code Complexity
• Analysis and synthesis filter bank modules
– 120 lines of CoDeL code each
– Generate 1170 and 840 lines of VHDL code, respectively.
• DWT module
– 50 lines of CoDeL code
– Generates 270 lines of VHDL
• Synthesized on a Xilinx 2v2000ff896-4 FPGA
– About 6% area used
– Maximum clock frequency of 103 MHz
• Eight element DWT takes 3.9μs
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Conclusion
• CoDeL is an easy and rapid environment for
architecture development
• Few lines of code needed for architecture description
• Working on enhancements to the compiler such as
register and state reuse
• CoDeL needs to be extended to allow explicit
parallelism.
– Compiler directives (similar to the technique used in
OpenMP and Handel-C) could be used.
• Allow power efficient architectures through
dependency analysis
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Questions
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