Introduction to Intel IA-32 and IA-64
Instruction Set Architectures
The code we used in the class
• The assembly code is
http://www.cs.fsu.edu/~zzhang/CDA3100_Spring_2009_files/first.asm
• The inline assembly code is:
http://www.cs.fsu.edu/~zzhang/CDA3100_Spring_2009_files/tryasm.c
History
9/27/2007 11:23:26 PM
week06-3.ppt
3
Recent Intel Processors
•
•
•
•
The Intel® Pentium® 4 Processor Family (2000-2006)
The Intel® Xeon® Processor (2001-2006)
The Intel® Pentium® M Processor (2003-Current)
The Intel® Pentium® Processor Extreme Edition (20052007)
• The Intel® Core™ Duo and Intel® Core™ Solo
Processors (2006-Current)
• The Intel® Xeon® Processor 5100 Series and Intel®
Core™2 Processor Family (2006-Current)
9/27/2007 11:23:26 PM
week06-3.ppt
4
History
9/27/2007 11:23:27 PM
week06-3.ppt
5
Most Recent Intel Processors
9/27/2007 11:23:27 PM
week06-3.ppt
6
Intel Core 2 Duo Processors
9/27/2007 11:23:28 PM
week06-3.ppt
7
Intel Core 2 Quad Processors
9/27/2007 11:23:28 PM
week06-3.ppt
8
Bit and Byte Ordering
9/27/2007 11:23:29 PM
week06-3.ppt
9
Intel Assembly
• Each instruction is represented by
– Where label presents the line
– A mnemonic is a reserved name for a class of
instruction opcodes which have the same
function.
– The operands argument1, argument2, and
argument3 are optional. There may be from zero
to three operands, depending on the instruction
9/27/2007 11:23:29 PM
week06-3.ppt
10
Memory Modes
9/27/2007 11:23:30 PM
week06-3.ppt
11
Addressing
• The processors use byte addressing
• Intel processors support segmented addressing
– Each address is specified by a segment register and byte
address within the segment
9/27/2007 11:23:30 PM
week06-3.ppt
12
9/27/2007 11:23:30 PM
week06-3.ppt
13
Intel Registers
9/27/2007 11:23:31 PM
week06-3.ppt
14
Basic Program Execution Registers
• General purpose registers
– There are eight registers (note that they are not
quite general purpose as some instructions
assume certain registers)
• Segment registers
– They define up to six segment selectors
• EIP register – Effective instruction pointer
• EFLAGS – Program status and control register
9/27/2007 11:23:31 PM
week06-3.ppt
15
General Purpose and Segment Registers
9/27/2007 11:23:32 PM
week06-3.ppt
16
General Purpose Registers
•
•
•
•
•
EAX — Accumulator for operands and results data
EBX — Pointer to data in the DS segment
ECX — Counter for string and loop operations
EDX — I/O pointer
ESI — Pointer to data in the segment pointed to by the DS
register; source pointer for string operations
• EDI — Pointer to data (or destination) in the segment pointed
to by the ES register; destination pointer for string operations
• ESP — Stack pointer (in the SS segment)
• EBP — Pointer to data on the stack (in the SS segment)
17
Alternative General Purpose Register Names
18
Registers in IA-64
19
Segment Registers
20
Operand Addressing
• Immediate addressing
– Maximum value allowed varies among
instructions and it can be 8-bit, 16-bit, or 32-bit
• Register addressing
– Register addressing depends on the mode (IA-32
or IA-64)
21
Register Addressing
22
Memory Operand
• Memory operand is specified by a segment and offset
23
Offset
• Displacement - An 8-, 16-, or 32-bit value.
• Base - The value in a general-purpose register.
• Index — The value in a general-purpose
register.
• Scale factor — A value of 2, 4, or 8 that is
multiplied by the index value.
24
Effective Address
25
Effective Address
• Common combinations
– Displacement
– Base
– Base + displacement
– (Index * scale) + displacement
– Base + index + displacement
– Base + (Index * scale) + displacement
26
Addressing Mode Encoding
27
Fundamental Data Types
28
Example
29
Pointer Data Types
• Near pointer
• Far pointer
30
128-Bit SIMD Data Types
31
BCD Integers
• Intel also supports BCD integers, where each
digit (0-9) is represented by 4 bits
32
Floating Point Numbers
33
General Purpose Instructions
• Data transfer instructions
34
Data Transfer Instructions
35
Data Transfer Instructions
36
Binary Arithmetic Instructions
37
Decimal Arithmetic Instructions
38
Logical Instructions
39
Shift and Rotate Instructions
40
Bit and Byte Instructions
41
Bit and Byte Instructions
42
Control Transfer Instructions
43
44
String Instructions
45
I/O Instructions
• These instructions move data between the
processor’s I/O ports and a register or memory
46
Enter and Leave Instructions
• These instructions provide machine-language support
for procedure calls in block structured languages
47
Segment Register Instructions
• The segment register instructions allow far pointers
(segment addresses) to be loaded into the segment
registers
48
Procedure Call Types
• The processor supports procedure calls in
the following two different ways:
– CALL and RET instructions.
– ENTER and LEAVE instructions, in conjunction
with the CALL and RET instructions
49
Stack
50
Calling Procedures Using CALL and RET
• Near call (within the current code segment)
• Near return
51
Far Call and Far Return
• Far call
• Far return
52
Stack During Call and Return
53
Parameter Passing
• Passing parameters through the general-purpose
registers
– Can pass up to six parameters by copying the parameters
to the general-purpose registers
• Passing parameters on the stack
– Stack can be used to pass a large number of parameters
and also return a large number of values
• Passing parameters in an argument list
– Place the parameters in an argument list
– A pointer to the argument list can then be passed
to the called procedure
54
Saving Procedure State Information
• The processor does not save general purpose
registers
– A calling procedure should explicitly save the values in any
of the general-purpose registers that it will need when it
resumes execution after a return
– One can use PUSHA and POPA to save and restore all the
general purpose registers (except ESP)
55
Calls to Other Privilege Levels
56
Stack For Calling and Called Procedure
57
Procedure Calls For Block-structured Languages
• ENTER and LEAVE instructions automatically
create and release, respectively, stack frames
for called procedures
– The ENTER instruction creates a stack frame
compatible with the scope rules typically used in
block-structured languages
– The LEAVE instruction, which does not have any
operands, reverses the action of the previous
ENTER instruction
58
ENTER Instruction
59
IA-32 and IA-64 Instruction Format
60
Examples of Instruction Formats
61
ADD Instructions
62
ADD Instructions
63
Add Instruction Description
64
SCAS/SCASB/SCASW/SCASD—Scan String
65
SIMD in IA-32 and IA-64
• To improve performance, Intel adopted SIMD (single
instruction multiple data) instructions
– MMX technology (Pentium II processor family)
– SSE
10/7/2007 9:37:48 PM
week07-1.ppt
66
MMX
• MMX introduced
– Eight new 64-bit data registers,
called MMX registers
– Three new packed data types:
• 64-bit packed byte integers (signed
and unsigned)
• 64-bit packed word integers
(signed and unsigned)
• 64-bit packed double word
integers (signed and unsigned)
– Instructions that support the
new data types
10/7/2007 9:37:59 PM
week07-1.ppt
67
MMX
• Packed integer types allow operations to be applied
on multiple integers
10/7/2007 9:38:00 PM
week07-1.ppt
68
SSE
• SSE introduced eight 128-bit data registers (called
XMM registers)
– In 64-bit modes, they are available as 16 64-bit registers
– The 128-bit packed single-precision floating-point data
type, which allows four single-precision operations to be
performed simultaneously
• They can be used in parallel with MMX registers
10/7/2007 9:38:04 PM
week07-1.ppt
69
SSE Execution Environment
10/7/2007 9:38:04 PM
week07-1.ppt
70
XMM Registers
• In certain modes, additional eight 64 bit
registers are also available (XMM8 - XMM15)
10/7/2007 9:38:05 PM
week07-1.ppt
71
SSE Data Type
• SSE extensions introduced one new data type
– 128-Bit Packed Single-Precision Floating-Point Data Type
– SSE 2 introduced five data types
10/7/2007 9:38:05 PM
week07-1.ppt
72
Packed and Scalar Double-Precision Floating-Point Operations
10/7/2007 9:38:07 PM
week07-1.ppt
73
SSE Instructions
• SSE Data Transfer Instructions
10/7/2007 9:38:10 PM
week07-1.ppt
74
SSE Packed Arithmetic Instructions
10/7/2007 9:38:11 PM
week07-1.ppt
75
SSE Packed Arithmetic Instructions
10/7/2007 9:38:12 PM
week07-1.ppt
76
SSE Comparison, Logical, and Shuffle Instructions
10/7/2007 9:38:12 PM
week07-1.ppt
77
SSE2 Instructions
10/7/2007 9:38:14 PM
week07-1.ppt
78
SSE2 128-Bit SIMD Integer Instructions
10/7/2007 9:38:14 PM
week07-1.ppt
79
Horizontal Addition/Subtraction
10/7/2007 9:38:16 PM
week07-1.ppt
80
Horizontal Data Movements
10/7/2007 9:38:17 PM
week07-1.ppt
81
Conversion Between Different Types
10/7/2007 9:38:17 PM
week07-1.ppt
82
Using MMX/SSE Instructions in C/C++ Programs
• Data types for MMX and SSE instructions
– These types are defined in C/C++
• /usr/lib/gcc/i386-redhat-linux/3.4.3/include/mmintrin.h
• /usr/lib/gcc/i386-redhat-linux/3.4.3/include/pmmintrin.h
• /usr/lib/gcc/i386-redhat-linux/3.4.3/include/emmintrin.h
10/7/2007 9:38:18 PM
week07-1.ppt
83
Built-in Functions
• Built-in functions are C-style functional interfaces
to MMX/SSE instructions
See http://developer.apple.com/documentation/DeveloperTools/gcc-4.0.1/gcc/X86-Built_002din-Functions.html
10/7/2007 9:38:29 PM
week07-1.ppt
84
Intel MMX/SSE Intrinsics
• Intrinsics are C/C++ functions and procedures for
MMX/SSE instructions
– With instrinsics, one can program using these instructions
indirectly using the provided intrinsics
– In general, there is a one-to-one correspondence between
MMX/SSE instructions and intrinsics
10/7/2007 10:01:41 PM
week07-1.ppt
85
GCC Inline Assembly
• GCC inline assembly allows us to insert inline
functions written in assembly
– GCC provides the utility to specify input and output
operands as C variables
– Basic inline
– Extended inline assembly
10/7/2007 10:01:43 PM
week07-1.ppt
86
GCC Inline Assembly
• Some examples
10/7/2007 10:03:01 PM
week07-1.ppt
87
GCC Inline Assembly
10/7/2007 10:03:04 PM
week07-1.ppt
88
GCC Inline Assembly
10/7/2007 10:03:06 PM
week07-1.ppt
89
Descargar

Slide 1