Advanced Digital Design
Description Methods
by A. Steininger, J. Lechner and R. Najvirt 1
Vienna University of Technology
Outline
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Utilizing the potential of asynchronous
circuits
Description methods
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Standard HDL
STG, PRS, AFSM, TEL
Balsa, Haste, CHP
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Before the description comes
the design
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Once a circuit is described,
optimization is limited to what
is in the description
The design of an average-case
performing circuit is different than
that of a worst-case timed one
This especially holds for the bundled
data style but not only
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Average-Case Design
Example
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A pipeline designed as if it was
synchronous...
Clk
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Average-Case Design
Example
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...now bundled data asynchronous
How much better is the performance?
Ctrl
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Average-Case Design
Example
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What about now?
Ctrl
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Average-Case Design
Example
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The same now delay insensitively
How is the performance?
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Average-Case Design
Example
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What about now?
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Average-Case Design
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In synchronous, concentrate on the
worst path only
In asynchronous, create sets of paths
with own worst path that are chosen
from dynamically
Many optimization options
Somewhat similar to power
optimization in synchronous circuits
One should know the capabilities of
the tool in use
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Description of Async. Circuits
with Standard HDL
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Description with standard HDL at low
level (gate instantiations) naturally
possible
It can also be used as a higher level
design entry if the tool supports it
For example: Null Convention Logic
Timing requirements, if necessary, are
difficult to express
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Null Convention Logic
Design Entry
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Circuit description in VHDL/Verilog with
special coding style
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Explicit coding of register
components/control network
Data path can be described like for
ordinary synchronous circuits
NCL library
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Single-rail data signals with data types for
multi-valued logic: 0, 1, N, U, X, Z, Overloaded operators
Hysteresis function for simulation
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Null Convention Logic
Design Entry Example
library ncl;
use ncl.ncl_logic.all,ncl.ack_logic.all;
use ncl.ncl_components.all;
entity enc_4_to_2 is
port (
din: in ncl_logic_vector(4 downto 1);
ack_in, reset: in ack_logic;
ack_out : out ack_logic;
dout: out ncl_logic_vector(2 downto 1));
end enc_4_to_2;
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Null Convention Logic
Design Entry Example
architecture behave of enc_4_to_2 is
signal b: ncl_logic_vector(2 downto 1);
begin
encode : process(din)
begin
...
end process encode;
ir1: ncl_register_ss
generic map (width => 2, initial_value => -1,
stages => 1)
port map (datain => d, ki => ack_in,
rst => reset, dataout => dout, ko => ack_out);
end behave;
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Specialized HDLs
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Describing async. circuits with
standard HDL can feel like hacking
wrong tools to do the right thing
An overview of HDLs made for
asynchronous:
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Low level – STG, PRS, AFSM, TEL
High level – Balsa, Haste, CHP
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Signal Transition Graphs (STG)
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Everybody should know them by now
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Production Rule Sets (PRS)
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The representation for an intermediate
step of the Martin synthesis (Caltech
Asynchronous Synthesis Tools).
Describes CMOS stacks directly
Generalized C-Element as in previous
lecture.
G1
G2
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Production Rule Sets (PRS)
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G is called the guard
x is the assignment
x  x = 0 must hold by definition
(non-interference)
x  x = 1 implements combinational
gate, if it can be 0 it is state holding
Guards must be stable (not change
until output stable)
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Burst Mode FSM
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NCL Half adder:
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Burst Mode FSM
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Extension of fundamental mode AFSM
The next-state function operates on
input bursts, produces output bursts
No input burst can be a subset of an
input burst of another transition going
from the same state
Restricted fundamental mode still
required – once a transition can
happen, no input can change before
the SM has stabilized
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Timed Event/Level Structures
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Dependencies similar to STGs
Guards similar to PRSs
Additionally, timing bounds
Nodes are events, edges are rules
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Timed Event/Level Structures
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Instead of conflict places, conflicts are
enlisted separately
Rules can be:
marked
enabled
satisfied
expired
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Communicating Hardware
Processes
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Design entry to Martin’s synthesis
process developed at Caltech
Based on Hoare’s Communicating
Sequential Processes formalism – like
many other parallel programming
languages
Documentation practically
unobtainable, yet used in many
publications
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Communicating Hardware
Processes
Main constructs:
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Simple assignment:
v := true or v := false
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Deterministic selection
[G1 -> S1 [] G2 -> S2]
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[G] is
Nondeterministic selection
[G -> skip]
[G1 -> S1 | G2 -> S2]
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Repetition
*[G1 -> S1 [] G2 -> S2]
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Sequencing and concurrent execution
S1; S2
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*[S] is *[true -> S]
and S1, S2
Communication
C (synchronization)
C?x (reception)
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C!x (transmission)
#C (probe)
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Communicating Hardware
Processes
Example – what does this do?
adide = process(X?int(8), Y?int(8),
Z!int(8))
u : int(8)
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*[ [ X ==>X?u; Z!u
| Y ==>Y?u; Z!u
]]
end
Lecture "Advanced Digital Design"
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/ TU Vienna
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Communicating Hardware
Processes
Lecture "Advanced Digital Design"
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Balsa
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Asynchronous high-level HDL &
complete synthesis framework
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Based on Tangram system by Philips
Open-Source: Developed at University of
Manchester
Syntax-directed compilation
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1-to-1 mapping of language constructs to
handshake circuit components
Allows experienced designer to easily
envision the resulting circuit but limits
optimization potential
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The Balsa Language
Overview
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Similar to a typical imperative
programming language
Strongly typed
Circuit described with procedures
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Like VHDL entity/architecture
Parameters represent in/out channels
Procedure call like component instantiation
procedure foo (input i : byte; output o : byte) is
-- Local declarations
Begin
-- Implementation
end
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The Balsa Language
Types
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Types based on bit vectors
Numeric types
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Enumerations
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Unsigned: Range [0, 2n-1]
Signed: Range [-2n-1, -2n-1-1]
Named numeric values
Records
Arrays
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The Balsa Language
Operators
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Standard logic/arithmetic operators
Control operators
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Channel Operators
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Sequence operator (;)
Parallel composition (||)
Sync Command
Read (->)
Write (<-)
Variable Assignment (:=)
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The Balsa Language
Conditional Execution
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If statements
-- Sequential evaluation
-- Concurrent evaluation
if <Condition1> then
<Command1>
else
if <Condition2> then
<Command2>
end
end
if <Condition1> then <Command1>
| <Condition2> then <Command2>
end
Case statements
case x+y of
1 .. 4, 11 then o <- x
| 5 .. 10 then o <- y
else o <- z
end
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The Balsa Language
Loops
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Iterative execution (while loop)
-- Simple while
while <Condition> then
<Command>
end
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-- Multiple guards
while
<Condition1> then <Command1>
| <Condition2> then <Command2>
| <Condition3> then <Command3>
end
Structural iteration (for loop)
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Hardware instantiated for each iteration
Comparable to “for ... generate” in VHDL
-- Sequential for
for ; i in 1 .. max_count
then
<Command>
end
Lecture "Advanced Digital Design"
-- Parallel for
for || i in 1 .. max_count then
<Command>
end
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Example:
1-place Buffer
(-- buffer1.balsa:
Balsa program defining an 8 bit wide single
place buffer --)
import [balsa.types.basic]
procedure buffer1 (input i : byte; output o : byte) is
variable x : byte
begin
loop
i -> x
-- Input communication
;
-- Sequence operator
o <- x
-- Output communication
end
end
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Example:
2-place Buffer
(-- buffer2.balsa:
a 2-place buffer using parallel composition --)
import [balsa.types.basic]
import [buffer1]
procedure
channel
begin
buffer1
buffer1
end
buffer2 (input i : byte; output o : byte) is
c : byte
(i, c) ||
(c, o)
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Example:
Modulo-10 Counter
import [balsa.types.basic]
type C_size is nibble
constant max_count = 9
procedure count10(sync aclk; output count: C_size) is
variable count_reg : C_size
variable tmp : C_size
begin
loop
sync aclk;
if count_reg /= max_count then
tmp := (count_reg + 1 as C_size)
else
tmp := 0
end || count <- count_reg ;
count_reg := tmp
end -- loop
end -- begin
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Haste
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Based on Tangram, very similar to
Balsa in syntax
Design environment TiDE, distributed
by Handshake Solutions, later Philips
Semi.
Has additional constructs e.g. for level
sensitive signals
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Haste
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Conclusion/Summary
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Asynchronous design is not quite the
same as synchronous
Specialized description methods allow
for EDA tool support
Still active field of research – many
methods, many tools
Presented description methods
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Allow for high-level modeling (RTL)
Proven for real-life circuits
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