ECE-545, Introduction to VHDL
Prof. K. J. Hintz
Department of Electrical and
Computer Engineering
George Mason University
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Introduction
Administration
 Why VHDL?
 Alternative languages
 Models of Digital Systems
 Basic Structure of VHDL
 VHDL Lexicography

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Administrative
Instructor: Prof. K. J. Hintz
 Course Information

– My home page
http://cpe.gmu.edu/~khintz
– Computer Engineering web site
» http://cpe.gmu.edu
» http://129.174.140.5
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Administrative

Office
– Science and Technology II, Room 225

Office Hours
– See home page
– Other Times by Appointment

Office Phone
– (703)993-1592 (Answering Machine)
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Administrative

Email
– [email protected]

Students with Disabilities
– If you need special assistance, please inform me
soon so that we can work something out.

A milestone chart and homework
assignments are available on the 545 web
site.
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Grading

HW
25%

Mid-Term Exam
35%

Final Exam
40%
– Optional semester long project
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Homeworks
Homeworks Require Use of MGC VHDL
 Mentor Graphics, ModelSim

– cpe02.gmu.edu, Computer Engineering Lab
X-terminals
 Off-campus access on PCs available
through VNC, Linux, Cygus

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Required Textbook

The Designer’s Guide to VHDL
–
–
–
–
–
–
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Peter J. Ashenden
Morgan-Kaufman
ISBN 1-55860-270-4 (paperback)
LOC TK7888.3.A863
Dewey Decimal 621.39’2--dc20
2nd Edition, Copyright 2002
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Local web Resources

IEEE Interactive VHDL Tutorial
– On-line on Computer Engineering Home page
– http://cpe.gmu.edu
– password protected

IEEE Standard 1076-1993
– On-line on Computer Engineering Home page
– password protected
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Optional Resources

Cypress Semiconductor (Warp release 6.x)
–
–
–
–
–

http://www.cypress.com
PC-based
$99 with textbook, possibly free
Oriented towards Their PLD & FPGA devices
VHDL Subset simulator
Xilinx FPGA, ISE
– http://www.xilinx.com
– Student edition, Prentice-Hall
– Schematic, FSM, VHDL
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Optional Resources

Ashenden CDROM (2nd Edition)
– Source Code
– FTL Simulator
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Honor Code

You Are Encouraged to Collaborate With
Other Students

Exams Are Closed Book, Closed Notes, and
the Normal Honor Code Applies to All
Exams
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RASSP

Some of the materials used in this course
come from ARPA RASSP Program and are
copyright
– Rapid Prototyping of Application Specific
Signal Processors Program
– http://www.eda.org/rassp/

Rest of materials are copyright K. J. Hintz
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RASSP Roadmap
RASSP DESIGN LIBRARIES AND DATABASE
Primarily
software
HW
DESIGN
SYSTEM
DEF.
FUNCTION
DESIGN
Primarily
hardware
VIRTUAL PROTOTYPE
HW
FAB
INTEG.
& TEST
HW &
SW
PART.
SW
DESIGN
HW & SW
CODESIGN
SW
CODE
VHDL
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Why HDL?

Achieve Maximum Reliability With
– Minimum cost
– Minimum development time

Allows for Design Automation
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Advantages

Industry Is Moving to
– FPGAs (Field Programmable Gate Array) for system
prototypes and small volume applications
– ASICs (Application Specific Integrated Circuits) for
high-performance/high-volume Systems


Reduces In-field Hardware Maintenance Due to
Fewer Components and Interconnects
High-level Design Tools Are Becoming Available
to Reduce the NRE Costs and Provide Quicker
Turn Around
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Multiple Capabilities Reduce
Board Size/cost
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Design Motivation
Digital System Complexity
 No Longer Able to Breadboard Systems

– Number of chips
– Number of components
– Length of interconnects

Need to Simulate and Verify Before
Committing to Hardware
– Not just logic, but timing
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Breadth Motivation

Different Types of Models are Required at
Various Development Stages
–
–
–
–
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Logic models
Performance models
Timing models
System models
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Value of Models
Formal Expression of System Requirements
 Communicate Actual System Behavior
From Designer to User
 Test & Verification
 Formal Verification of Design
 Allow Automatic Synthesis of Design into
Hardware

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SysGen Design to FPGA
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FPGA Design Process
Implementation
Code In VHDL (RTL)
2. Synthesis and
Implementation
Verification
1. Functional simulation
Aldec, Active HDL 5.1
Synplify Pro 7.2 and Xilinx ISE 4.1
Netlist with timing
3. Timing simulation
Aldec, Active HDL 5.1
Bitstream
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4. Verification
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SLAAC1-V FPGA Board
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Lengua Franca Motivation
Need a Universal Language for Various
Levels of System Design and Designers
 Replacement for Schematics
 Unambiguous, Formal Language
 Partitions Problem

– Design
– Simulation and Verification
– Synthesis (Implementation)
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Legacy Motivation

Standard for Development of Upgrades
– Testbenches and results
– System modifications must still pass original
testbench
– Testbench can (and should) be written by
people other than designers
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Need for HDL

Leads to Computer Aided Implementation-Synthesis
–
–
–
–
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Routing tools
Standard cell libraries
FPGA
CPLD
Formal language description is independent of
physical implementation
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Typical FPGA
Xilinx Virtex XCV 1000
• 0.22 m CMOS process
• 12,288 CLB slices
• ten 4-kbit block RAMs
• 106 equivalent logic gates
• Up to 200 MHz clock
Block RAMs
Configurable Logic
Block
slices (CLB slices)
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Programmable Interconnects
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What Is Inside A Virtex Slice?
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Breadth of HDL

Need a Unified Development Environment
– Errors occur at translations from one stage of
design to another
– HDL language the same at all levels
– All people involved speak the same formal
language
– Testing and verification

Performance, Reliability, and Behavioral
Modeling Available at All Design Levels
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Depth of HDL

Need to Have Power and Flexibility to
Model Digital Systems at Many Different
Levels of Description
– Can model to high or low levels of detail, but
still simulate at all of these levels
– Support “mixed mode” simulation at different
levels of abstraction, representation, and
interpretation with an ability for step-wise
refinement
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VHDL
 VHDL Is
an International IEEE Standard
Specification Language (IEEE 1076-2001)
for Describing Digital Hardware Used by
Industry Worldwide
– VHDL is an acronym for VHSIC (Very High
Speed Integrated Circuit) Hardware
Description Language
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A Brief History of VHDL
 Very
High Speed Integrated Circuit
(VHSIC) Program
– Launched in 1980
– Object was to achieve significant gains in VLSI
technology by shortening the time from
concept to implementation (18 months to 6
months)
– There was a well known need for a common
descriptive and simulation language
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A Brief History of VHDL

Woods Hole Workshop
– Held in June 1981 in Massachusetts
– Discussion of VHSIC goals
– Comprised of members of industry,
government, and academia
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A Brief History of VHDL
 July
1983: contract awarded to develop
VHDL
– Intermetrics
– IBM
– Texas Instruments
 August
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1985: VHDL Version 7.2 released
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A Brief History of VHDL
December 1987: VHDL became IEEE
Standard 1076-1987 and in 1988 an ANSI
standard
 September 1993: VHDL was restandardized
to clarify and enhance the language
 1998: Standard committee convened to
update VHDL-93
 2001: Revised IEEE VHDL Standard

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Languages Other Than VHDL

VHDL: VHSIC (Very High Speed
Integrated Circuit) Hardware Description
Language
– Not the only hardware description language
– Some HDLs are proprietary
– Capabilities and uses of HDLs vary
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ABEL

ABEL
–
–
–
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Simplified HDL
PLD language
Dataflow primitives, e.g., registers
Can use to Program XILINX FPGA
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ALTERA

ALTERA
– Created by Altera Corporation
– Simplified dialect of HDL
» AHDL: Altera Hardware Description Language
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AHPL

AHPL: A Hardware Programming
Language
–
–
–
–
–
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Dataflow language
Implicit clock
Does not support asynchronous circuits
Fixed data types
Non-hierarchical
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CDL

CDL: Computer Design Language
–
–
–
–
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Academic language for teaching digital systems
Dataflow language
Non-hierarchical
Contains conditional statements
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CONLAN

CONLAN: CONsensus LANguage
– Family of languages for describing various
levels of abstraction
– Concurrent
– Hierarchical
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IDL

IDL: Interactive Design Language
– Internal IBM language
– Originally for automatic generation of PLA
structures
– Generalized to cover other circuits
– Concurrent
– Hierarchical
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ISPS

ISPS: Instruction Set Processor
Specification
– Behavioral language
– Used to design software based on specific
hardware
– Statement level timing control, but no gate level
control
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TEGAS

TEGAS: TEst Generation And Simulation
– Structural with behavioral extensions
– Hierarchical
– Allows detailed timing specifications
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TI-HDL

TI-HDL: Texas Instruments Hardware
Description Language
–
–
–
–
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Created at Texas Instruments
Hierarchical
Models synchronous and asynchronous circuits
Non-extendable fixed data types
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VERILOG

Verilog
– Essentially identical in function to VHDL
» No generate statement
– Simpler and syntactically different
» C-like
–
–
–
–
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Gateway Design Automation Co., 1983
Early de facto standard for ASIC programming
Open Verilog International standard
Programming language interface to allow connection to
non-Verilog code
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ZEUS

ZEUS
–
–
–
–
–
–
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Created at General Electric
Hierarchical
Functional Descriptions
Structural Descriptions
Clock timing, but no gate delays
No asynchronous circuits
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Different Representation Models

Some,Not Mutually Exclusive, Models
–
–
–
–
–
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Functional
Behavioral
Dataflow
Structural
Physical
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Gajski and Kuhn’s Y Chart
Architectural
Structural
Behavioral
Algorithmic
System
s Algorithms
Processo
r
Hardware Modules
Functional Block
Logic
Register
Transfer
ALUs, Registers
Gates, FFs
Circuit
Logic
Transistor
Transfer Functions
s
Rectangle
s
Cell, Module Plans
Floor Plans
Cluster
s
Physical Partitions
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Physical/Geometr
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Functional Model

Describes the Logical Function of Hardware
Independent of Any Specific
Implementation or Timing Information
– Can exist at multiple levels of abstraction,
depending on the granularity and the data types
that are used in the behavioral description
– Independent of any particular language
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Behavioral Model

Describes the Function and Timing of
Hardware Independent of Any Specific
Implementation
– Can exist at multiple levels of abstraction,
depending on the granularity of the timing that
are used in the functional description
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Functional & Behavioral
Descriptions

Functional & Behavioral Models May Bear
Little Resemblance to a System’s
Implementation
– Structure is not necessarily implied
Input
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Behavioral
Description
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Output
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Dataflow Model

Describes How Data Moves Through the
System and the Various Processing Steps
– Register Transfer Level (RTL)
» Registers are not native to VHDL
– Hides details of underlying combinational
circuitry and functional implementation
» High-level functional model which my have gross
timing modeled
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Structural Model

Represents a System in Terms of the
Interconnections of a Set of Components
– A design is represented by components and
their interconnects
– Components themselves may be described
structurally, behaviorally, or functionally with
interfaces between the structural and their
behavioral-level implementations
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Structural Descriptions



Pre-Defined VHDL Components Are ‘Instantiated’
and Connected Together
IEEE Standard Libraries for some
Manufacturer’s Libraries for Others
– Xilinx “Core” technology
– Xilinx FPGA specific components (e.g., hardware
adders)

Structural Descriptions May Connect Simple
Gates or Complex, Abstract Components
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Structural Descriptions
 Mechanisms
for Supporting Hierarchical
Description
 Mechanisms for Easily Describing Highly
Repetitive Structures
Input
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Behavioral
Entity
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Output
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Physical Model

Specifies the Relationship Between the
Component Model and the Physical
Packaging of the Component
– Contains all the timing and performance details
to allow for an accurate simulation of physical
reality
– Back annotation allows precise simulations
» Post synthesis all values are known
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Processing of Models

Analysis
– Syntactic and static semantic errors detected

Elaboration
– Expanding and creating design objects
– Reduces all components to signals and processes

Execution
– Discrete Event Simulation (DES)
» Functional model
» Fully synthesized, back-annotated model
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VHDL Model
Package
Ports
Generic
Entity
Behavioral
Functional
Dataflow
Structural
Architect
Architect
Architect
Architect
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VHDL Design Example

Problem: Design a single bit half adder with carry and
enable

Specifications
– Inputs and outputs are each one bit
– When enable is high, result gets x plus y
– When enable is high, carry gets any carry of x plus y
– Outputs are zero when enable input is low
x
y
Half Adder
enable
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carry
result
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VHDL Design Example
Entity Declaration
 As
a first step, the entity declaration
describes the interface of the component
– input and output ports are declared
ENTITY half_adder IS
PORT( x, y, enable: IN BIT;
carry, result: OUT BIT);
END half_adder;
x
y
enable
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Half
Adder
carry
result
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VHDL Design Example
Functional Specification
 A high
level description can be used to
describe the function of the adder
ARCHITECTURE half_adder_a OF half_adder IS
BEGIN
PROCESS (x, y, enable)
BEGIN
IF enable = ‘1’ THEN
result <= x XOR y;
carry <= x AND y;
ELSE
carry <= ‘0’;
result <= ‘0’;
END IF;
END PROCESS;
END half_adder_a;
 The
model can then be simulated to verify
correct functionality of the component
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VHDL Design Example
Behavioral Specification
 A High
Level Description Can Be Used to
Describe the Function of the Adder
 The
ARCHITECTURE half_adder_b OF half_adder IS
BEGIN
PROCESS (x, y, enable)
BEGIN
IF enable = ‘1’ THEN
result <= x XOR y after 10ns;
carry <= x AND y after 12 ns;
ELSE
carry <= ‘0’ after 10ns;
result <= ‘0’ after 12ns;
END IF;
END PROCESS;
END half_adder_b;
Model Can Then Be Simulated to
Verify Correct Timing of the Entity
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VHDL Design Example
Data Flow Specification
 A Third
Method Is to Use Logic Equations
to Develop a Data Flow Description
ARCHITECTURE half_adder_c OF half_adder IS
BEGIN
carry <= enable AND (x AND y);
result <= enable AND (x XOR y);
END half_adder_c;
 The
Model Can Be Simulated at This Level
to Confirm the Logic Equations
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VHDL Design Example
Structural Specification
 As
a Fourth Method, a Structural
Description Can Be Created From
Previously Described Components
 These gates can be taken from a library of
parts
x
y
enable
carry
result
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VHDL Design Example
Structural Specification (Cont.)
ARCHITECTURE half_adder_d OF half_adder IS
COMPONENT and2
PORT (in0, in1 : IN BIT;
out0 : OUT BIT);
END COMPONENT;
COMPONENT and3
PORT (in0, in1, in2 : IN BIT;
out0 : OUT BIT);
END COMPONENT;
COMPONENT xor2
PORT (in0, in1 : IN BIT;
out0 : OUT BIT);
END COMPONENT;
FOR ALL : and2 USE ENTITY gate_lib.and2_Nty(and2_a);
FOR ALL : and3 USE ENTITY gate_lib.and3_Nty(and3_a);
FOR ALL : xor2 USE ENTITY gate_lib.xor2_Nty(xor2_a);
-- description is continued on next slide
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VHDL Design Example
Structural Specification (Cont.)
-- continuing half_adder_d description
SIGNAL xor_res : BIT; -- internal signal
-- Note that other signals are already declared in entity
BEGIN
A0 : and2 PORT MAP (enable, xor_res, result);
A1 : and3 PORT MAP (x, y, enable, carry);
X0 : xor2 PORT MAP (x, y, xor_res);
END half_adder_d;
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VHDL Model Components
 A Complete VHDL Component
Description
Requires a VHDL Entity and a VHDL
Architecture
– The entity defines a component’s interface
– The architecture defines a component’s function
 Several Alternative Architectures
May Be
Developed for Use With the Same Entity
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VHDL Model Components

Areas of Description for a VHDL
Component
–
–
–
–
–
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Structural descriptions
Functional descriptions (no timing)
Timing and delay descriptions (Behavioral)
Dataflow
Mixed behavioral & structural
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Process

Fundamental Unit for Component Behavior
Description Is the Process
– Behavioral models are ultimately made up
exclusively of processes
– Processes may be explicitly or implicitly
defined and are packaged in architectures
– A process is one type of concurrent statement
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VHDL Model Components

Primary Communication Mechanism Is the
Signal (distinct from a variable)
– Process executions result in new values being
assigned to signals which are then accessible to
other processes
– Similarly, a signal may be accessed by a
process in another architecture by connecting
the signal to ports in the the entities associated
with the two architectures
Output <= My_id + 10;
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Entity Declarations
 The
Primary Purpose of the Entity Is to
Declare the Signals in the Component’s
Interface
– The interface signals are listed in the PORT
clause
» In this respect, the entity is akin to the schematic
symbol for the component
– Entity is roughly equivalent to a function
definition in C
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Entity Example
x
y
enable
Half
Adder
carry
result
ENTITY half_adder IS
GENERIC(prop_delay : TIME := 10 ns);
PORT( x, y, enable : IN BIT;
carry, result : OUT BIT);
END half_adder;
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Entity Declarations
Port Clause
 PORT
clause declares the interface signals
of the object to the outside world
PORT (signal_name : mode data_type);
 Three
parts of the PORT clause
– Name
– Mode
– Data type
PORT ( input : IN BIT_VECTOR(3 DOWNTO 0);
ready, output : OUT BIT );
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Entity Declarations
Port Clause (Cont.)
 The
Port Mode of the Interface Describes
the Direction in Which Data Travels With
Respect to the Component
 Five Port Modes
1. In: data comes in this port and can only be
read
2. Out: data travels out this port
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Entity Declarations
Port Clause (Cont.)
3. Buffer: bidirectional data, but only one
signal driver may be enabled at any one time
4. Inout: bidirectional data with any number of
active drivers allowed but requires a Bus
Resolution Function
5. Linkage: direction of data is unknown
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Entity Declarations
Generic Clause
 Generics
May Be Used for Readability,
Maintenance and Configuration
 Generic Clause Syntax :
GENERIC (generic_name : type [:= default_value]);
– If optional default_value missing in generic
clause declaration, it must be present when
component is to be used (i.e. instantiated)
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Behavioral Descriptions
 VHDL Provides
Two Styles of Describing
Component Behavior
– Data Flow: concurrent signal assignment
statements
– Behavioral: processes used to describe
complex behavior by means of high-level
language constructs
» variables, loops, if-then-else statements, etc.
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Generic Clause

Generic Clause Example :
GENERIC (My_ID : INTEGER := 37);
– The generic My_ID, with a default value of 37,
can be referenced by any architecture of the
entity with this generic clause in it
– The default can be overridden at component
instantiation
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Architecture Bodies
Describes the Operation of the Component, Not Just
Its Interface
 More Than One Architecture Can (and Usually Is)
Associated With Each Entity
 Each Architecture Suited to Different Type of
Modeling
 Architecture is roughly equivalent to a function
declaration in C

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Architecture Bodies

Consist of Two Parts
1. Declarative part -- includes necessary
declarations, e.g.
» type declarations
» signal declarations
» component declarations
» subprogram declarations
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Architecture Bodies
2. Statement part -- includes statements that
describe organization and/or functional
operation of component, e.g.
» concurrent signal assignment statements
» process statements
» component instantiation statements
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Architecture Body, e.g.
ARCHITECTURE half_adder_d OF half_adder
IS
-- architecture declarative part
SIGNAL xor_res : BIT ;
-- architecture statement part
BEGIN
carry
<= enable AND (x AND y) ;
result <= enable AND xor_res ;
xor_res <= x XOR y ;
END half_adder_d ;
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Lexical Elements of VHDL

Comments
– two dashes to end of line is a comment, e.g.,
--this is a comment
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Lexical Elements of VHDL

Basic Identifiers
– Can Only Use
» alphabetic letters ( A-Z, a-z ), or
» Decimal digits ( 0-9 ), or
» Underline character ( _ )
– Must Start With Alphabetic Letter ( MyVal )
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Lexical Elements of VHDL

Basic Identifiers
– Not case sensitive
( LastValue = = lAsTvALue)
– May NOT end with underline ( MyVal_ )
– May NOT contain sequential underlines
(My__Val)
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Lexical Elements of VHDL

Extended Identifiers
– Any character(s) enclosed by \
\
– Case IS significant
– Extended identifiers are distinct from basic
identifiers
– If “ \ ” is needed in extended identifier, use
“ \\ “
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Lexical Elements of VHDL

Reserved Words
– Do not use as identifiers

Special Symbols
– Single characters
& ‘ ( ) * + , - . / : ; < = > |
– Double characters (no intervening space)
=>
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:=
/=
>=
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<=
<>
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Lexical Elements of VHDL

Numbers
– Underlines are NOT significant
( 10#8_192 )
– Exponential notation allowed
( 46e5 , 98.6E+12 )
– Integer Literals ( 12 )
» Only positive numbers; negative numbers are
preceded by unary negation operator
» No radix point
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Lexical Elements of VHDL
– Real Literals ( 23.1 )
» Always include decimal point
» Radix point must be preceded and followed by at
least one digit.
– Radix ( radix # number expressed in radix)
» Any radix from binary ( 2 ) to hexadecimal ( 16 )
» Numbers in radices > 10 use letters a-f for 10-15.
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Lexical Elements of VHDL

String
– A sequence of any printable characters enclosed in
double quotes
( “a string” )
– Quote uses double quote
( “ he said ““no!”” ”)
– Strings longer than one line use the concatenation
operator ( & ) at beginning of continuation line.
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Lexical Elements of VHDL

Characters
– Any printable character including space
enclosed in single quotes ( ‘x‘ )

Bit Strings
– B for binary
( b”0100_1001” )
– O for Octal
( o”76443” )
– X for hexadecimal ( x”FFFE_F138” )
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VHDL Syntax

Extended Backus-Naur Form (EBNF)
– Language divided into syntactic categories
– Each category has a rule describing how to
build a rule of that category
– Syntactic category <= pattern
– “<=“ is read as “...is defined to be...”
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VHDL Syntax
– e.g.,
variable_assignment <= target :=
expression;
– A clause of the category variable_assignment is
defined to be a clause from the category target
followed by the symbol “ := “ followed by a
clause from the expression category followed
by a terminating “ ; ”
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VHDL Syntax
– syntax between outline brackets [ ] is optional
– syntax between outline braces { } can be
repeated none or more times, a.k.a. “Kleene
Star”
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VHDL Syntax
– A preceding lexical element can be repeated an
arbitrary number of times if ellipses are present,
e.g.,
case-statement <=
case expression is
case_statement_alternative
{ . . . }
end case ;
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VHDL Syntax
– If a delimiter is needed, it is included with the
ellipses as
identifier_list <=
identifier {
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,
. . .
}
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VHDL Syntax

“OR” operator, “ | ”, in a list of alternatives,
e.g.,
mode <= in | out | inout

When grouping is ambiguous, parenthesis
are used, e.g.,
term <=
factor { ( * | / | mod | rem ) factor }
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VHDL Syntax

e.g. an identifier may be defined in EBNF as
identifier <=
letter { [ underline ] letter_or_digit }
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VHDL Lecture 1

The end...
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