The Future in 8-Bit Microcontrollers
ENHANCED RISC
The AVR is...
 … the first new 8-bit MCU architecture to be launched in the





last 12 years
… a new design, not based on an architecture from the 70’s
… designed to be fast and code efficient instead of backwards
compatible
… designed to meet today’s and the future’s demand for
processing power and memory size
… taking advantage of today’s semiconductor technology
… designed in co-operation with C compiler experts to be C
code efficient
ENHANCED RISC
The AVR Offers...







… Industry’s Highest 8-bit Performance
… a Real 8-Bit RISC Architecture
… Low Power
… a broad Family of MCUs
… a Variety of Peripherals
… excellent C Language Code Density
… in-System Programmable Flash and
EEPROM
ENHANCED RISC
This is how it’s done







Four Memory Pointers
Linear (Non Paged) Memories
32 General Purpose Registers
Harvard Architecture
True single external clock cycle execution
A very rich and powerful instruction set
Powerful data addressing modes optimized
for the C language
 Utilization of Atmel’s 14 years of experience
in Non-Volatile Memories
ENHANCED RISC
Breaking Traditions
Code Size
Traditional
RISC
Traditional
CISC
AVR
Speed
ENHANCED RISC
AVR Block Diagram
ENHANCED RISC
AVR Register File
R0
R1
R2
R3
R26
R27
R28
R29
R30
R31
XL
XH
YL
YH
ZL
ZH
Register File
X Pointer
Y Pointer
Z Pointer
ENHANCED RISC
Direct Register - ALU Connection
Register operations
take ONE clock pulse
on the EXTERNAL clock
input
Register File
ALU
ENHANCED RISC
Execute 2 Instructions
1 2
PIC
1
HC05
1
‘C51
1
Done!
2
Done!
2
Done!
2
Done!
ENHANCED RISC
The Three AVR Families
 MEGA AVR
ATmegaxxx
( 16KB - 128KB)
 Targets complex applications with requirements for
large program memories
 Classic AVR
AT90Sxxxx
( 1KB- 8KB )
 Targets medium-range applications where high
throughput and low power are important
 Tiny AVR
ATtinyxx
( 1KB - 2KB )
 Targets cost-sensitive applications in the very low end
of the 8-bit MCU market
ENHANCED RISC
Available AVR Products
‘S1200
‘S2323
‘S2343
‘S2313
20
8
8
FLASH
1KB
2KB
SRAM
0
‘S4414
‘S4434
20
40/44
40/44
2KB
2KB
4KB
4KB
128B
128B
128B
256B
256B
64B
128B
128B
128B
256B
256B
UART
-
-
-
YES
YES
YES
PWMs
0
0
0
1
2
3
A/D Converter
-
-
-
-
-
[email protected]
RTC
-
-
-
-
-
YES
PINS
EEPROM
SAMPLES
NOW
NOW
NOW
NOW
NOW
NOW
PRODUCTION
NOW
NOW
NOW
NOW
NOW
NOW
ENHANCED RISC
Available AVR Products
‘S8515
‘VC8534 ‘S8535
PINS
40/44
48
40/44
FLASH
8KB
8KB
8KB
SRAM
512B
256B
512B
EEPROM
512B
512B
512B
UART
YES
NO
YES
PWMs
2
-
3
A/D Converter
-
RTC
-
[email protected] [email protected]
-
YES
SAMPLES
NOW
NOW
NOW
PRODUCTION
NOW
NOW
NOW
ENHANCED RISC
Available megaAVR Products
mega103 mega603 mega163 mega161 Mega 83
PINS
64
64
40/44
40/44
FLASH
128KB
64KB
16KB
16KB
16KB
SRAM
4KB
4KB
1KB
1KB
512B
EEPROM
4KB
2KB
1KB
512B
512B
UART
YES
YES
2
2
2
PWM
4
4
4
4
4
A/D Converter
[email protected] [email protected]
[email protected]
40/44
[email protected]
RTC
YES
YES
YES
YES
YES
SAMPLES
NOW
NOW
NOW
2Q00
2Q00
PRODUCTION
NOW
NOW
3Q00
3Q00
3Q00
ENHANCED RISC
AVR MCU’s Available cont.
90S2333
90S4433
28/32
28/32
FLASH
2KB
4KB
SRAM
128B
128B
EEPROM
128B
256B
UART
YES
YES
PWM
1
1
[email protected]
[email protected]
YES
YES
SAMPLES
NOW
NOW
PRODUCTION
NOW
NOW
PINS
A/D Converter
ISP
ENHANCED RISC
tinyAVR Roadmap
PINS
tiny10
tiny11
tiny12
8
8
8
tiny15L
8
tiny19
28
tiny22
tiny28
8
28
FLASH
1KB*
1KB
1KB
1KB
1KB
2KB
2KB
SRAM
0B
0B
0B
0B
0B
128B
0B
-
-
64B
64B
-
ISP
NO
NO
YES
YES
NO
I/O’s
6
6
6
6
A/D Converter
-
-
-
[email protected]
-
T/C
1
1
1
2, 1 PWM
1
1
1
SAMPLES
1Q00
NOW
1Q00
NOW
2Q00
NOW
NOW
PRODUCTION
2Q00
NOW
2Q00
2Q00
3Q00
NOW
3Q00
EEPROM
*QuickFlash Version of tiny11
128B
20
-
YES
NO
5
20
-
ENHANCED RISC
AVR Direction
 16KB MEGA AVR
 Application Specific Standard Products
(ASSPs)
– Battery Charger
– USB Device
– Remote Control Device
 The first TINY devices
– Pin Counts:
– Program Memories:
8 - 28
0.5 - 2K
ENHANCED RISC
A C-Code Example
The following example illustrates the AVR
benefits in terms of:
Code Size
Throughput
Power Consumption
ENHANCED RISC
A Small C Function
/* Return the maximum value of a table of 16 integers */
int max(int *array)
{
char a;
int maximum=-32768;
for (a=0;a<16;a++)
if (array[a]>maximum)
maximum=array[a];
return (maximum);
}
ENHANCED RISC
AVR Assembly output
; 7.
for (a=0;a<16;a++)
LDI
R18,LOW(0)
LDI
R19,128
CLR
R22
LDD
LDD
CP
CPC
BRGE
?0001:
; 8.
; 9.
CPI
R22,LOW(16)
BRCC
?0000
{
if (array[a]>maximum)
MOV
R30,R22
CLR
R31
LSL
R30
ROL
R31
ADD
R30,R16
ADC
R31,R17
MOV
MOV
R20,Z+0
R21,Z+1
R18,R20
R19,R21
?0005
maximum=array[a];
R18,R20
R19,R21
INC
RJMP
R22
?0001
; 10.
?0005:
?0000:
; 11.
; 12.
; 13.
}
return (maximum);
MOV
R16,R18
MOV
R17,R19
}
RET
Code Size: 46 Bytes, Execution time: 335 cycles
ENHANCED RISC
C51 Assembly Output
; FUNCTION _max (BEGIN)
;---- Variable 'array' assigned to Register 'R1/R2/R3' ---; SOURCE LINE # 4
; SOURCE LINE # 5
; SOURCE LINE # 7
MOV
maximum,#080H
MOV
maximum+01H,#00H
; SOURCE LINE # 9
;---- Variable 'a' assigned to Register 'R5' ---CLR
A
MOV
R5,A
?C0001:
; SOURCE LINE # 10
; SOURCE LINE # 11
MOV
A,R5
MOV
R7,A
RLC
A
SUBB
A,ACC
MOV
R6,A
MOV
A,R7
ADD
A,ACC
MOV
R7,A
MOV
A,R6
RLC
A
MOV
DPL,R7
MOV
DPH,A
LCALL
?C?ILDOPTR
MOV
R7,A
MOV
R6,B
SETB
C
SUBB
A,maximum+01H
MOV
A,maximum
XRL
A,#080H
MOV
R0,A
MOV
A,R6
XRL
A,#080H
SUBB
A,R0
JC
?C0003
; SOURCE LINE # 12
MOV
maximum,R6
MOV
maximum+01H,R7
; SOURCE LINE # 13
?C0003:
INC
R5
CJNE
R5,#010H,?C0001
?C0002:
; SOURCE LINE # 14
MOV
MOV
R6,maximum
R7,maximum+01H
; SOURCE LINE # 15
?C0005:
RET
; FUNCTION _max (END)
?C?ILDOPTR:
CJNE
R3,#0x01,0x195
MOV
A,0x82
ADD
A,R1
MOV
0x82,A
MOV
A,0x83
ADDC
A,R2
MOV
0x83,A
MOVX
A,@DPTR
MOV
OxF0,A
INC
DPTR
MOVX
A,@DPTR
RET
JNC
0x1A0
MOV
A,R1
ADD
A,0x82
MOV
R0,A
MOV
0xF0,@R0
INC
R0
MOV
A,@R0
RET
CJNE
R3,#0xFE,0xAD
MOV
A,R1
ADD
A,0X82
MOV
R0,A
MOV
A,@R0
MOV
0xF0,A
INC
R0
RET
MOV
A,0X83
ADD
A,R2
MOV
0X83,A
MOV
A,R1
MOVC
A,@A+DPTR
RET
Code Size: 112 Bytes, Execution time: 9384 cycles
ENHANCED RISC
HC11 Assembly output
; 7.
for (a=0;a<16;a++)
TSX
LDD
#-32768
STD
1,X
CLR
0,X
?0001:
; 8.
; 9.
STD
5,X
INS
INS
CPD
BLE
STD
3,X
?0005
maximum=array[a];
3,X
TSX
INC
BRA
0,X
?0001
; 10.
LDAA
0,X
CMPA
#16
BHS
?0000
{
if (array[a]>maximum)
PSHY
TAB
CLRA
LSLD
TSX
ADDD
0,X
XGDX
LDD
0,X
TSX
?0005:
?0000:
; 11.
; 12.
; 13.
}
return (maximum);
LDD
1,X
}
PULX
PULX
INS
PULY
RTS
Code Size: 57 Bytes, Execution time: 5244 cycles
ENHANCED RISC
PIC16C74 Assembly output
bcf
3,5
movwf
?a_maxnum& (0+127)
;MAX_MAIN.C: 4: char a;
;MAX_MAIN.C: 5: int maximum=-32768;
clrf
(?a_maxnum+2)& (0+127)
movlw
128
movwf
(?a_maxnum+3)& (0+127)
;MAX_MAIN.C: 7: for (a=0;a<16;a++)
clrf
(?a_maxnum+1)& (0+127)
l2
;MAX_MAIN.C: 8: {
;MAX_MAIN.C: 9: if (array[a]>maximum)
bcf
3,5
movf
(?a_maxnum+1)& (0+127),w
addwf
(?a_maxnum+1)& (0+127),w
addwf
?a_maxnum& (0+127),w
movwf
4
movf
0,w
movwf
btemp
incf
4
movf
0,w
movwf
btemp+1
movf
(?a_maxnum+3)& (0+127),w
xorlw
128
movwf
btemp+2
movf
btemp+1,w
xorlw
128
subwf
btemp+2,w
btfss
3,2
goto
u15
movf
btemp,w
subwf
(?a_maxnum+2)& (0+127),w
u15
btfsc
3,0
goto
l5
;MAX_MAIN.C: 10: maximum=array[a];
bcf
3,5
movf
(?a_maxnum+1)& (0+127),w
addwf
(?a_maxnum+1)& (0+127),w
addwf
?a_maxnum& (0+127),w
movwf
4
movf
0,w
movwf (?a_maxnum+2)& (0+127)
incf
4
movf
0,w
movwf
(?a_maxnum+3)& (0+127)
l5
;MAX_MAIN.C: 11: }
bcf
3,5
incf
(?a_maxnum+1)& (0+127)
movlw
16
subwf
(?a_maxnum+1)& (0+127),w
btfss
3,0
goto
l2
;MAX_MAIN.C: 12: return (maximum);
bcf
3,5
movf
(?a_maxnum+3)& (0+127),w
movwf
btemp+1
movf
(?a_maxnum+2)& (0+127),w
movwf
btemp
return
Code Size: 87 Bytes, Execution time: 2492 cycles
ENHANCED RISC
Performance Comparison:




AT90S8515
80C51
68HC11A8
PIC16C74
Code
Size
[Bytes]
@ 8 MHz
@ 24 MHz
@ 12 MHz
@ 20 MHz
Function Execution
Time [uS]
Current
Consumption
[mA]
46 (1)
42 (1)
11 (1)
434 (1)
112 (2.4)
391 (9)
16 (1.5)
32 (0.07)
68HC11
57 (1.2)
437 (10)
27 (2.5)
17 (0.04)
PIC16C74
87 (1.9)
125 (3)
13.5 (1.2)
119 (0.27)
AT90S8515
80C51
Normalized figures given in parentheses
Executions
/ S / mW
ENHANCED RISC
Some Conclusions on THIS
Case
 The C51 would have to run at 224 MHz to
match the 8 MHz AVR.
 The HC11 is quite code efficient, but
delivers only one 10th of the processing
power at 2.5 times the current consumption
 The PIC is a fast microcontroller, but the
AVR delivers more than 3.5 times higher
throughput per mW.
ENHANCED RISC
What made the AVR do
better?
 Excellent support for 16-bit arithmetics.
(Zero-Flag Propagation on Compare)
 A lot of registers which eliminate move to
and from SRAM
 Single Cycle execution
ENHANCED RISC
An Architecture Optimized for
High Level Language
ENHANCED RISC
High Level Languages
Increased importance for Microcontrollers
–
–
–
–
–
–
Time to market
Simplified maintenance
Portability
Learning time
Reusability
Libraries
Potential drawbacks
– Increased code size
– Decreased speed
ENHANCED RISC
AVR Architecture and
Instruction Set Influenced
by IAR
Architecture co-designed with IAR systems
through several iterations:
– Compiler development project initiated before architecture
and instruction set frozen
– Compiler expert’s advice implemented in hardware
– Potential HLL bottlenecks identified and removed
ENHANCED RISC
C-like Addressing Modes (1)
Auto Increment/Decrement:
C Source:
unsigned char *var1, *var2;
*var1++ = *--var2;
Generated code:
LD R16,-X
ST Z+,R16
ENHANCED RISC
C-Like Addressing Modes (2)
Indirect with Displacement:
Efficient for accessing arrays and structs
Autos placed on Software Stack
ENHANCED RISC
Four Memory Pointers
SRAM
X
Y
Z
SP
Code efficient memory to
memory copy
Pointer reloading is
minimized
Separate stacks for
return addresses and
local variables
ENHANCED RISC
16 and 32-Bit Support
Carry instructions
– Addition and Subtraction
– Register/register
– Register/immediate
Zero flag propagation
Enables fast and code efficient operations on
16 and 32-bit data types
ENHANCED RISC
Subtract Two 16-Bit
Values
Without Zero Flag Propagation
R1:R0 - R3:R2 ($E104 - $E101)
R1
R0
Z
E1
04
X
sub r0,r2
E1
03
0
sbc r1,r3
00
03
1
Wrong!
ENHANCED RISC
Subtract Two 16-Bit
Values
With Zero Flag Propagation
R1:R0 - R3:R2 ($E104 - $E101)
R1
R0
Z
E1
04
X
sub r0,r2
E1
03
0
sbc r1,r3
00
03
0
Correct!
ENHANCED RISC
Multi-Byte Compare
Example: 32-bit compare
CP
CPC
CPC
CPC
R16,R24
R17,R25
R18,R26
R19,R27
Compare with carry
instruction
Zero-flag
propagation
No restoring
necessary
All conditional
branches available
after compare
ENHANCED RISC
Switch Support
Switches are very frequently generated by
CASE tools
Conventional straight-forward approaches are
generally inefficient
Compact switch constructions take advantage
of the AVR’s indirect jumps
General library routines in the compiler
manages switches efficiently
ENHANCED RISC
Compiler Features
Fully compatible with the ANSI standard
All required data types supported
Fully re-entrant code
General optimizations
AVR specific optimizations
AVR specific extensions
ENHANCED RISC
Optimization
Code and Speed optimization
C and Assembly level optimizations
–
–
–
–
–
–
–
–
–
–
–
Algebraic identities
Common subexpression elimination
Removal of branch chains
Condition reversal
Constant folding
Register allocation
Bit operations
Peephole optimizations
Cross jumping and hoisting
Removal of unreachable code
Redundant assignment removal
ENHANCED RISC
Summary
AVR Architecture originally designed with
High Level Languages in mind
Architecture tuned for C in co-operation with
C-compiler experts
Resulting compiler generates highly efficient
code
ENHANCED RISC
AVR Peripherals
A closer look at some of the on-chip modules
ENHANCED RISC
I/O Ports General Features







Push-Pull Drivers
High Current Drive (sinks up to 20 mA)
Pinwise Controlled Pull-Up Resistors
Pinwise Controlled Data Direction
Fully Synchronized Inputs
Three Control/Status Bits per Bit/Pin
Real Read-Modify-Write
ENHANCED RISC
3 Control/Status Bits
per Pin
 DDRx
 PORTx
 PINx
X = A, B, C, ...
Data Direction Control Bit
Output Data or Pull-Up Control Bit
Pin Level Bit
ENHANCED RISC
I/O Pin Block Diagram
DDRx
0
Pull-Up
PORTx
0
PINx
Physical Pin
X
X
Direction:
Pull-Up:
INPUT
OFF (Tri-State)
ENHANCED RISC
Why Three Addresses?
Why not let WRITE PORTx write the LATCH
and
READ PORTx read the PINS?
(just like Microchip, Hitachi, Motorola...)
A Two-Address Port
Will Give You Trouble with
Read-Modify-Write
ENHANCED RISC
The problem with TwoAddresses
 Read-Modify-Write writes an unknown value
to the bits that are inputs.
 If two successive Read-Modify-Writes are
performed, the results from the first one
might get corrupted.
 When the latch controls the pull-up for input
lines, a read-Modify-Write will TURN OFF the
pull-ups for input lines that are low.
ENHANCED RISC
From the PIC16C64 Datasheet:
“Reading the PORT register, reads the values of the PORT pins.
Writing to the PORT register writes the value to the PORTB latch.
When using read modify write instructions (ex. BCF, BSF, etc.) on
a PORT, the value of the PORT pins is read, the desired operation is
done to this value, and the value is then written to the PORT latch”
.”
…
“…care must be exercised if a write followed by a read operation is
carried out on the same I/O port. The sequence of instructions should
be such to allow the pin voltage to stabilize (load dependent) before the
next instruction … otherwise, the previous state of that pin may be read
into the CPU rather than the new state … it is better to separate these
instructions with a NOP or another instruction not accessing this I/O port.”
ENHANCED RISC
From HITACHI’s H8/300
Programming Manual:
“BSET, BCLR, … are read-modify-write instructions. They read a
byte of data, modify one bit in the byte, then write the byte back.
Care is required when these instructions are applied to registers
with write-only bits and to the I/O port registers.”
…
“Programming Solution: The switching of the pull-ups can be
avoided by storing the same data both in the port data register
and in a work area in RAM”
ENHANCED RISC
UART Features






Full Duplex
8 or 9 Data Bits
Framing Error Detection
False Start Bit Detection
Noise Canceling
High BAUD Rates at low XTAL Frequencies
E.g. 115,200 BAUD at 1.8432 MHz
 Generates the BAUD rate you need
 Separate BAUD rate timer
 Three Interrupts with Separate Vectors
ENHANCED RISC
ADC Features
 Successive approximation w/ sample & hold
 Up to 8 single ended channels and up to 7
differential channels
 10-Bit resolution
 Configurable conversion time
 Accuracy:
– down to 65 ms conversion time: 10 bits ± 0.5 LSB
– down to 12 ms conversion time: 8 bits ± 0.5 LSB
 Free-run and single conversion modes
 Interrupt on conversion complete
 CPU Turn-Off Noise Reduction
ENHANCED RISC
Sleep Modes
 Idle Mode
 Power Down Mode
 Power Save Mode (Parts with RTC)
Feb 98
ENHANCED RISC
Idle Mode
 CPU is Stopped
 XTAL Oscillator Runs
 Timer/Counters and other Peripherals
Operate
 Reset + All Enabled Interrupts Can Wake Up
the MCU
ENHANCED RISC
Power Down Mode
 CPU is Stopped
 XTAL Oscillator is Stopped
 Timer/Counters and Other Peripherals are
Stopped
 The Watchdog can be Enabled.
 Reset + External Level Interrupt Can Wake
up the MCU
 Typical power consumption: 100 nA*
* WDT Not Enabled
ENHANCED RISC
Power Save Mode
 Applies to Devices with Asynchronous
32 kHz Timer (RTC)
 Similar to Power Down, but RTC is running
 RTC Interrupt Wakes the Device Up
 Typical Power Consumption: 5mA @ 5V
ENHANCED RISC
Wake-Up from Sleep Mode
 RESET:
The MCU Starts Execution
from the Reset Vector
 INTERRUPT:
The MCU Enters the
Interrupt Routine, Runs it
and Resumes Execution
from the Instruction
following “SLEEP”.
ENHANCED RISC
In-System Programmable
Flash and EEPROM
Now Offered on an MCU by a technology
leader in Non-Volatile memories
ENHANCED RISC
This is ISP Flash and
EEPROM
5-wire
serial programming
interface
Your device sits in the application. It is clocked from
the application clock, and Vcc can be as low as 2.7V.
Now, with four logical signals + Ground, you can
REPROGRAM THE FLASH AND THE EEPROM
NO +12V PROGRAMMING VOLTAGE REQUIRED!
ENHANCED RISC
Just Imagine...










No OTP parts thrown away
No 5-minute UV erase time
No sleepless nights after mask tape-out
No stocking of multiple system versions
No surprises in moving from OTP to mask
No 10-week lead time
… instead ...
Easy update of new features
Easy bug fix
Easy testing
Easy in-line calibration
ENHANCED RISC
A True Story
 Application:
– Remote Controlled Keyless Entry/Car Alarm
 MCU:
– Mask Programmed C51
 What happens:
– The law is changed overnight. All car alarms are
required to feature “hopping code” signaling
 Company solution:
– Scrap tens of thousands of mask parts.
– Produce with expensive OTPs while new masks are in
production
This company is now an AVR customer
ENHANCED RISC
New AVR Feature Planned In
2000
 Several new AVR devices will have an enhanced
feature set -- Self Programming Capability
– Self Programming gives the AVR MCU the ability to reprogram
itself -- without any external components
– In-System Programmability is achieved via multiple data ports,
such as UART and SPI ports
– In-System Programmability can be done over the full
temperature and voltage range specified for the device
ENHANCED RISC
Self Programming Features
 Enhanced FLASH Memory Architecture
– Dual memory areas
» Application Partition
» Boot Block Partition
• Boot Block is optional
– FLASH memory divided into 128 byte sectors
» Each sector independently addressable
ENHANCED RISC
Self Programming
 Write data to
buffer
 Z-pointer points
to the word
location in the
buffer
ENHANCED RISC
Self Programming
 Transfer the
buffer to the
Flash page
 Z-pointer points
to correct page
ENHANCED RISC
Self Programming Features
 Enhanced FLASH Memory Architecture
– Each memory partition has independent lock bit protection
» Protect entire FLASH memory
» Protect Boot Block while updating Application partition
» Protect Application partition while updating Boot Block
» Allow software update in entire FLASH address space
where Boot Block is not used
ENHANCED RISC
Self Programming Features
 Executing instructions out of the Boot Block
you can:
– Read code or data from Application partition
– Modify code or data within Application partition
– Modify code within Boot block itself
 ISP method is flexible and interchangeable via:
– UART
– SPI Port
– I2C Port
ENHANCED RISC
Benefits of Self Programming
 ISP of the MCU is completely autonomous
– No external device(s) required to reprogram the AVR
microcontroller in-system
– Application code can be updated or modified based on
external conditions
 Sectored FLASH provides unmatched
flexibility
– Small sections of application code can be changed instead
of having to do a full update
– Unused sectors provide additional data storage memory -perfect for calibration data
ENHANCED RISC
Self Programming AVR Devices
For 1999
 8KB Version
– 8KB FLASH, 512B EEPROM, 512B SRAM, 7 Channel 10-Bit
ADC with 5 Differential inputs - one with programmable gain
stage, UART, SPI and I2C ports. 40-pin PDIP, 44-pin TQFP.
– Initial Target Applications: Smart Battery chargers
 16KB Version
– 16KB FLASH, 512B EEPROM, 1024B SRAM, Dual UART’s, SPI
Port, Multiplication Instruction. 40-pin PDIP, 44-pin TQFP.
» Initial Target Applications: ADSL modem; 90S8515 upgrade
path
ENHANCED RISC
Self Prog. AVR Roadmap
8KB
16KB
PINS
40/44
40/44
FLASH
8KB
16KB
BOOT BLOCK
1024B
1024B
SRAM + REG’s
512+32
1024+32
512
512
EEPROM
UART
ISP METHODS
SINGLE
DUAL
UART, I2C
SPI
UART, SPI
A/D CONVERTER
YES
NO
VOLTAGE
2.7V - 5.5V
2.7V - 5.5V
SAMPLES
3Q00
2Q00
PRODUCTION
4Q00
3Q00
ENHANCED RISC
Target Applications
 What are some of the target applications that need
the self programming feature?
– Applications that are real estate and/or cost constrained and
cannot afford another MCU for programming
» Smart Battery charger for PC laptops
» “Learning” Universal Remote controller
– Applications that are difficult to access are also ideal
candidates
ENHANCED RISC
Development Tools
ENHANCED RISC
Available Development
Tools







Assemblers
C-Compiler / Linker
Simulator / Debuggers
Development Kits
Programmers
In-Circuit Emulator
Application notes / FAQ
ENHANCED RISC
AVR StudioTM Features









Acts as Simulator when no ICE Connected
Acts as ICE Front-End when ICE Connected
C or Assembly Level Debugging
C Variable Watch
Memory & Register View
Simulates Peripherals (including I/O Pins)
32-bit Windows Application
Supports All AVR Devices
Freeware
ENHANCED RISC
STK200 - a Flash MCU
Starter Kit
 Programs all Classic, Analog and TINY AVR
in 8, 20, 28 and 40 pin package
 External SRAM, RS232 and LCD interface
 Includes Switches, LEDs and adjustable
voltage reference
 Dual Voltage operation 3.3V, 5V
 Brown-Out protection
ENHANCED RISC
STK300 - a Flash MCU
Starter Kit




Supports ATmega103/603
Includes ATMEGA103 module
External SRAM, RS232 and LCD interface
Includes Switches, LEDs and adjustable
voltage reference
 Dual Voltage operation 3.3V, 5V
 Brown-Out protection
ENHANCED RISC
In-Circuit Emulators
 ICE200 - Emulates classic AVR devices
 ICEPRO - Emulates classic and tiny AVR
devices
 MEGAICE - Emulates megaAVR devices
 ASICICE - Emulates AVR core for ASIC
development
ENHANCED RISC
ICE Features









Emulates all Peripherals, Analog and Digital
Interfaces to the AVR Studio
32K x 96 Bit Trace Buffer
Unlimited number of Breakpoints
Logic Analyzer Interface
5 Trigger Outputs
5 Trace Inputs
External Clocking Options
Supports VCC voltages 2.7 - 6V
ENHANCED RISC
ATMEL WEBSITE:
www.atmel.com
 Datasheets
 Application Notes
 FAQ
ATMEL KOREA FAE :
swlee.atmelkor.co.kr
ENHANCED RISC
IAR Systems C Development
Tools
IAR SYSTEMS WEBSITE: www.iar.com
ENHANCED RISC
EWA90 - Embedded
Workbench from IAR
 Total Integration of IAR C development tools
–
–
–
–
–
Editor
Compiler
Assembler
Linker
Debugger
 Hierarchical Project Presentation
 Runs under Windows95, NT and 3.11
ENHANCED RISC
ICCA90 - AVR C Compiler
from IAR





Fully ANSI compatible
Device Specific Extensions
Built-In AVR Specific Optimizer
Generates Re-entrant Code
Supports all Classic AVR Devices with
SRAM + MEGA AVR
ENHANCED RISC
Other Third Party Tools
Suppliers
 Starter Kits
– Equinox Technologies (www.equinox-tech.com)
– Kanda Systems (www.kanda-systems.com)
 Basic Compiler for the AT90S1200
– Silicon Studios (www.sistudio.com)
 Pascal Compiler for All AVR SRAM Devices
– ELAB Computers [email protected]
ENHANCED RISC
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