Embedded Systems
University of Belgrade
School of Electrical Engineering
Department of Computer Science
Authors:
Gvozden Marinkovic [email protected]
Nikola Milanovic [email protected]
Goran Timotic [email protected]
Ivan Sokic [email protected]
Prof. Dr. Veljko Milutinovic [email protected]
Introduction







Design
Components
Microcontrollers
Communication
Examples
ARMs
PIC MCUs
2/175
Design






Specification
Circuit Design
Printed Circuit Board Layout
Firmware
Pilot Run
Production
Source
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Electronic Design Flowchart
Progra m
Spe cific atio n
Spe cific atio n
Circu it Des ig n
PCB La you t
Prototy pe s
Progra m
Des ign
W riting Cod e
Progra m T es t
Pilot Run
Source
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Produ ctio n
4/175
Specification

Starts as collection of ideas that describe a device or product

Specifications go through two phases
– first phase they describe the product as desired:
must-have, bells and whistles features
– second phase they describe the product as required:
describes the product as it is required to be produced
Source
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Specifying New Design

Give your project a name
– Keep project name short, it saves time

Describe your project (Opening Statement)
– Keep the first description short
– First sentence should summarize the whole function of the project
– Describe or name equipment, devices or interfaces

Describe your projects market

Describe the market need your product fulfills

Estimate the production volume
Source
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Specification:Technical Ingredients

A Specification reads like a list of project features,
describing the unit, and will usually include:
Inputs
Power Supply
Controls
Communications
Outputs
Protection
Indicators
Fail safes and
replaceable parts
Functions Modes of operation
Connector types
Physical format and size
Source
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Part 1
Circuit Design

Maps out the electronics and connections
in the most readily readable form

The designer needs to do background work:
– research specifications of components
– research interaction between components
(especially timing and loading)
– research physical packages
– research arrangement of connector pinouts

The finished circuit diagram is the main document for the design
Source
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Part 2
Circuit Design

Circuit diagram is a strict document

A circuit diagram must reflect the actual construction
of the printed circuit board which is made from it

Printed circuit board CAD and Schematic CAD
are tied together through a Net-check

The circuit diagram references each part on the PCB
with a designator and pin numbers for each connection
Source
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Printed Circuit Board Layout

Connections on the PCB
should be identical to
the circuit diagram
– Circuit diagram is arranged
to be readable
– PCB layout is arranged
to be functional

PCB layout can be performed:
– manually (using CAD)
– in combination with
an Autorouter
Source
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Part 1
Methods of PCB construction

Conventional
– Rigid PCB of thickness 1.6mm
– Wire-leaded components
mounted on only one side
of the PCB
– All the leads through holes,
soldered and clipped.
– Easier to debug and repair than
Surface mount
Source
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Part 2
Methods of PCB construction

Surface Mount Technology (SMT)
devices (SMD)
– PCB with tag-leaded components
soldered flush to PCB pads
– Holes are still needed on the PCB,
not where the component leads are
attached
– Generally smaller than conventional
– Generally more suited to
automated assembly than
conventional
Source
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Part 3
Methods of PCB construction

Surface mount and conventional
mix
– Most boards are a mix of
surface mount and
conventional components
– Disadvantages because
the two technologies require
different methods of
insertion and soldering
Source
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Part 4
Methods of PCB construction

Double sided Laminate
– Tracks on both sides, normally with PTH holes
connecting circuitry on the two sides together

Double sided component Assembly
– Mounting components on both sides of the PCB
– Normally only surface mount circuitry
would be mounted on both sides of a PCB
Source
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Part 5
Methods of PCB construction

Multi-layer
– PCB Laminate manufactured
with more than two layers of copper tracks,
by using a sandwich construction
– Cost of the laminate reflects the number of layers
– Used to
• route complicated circuitry
• distribute the power supply
more effectively
Source
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Part 6
Methods of PCB construction

Gold plated
– Certain areas on a PCB may be gold
plated for use as contact pads

Flexible PCB
– Technique used extensively with
• membrane keyboards
• combination connector/circuit
boards
• circuit boards to fit in awkward
shapes
Source
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Part 7
Methods of PCB construction

Chip On Board (COB)
– IC is attached direct to a PCB
– Bond out wires from the IC
connect directly to PCB lands
– Chip is covered with a black blob
of epoxy
– Used mostly with very high
volume, cost sensitive
applications
Source
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Part 8
Methods of PCB construction

Phenolic PCB
– Phenolic is a cheaper PCB laminate material

Daughterboard
– Circuit board mounted to another circuit board
Source
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Part 1
Printed Circuit Board Etching

CAD File processing
– PCB CAD files are sent to
the PCB Manufacturer
– PCB manufacturer inspects
the files, making a drill list
and adding identification
– CAD files are processed and
sent to a photoplotter
to turn into film artwork
Source
AirBorn Electronics
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Part 2
Printed Circuit Board Etching

Laminate drilling and electroplating
– Laminates are drilled with holes
– Drilled laminates are coated
in a chemical to enhance
electroplating of holes
– Laminates are put in
a copper plating bath,
all the holes are electroplated
– This connects pads on opposite
sides of the PCB, electrically
Source
AirBorn Electronics
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Part 3
Printed Circuit Board Etching

Laminate etching
– The laminates are coated with a UV-sensitive photo-resist
– The track pattern is imaged onto each side of each PCB,
using the photoplots and UV light
– The photo-resist is developed,
leaving photo-resist only where copper is required
– The laminates are put in acid,
to etch away unrequired copper, forming the track pattern
– The bare copper PCB, with tracks and pads now finished,
is cleaned
Source
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Part 4
Printed Circuit Board Etching

Laminate solder masking and
tinning
– The bare copper PCB is
silkscreened with a solder mask
(usually green)
– The solder mask is dried or cured
– The PCB is tinned - solder is
applied to exposed pads
– The PCB is levelled - bumps in
the solder is made flat by using
hot air or hot oil
Source
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Part 5
Printed Circuit Board Etching

Final stages
– The PCB is silkscreened with
component identification
lettering (usually white)
– The silkscreen legend
is dried or cured
– Any final drilling is done of holes
that are not to be plated through,
any routing is done, and the
laminate is cut into individual
printed circuit boards
Source
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PCB Assembly

Assemblies should be
– maintainable
– repairable
– durable; and
– easy to install
Source
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Part 1
PCB Documentation

Front Cover
– Title, date, version number, customer details, project features

Schematic

ECO Sheet
– Details of any circuit modifications

Bill of material
– The parts list

Parts key
– A glossary of the part number abbreviations, with package sizes,
lead spacing, tolerance notes and preferred types
Source
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Part 2
PCB Documentation

Front panel artwork

Manufacturing notes
– Contains the notes relating to previous production runs
- for instance problems encountered, methods of testing

Drilling diagram
– Showing the positioning and size of every hole on the PCB

Actual size PCB overlay
– Showing the positioning and identification of the PCB components
– The plan is printed actual size to allow components
to be placed against it to check for fit
Source
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Firmware

The major steps in Firmware design are:
– Program Specification
– Program Design
– Writing code
– Program Test
Source
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Program Specification

The specification for the Electronic Product being designed
will usually also be the specification for the programming required

The program specification will required the writer to go into
substantial detail about how the product actually operates,
and how it is used

A thorough program specification leads straight in to
Flow charts and timing diagrams,
which are components of Program Design
Source
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Program Design

The program design stage lays out the structure and
algorithms of the firmware

The structure and algorithms may be laid out as:
– flowchart
– timing diagram
– description of a protocol
– memory map; or
– equation
Source
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Writing Code

If the program is well specified and
the algorithm design stage has been thorough,
the actual code writing stage can become almost mechanical

By defining the software at the outset, before code is written,
a much more defined, integrated, set of code can be produced

The extra space occupied by comments costs nothing,
and if the comments are well laid out
there is no possibility that they can detract
from understanding the code
Source
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Program Test

Divide the testing of the design into small, autonomous units
– It is easier to detect faults
before they are compounded by other factors

Program testing requires getting diagnostic data out of the target,
for analysis
– By emulation tools,
or through the hardware itself (for instance a serial port)
Source
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Pilot Run

To test the product further,
a Pilot run normally follows the prototyping stage

Small quantity of units are field trialed in a beta test

Opportunity to assess the manufacturability of the design,
and the usability of the documentation
Source
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Production

Following the pilot run there will likely be changes
to the firmware, and possibly the circuit design,
as the unit develops into a stable, final product

This process is controlled by ECO’s and version numbers

The cost, style of design of the final production,
is heavily influenced by the number of units manufactured
Source
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Components


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
Capacitors
Resistors
Transistors
Diodes
Oscillators and Crystals
AD Converters
DA Converters
LCD (Liquid Crystal Display)
Operational Amplifier
Sensors and Transducers
34/175
Oscillators and Crystals

Feedback Oscillators
– Loop Gain
– How Feedback Oscillators Work?

Quartz Crystal
–
–
–
–
–
Crystal Parameters
Equivalent Circuit
Load Capacitance
“Series” vs. “Parallel” Crystals
Frequency Tolerance
35/175
AD Converters

Converts analog input to a digital
value and outputs it as serial or
parallel data

Basic attributes
– number of channels for analog
input
– approximation type
– resolution (number of bits)
– conversion speed
– serial or parallel output
– operating temperature range
– errors (linearity, differential
linearity, total)
36/175
DA Converters

Converts digital input to an analog value and outputs it as a DC
voltage

Basic attributes
–
–
–
–
conversion method
output settling time
analog output sink/source current
operating temperature range
37/175
LCD (Liquid Crystal Display)





Used in low power devices (voltage 2-3V)
Layer of liquid crystal (10-12m thick) is
formed between two glass plates
When applied, electrical field polarizes
molecules of liquid crystal and the chosen
segment becomes visible
Beside low power devices, LCD is
becoming a standard option for desktop
monitors - flat panel TFT LCD (clearer
picture with higher resolution)
Problem: viewing angle
38/175
Operational Amplifier

Realization with differential amplifier (IC or discrete logic)
 Circuits with negative or positive feedback (amplifiers and
oscillators)
 Basic parameters:
–
–
–
–
–
gain
input and output resistance
bandwidth (frequency characteristics)
voltage and current drift
max. output current
39/175
Sensors and Transducers

Classification:
– physical property (piezoelectric, photovoltaic, etc.)
– function (measurement of length, temperature, etc)

Radiant, gravitational, mechanical, thermal, electrical, magnetic,
molecular, atomic, nuclear

The signal is fed into an input transducer, which changes the form
of energy, usually into electrical.

A modifier, usually an amplifier, and an output transducer then
convert the energy into a form to be displayed or recorded.
40/175
Sensors and Transducers

The following is a diagram representative of this system:
radiant
mechanical
thermal
electrical

input transducer
modifier
output transducer
Three basic types of transducers are:
– self generating
– modulating
– modifying
41/175
Microcontrollers

Specially designed microprocessors
– It is small on chip computer

Highly integrated chip
includes all or most parts needed for controller
 A typical microcontroller has:
– bit manipulation
– easy and direct access to I/O
– quick and efficient interrupt processing

Microcontroller drastically reduces design cost
42/175
Worldwide Microcontroller shipments
- in millions of dollars '9 5
'9 6
'9 7
'9 8
'9 9
00
4 -b it
1826
1849
1881
1856
1816
1757
8 -b it
5634
6553
7529
8423
9219
9715
1 6 -b it
1170
1628
2191
2969
3678
4405
Source
WSTS & ICE
43/175
Worldwide Microcontroller shipments
- in millions '9 5
'9 6
'9 7
'9 8
'9 9
00
4 -b it
1100
1100
1096
1064
1025
970
8 -b it
1803
2123
2374
2556
2681
2700
157
227
313
419
501
585
1 6 -b it
Source
WSTS & ICE
44/175
Applications

Appliances
(microwave oven, refrigerators, television and VCRs, stereos)

Computers and computer equipment
(laser printers, modems, disk drives)

Automobiles
(engine control, diagnostics, climate control),

Environmental control
(greenhouse, factory, home)

Instrumentation

Aerospace

Robotics, etc...
45/175
Flavors

4, 8, 16, or 32 bit microcontrollers

specialized processors include features specific for
– communications,
– keyboard handling,
– signal processing,
– video processing, and other tasks.
46/175
Part 1
Popular Microcontrollers

8048 (Intel)

8051 (Intel and others)

80c196 (MCS-96)

80186,80188 (Intel)

80386 EX (Intel)

65C02/W65C816S/W65C134S (Western Design Center)

MC14500 (Motorola)
47/175
Part 2
Popular Microcontrollers

68HC05 (Motorola)

68HC11 (Motorola and Toshiba)

683xx (Motorola)

PIC (MicroChip)

COP400 Family (National Semiconductor)

COP800 Family (National Semiconductor)

HPC Family (National Semiconductor)

Project Piranha (National Semiconductor)
48/175
Part 3
Popular Microcontrollers

Z8 (Zilog)

HD64180 (Hitachi)

TMS370 (Texas Instruments)

1802 (RCA)

MuP21 (Forth chip)

F21 (Next generation Forth chip)
49/175
Part 1
Programming Languages

Machine/Assembly language

Interpreters

Compilers

Fuzzy Logic and Neural Networks
50/175
Part 1
Development Tools

Simulators

Resident Debuggers

Emulators

Java on Embedded Systems
51/175
Choosing microcontoller

Technical support
 Development tools
 Documentation
 Purchasing more devices at one manufacturer
(A/D, memory, etc.)

Additional features
(EEPROM, FLASH, LCD driver, etc.)
52/175
Microcontrollers

Basic parts are:
– Central Processing Unit
– RAM
– EPROM/PROM/ROM or
FLASH Memory
– I/O serial or/and parallel
– timers
– interrupt controller

Optional parts are:
–
–
–
–
Watch Dog Timer
AD Converter
LCD driver
etc.
external
inerrupts
interrupt
control
ROM
RAM
timer 1
timer 0
CPU
OSC
bus
control
4 I/O
ports
serial
port
TxD RxD
P0 P2 P1 P3
address/
data
53/175
counter
inputs
Intel 8051

A typical 8051 contains:
RAR
– CPU with Boolean processor
4Kx8
ROM
RAM
BUFFER
SENSE
AMPS
PCH
DPH
P2 LATCH
PCL
DPL
PORT2
P0 LATCH
INTERNAL BUS
– 5 or 6 interrupts:
2 external, 2 priority levels
128x8
RAM
P2 LATCH
PORT2
ALU
ROM
A
– 2 or 3 16-bit timer/counters
– programmable full-duplex
serial port
– 32 I/O lines (four 8-bit ports)
– RAM
– ROM/EPROM in some models
IR
PLA
TMP2
TMP1
B
CONTROL
PSW
SP
ALU
P0 LATCH
SCON
TCON
IE
P3 LATCH
PORT0
SBUF(REC)
TMOD
IP
PORT3
SBUF(XMIT)
TL0
INTERRUPT
CONTROL
SERIAL
PORT
TH0
TL1
TH1
TIMER
CONTROL
54/175
Part 1
Intel 8051: Pin Description
VCC

VSS - Ground: 0V
 VCC - Power Supply
 P0.0-P0.7 - Port 0
PORT 0
XTAL1
ADDRESS AND
DATA BUS
XTAL2
PSEN
ALE/PROG
PORT 1
RST
EA/Vpp
RxD
INT1
T0
PORT 2
TxD
INT0
PORT 3
SECONDARY FUNCTIONS
– Open drain,
bi-directional I/O port
– Pins that have 1s written to
them float and can be used
as high-impedance inputs
– Multiplexed low-order
address and data bus during
accesses to external program
and data memory
VSS
ADDRESS BUS
T1
WR
RD
55/175
Part 2
Intel 8051: Pin Description

P2.0-P2.7 - Port 2
– Bi-directional I/O port
with internal pull-ups
– Pins that have 1s written to
them float and can be used
as high-impedance inputs.
– Port 2 emits high-order
address byte during
accesses to external program
and data memory

P3.0-P3.7 - Port 3
– Bi-directional I/O port
with internal pull-ups
– Pins that have 1s written to
them float and can be used
as high-impedance inputs.

Port 3 serves the
special features:
–
–
–
–
–
–
–
RxD - Serial input port
TxD - Serial output port
INT0 - External interrupt
INT1 - External interrupt
T0 - Timer 0 external input
T1 - Timer 1 external input
WR - External data memory
write strobe
– RD - External data memory
read strobe
56/175
Part 3
Intel 8051: Pin Description

RST - Reset

– A high on this pin
for two machine cycles
resets the devices


– EA must be externally held
low to enable device to fetch
code from external memory
locations.
ALE - Address Latch Enable
– Output pulse for latching
the low byte of address
during an access to external
memory

XTAL1 - Crystal 1
– Input to the inverting
oscillator amplifier and
input to internal clock
generator circuits
PSEN - Program Store Enable
– Read strobe to external
program memory
EA - External Access Enable

XTAL2 - Crystal 2
– Output from the inverting
oscillator amplifier
57/175
Part 1
Intel 8051: Pin Configurations

Dual In-Line Package
 Plastic Lead Chip Carrier
 Plastic Quad Flat Pack
P1.0
1
40
Vcc
P1.1
2
39
P0.0/AD0
P1.2
3
38
P0.1/AD1
P1.3
4
37
P0.2/AD2
P1.4
5
36
P0.3/AD3
P1.5
6
35
P0.4/AD4
P1.6
7
34
P0.5/AD5
P1.7
8
33
P0.6/AD6
RST
9
32
P0.6/AD6
RxD/P3.0
TxD/
P3.1
INT0/P3.2
10
31
EA
11
30
ALE
12
29
PSEN
INT1/P3.3
13
28
P2.7/A15
T0/P3.4
14
27
P2.6/A14
T1/P3.5
15
26
P2.5/A13
WR/P3.6
16
25
P2.4/A12
RD/P3.7
17
24
P2.3/A11
XTAL2
18
23
P2.2/A10
XTAL1
19
22
P2.1/A9
Vss
20
21
P2.0/A8
58/175
Part 2
Intel 8051: Pin Configurations
–6
–1
–7
–40
44
–39
34
33
1
PQFP
–17
–18
–1 NIC
–2 P1.0
–3 P1.1
–4 P1.2
–5 P1.3
–6 P1.4
–7 P1.5
–8 P1.6
–9 P1.7
–10 RST
–11 P3.0/RxD
–12 NIC
–13 P3.1/TxD
–14 P3.2/INT0
–15 P3.3/INT1
PLCC
–29
–16 P3.4/T0
–17 P3.5/T1
–18 P3.6/WR
–19 P3.4/RD
–20 XTAL2
–21 XTAL1
–22 VSS
–23 NIC
–24 P2.0/A8
–25 P2.1/A9
–26 P2.2/A10
–27 P2.3/A11
–28 P2.4/A12
–29 P2.5/A13
–30 P2.6/A14
–28
–31 P2.7/A15
–32 PSEN
–33 ALE
–34 NIC
–35 EA
–36 P0.7/AD7
–37 P0.6/AD6
–38 P0.5/AD5
–39 P0.4/AD4
–40 P0.3/AD3
–41 P0.2/AD2
–42 P0.1/AD1
–43 P0.0/AD0
–44 VCC
11
23
12
1 P 1 .5
2 P 1 .6
3 P 1 .7
4 RST
5 P 3 .0 /R xD
6 N IC
7 P 3 .1 /T x D
8 P 3 .2 /IN T 0
9 P 3 .3 /IN T 1
1 0 P 3.4 /T 0
1 1 P 3.5 /T 1
1 2 P 3.6 /W R
1 3 P 3.4 /R D
14 X TAL 2
15 X TAL 1
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
VSS
N IC
P 2.0 /A 8
P 2.1 /A 9
P 2.2 /A 1 0
P 2.3 /A 1 1
P 2.4 /A 1 2
P 2.5 /A 1 3
P 2.6 /A 1 4
P 2.7 /A 1 5
PSEN
ALE
N IC
EA
P 0.7 /A D 7
22
31
32
33
34
35
36
37
38
39
40
41
42
43
44
P 0.6 /A D 6
P 0.5 /A D 5
P 0.4 /A D 4
P 0.3 /A D 3
P 0.2 /A D 2
P 0.1 /A D 1
P 0.0 /A D 0
VCC
N IC
P 1.0
P 1.1
P 1.2
P 1.3
P 1.4
59/175
Part 1
Intel 8051: CPU

Primary elements are:
RAR
– eight bit ALU
with associated registers
A, B, PSW and SP
– sixteen-bit
Program Counter (PC)
– Data Pointer registers
128x8
RAM
4Kx8
ROM
RAM
BUFFER
SENSE
AMPS
PCH
DPH
P2 LATCH
PCL
DPL
PORT2
P0 LATCH
INTERNAL BUS
P2 LATCH
PORT2
ALU
ROM
A
IR
PLA
TMP2
TMP1
B
CONTROL
PSW
SP
ALU
P0 LATCH
SCON
TCON
IE
P3 LATCH
PORT0
SBUF(REC)
SBUF(XMIT)
TMOD
IP
PORT3
TL0
INTERRUPT
CONTROL
SERIAL
PORT
TH0
TL1
TH1
TIMER
CONTROL
60/175
Part 2
Intel 8051: CPU

The ALU can manipulate one-bit as well as eight-bit data types
– This features makes the 8051 especially well suited
for controller-type applications

A total of 51 separated operations
move and manipulate three data types:
– Boolean (1-bit)
– Byte (8-bit)
– Address (16-bit)
61/175
Part 3
Intel 8051: CPU

Instruction types:
–
–
–
–
–
Arithmetic Operations
Logic Operations for Byte Variables
Data Transfer Instructions
Boolean Variable Manipulation
Program Branching and Machine Control
62/175
Part 4
Intel 8051: CPU

There are eleven addressing modes:
– seven for data
– four for program sequence control

Most operations allow several addressing modes,
bringing total number of instructions to 111,
encompassing 255 of the 256 possible 8-bit instruction opcodes
 8051 instruction set fares well at both
real-time control and data intensive algorithms
63/175
Part 1
Intel 8051: Memory Organization

Program memory is separate distinct from data memory
– Each memory type has a different addressing mechanism,
different control signals, and a different functions

Architecture supports several distinct “physical” address spaces
functionally separated at the hardware level:
–
–
–
–
–
On - chip program memory
On - chip data memory
Off - chip program memory
Off - chip data memory
On chip special function registers
64/175
Part 2
Intel 8051: Memory Organization

Program (Code) memory
– Holds the actual 8051 program that is to be run
– Limited to 64K
– may be found on-chip as ROM or EPROM
– may be stored completely off-chip in
an external ROM or an external EPROM
– Flash RAM is also another popular method of storing a program
– Various combinations of these memory types may be used
(e.g. 4 K on-chip and 64 KB off-chip)
65/175
Part 3
Intel 8051: Memory Organization

External RAM
– External RAM is any random access memory which is found off-chip
– External RAM is slower
• To increment an Internal RAM location by 1
requires only 1 instruction and 1 instruction cycle
• To increment a 1-byte value stored in External RAM
requires 4 instructions and 7 instruction cycles
– While Internal RAM is limited to 128 bytes (256 bytes with an 8052),
the 8051 supports External RAM up to 64K
66/175
Part 4
Intel 8051: Memory Organization

On-chip memory
– Two types:
• Internal RAM; and
• Special Function Register (SFR) memory
– Internal RAM is on-chip so it is the fastest RAM available
– Internal RAM is volatile, when the 8051 is reset this memory is cleared
– Special Function Registers (SFRs) are areas of memory that
control specific functionality of the 8051 processor
67/175
Part 1
PORT 2 : High byte of address
held for the duration of
read or write cycle
 PORT 0 : time multiplexed
low byte of address with data byte
 Signal ALE: used to capture the
address byte into an external latch
EA
PORT2
PORT0
A8-A15
AD0-AD7
A0-A7
LATCH
ALE
"0"
LE
A8-A15
A8-A15
A0-A7
A0-A7
CS
RD
WR
Static RAM

"0"
8051
D0-D7
PSEN
RD
WR
64 Kbytes - Program memory (external)
64 Kbytes - Data Memory
68/175
CS
OE
ROM
Intel 8051: Memory Access
Part 2
Intel 8051: Memory Access
STAGE 1
STAGE 2
STAGE 3
STAGE 4
STAGE 5
STAGE 6
STAGE 4
STAGE 5
STAGE 6
STAGE 1
STAGE 2
STAGE 3
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P2
P2
P2
P2
P2
P2
XTAL1
XTAL1
ALE
ALE
PSEN
RD
P0
P2
INS.
IN
INS.
IN
A0-A7
A8-A15
INS.
IN P0
A0-A7
A8-A15
P2
P2
P2
P2
P2
FLOAT
A0-A7
P2
data
in
A8-A15
P2
FLOAT
A8-A15
69/175
Part 1
Intel 8051: Program Memory
PROGRAM MEMORY
Up to 64K of Program Memory
 PSEN: read strobe
for all external program fetches
 PSEN: not activated for
internal program fetches
 Depending on EA pin
lowest bytes can be either
in the on-chip ROM or in an external ROM
0xFFFF
EXTERNAL

EA = 0
EA = 1
0x0000
PSEN
70/175
Part 2
Intel 8051: Program Memory

Boot address - 0x0000
 Each interrupt is assigned
a fixed location in Program Memory
 If interrupt is not going to used,
its service location is available as
general purpose Program Memory
LOWER PART OF PROGRAM MEMORY
0x0028
0x0023
INTERRPUT
LOCATIONS
0x0018
0x0013
8 BYTES
0x0008
0x0003
RESET
0x0000
71/175
Part 3
Intel 8051: Program Memory

Port 0 and Port 2 are dedicated
to bus functions during
external Program Memory fetches
PORT0
INSTR
EA
AD0-AD7
A0-A7
LATCH
ALE
PORT2
PSEN
ADDR
LE
A8-A15
OE
8051
EROM
72/175
Part 1
Intel 8051: Data Memory
DATA MEMORY

Up to 64K Data Memory
 Access to Data memory use
RD or WR to strobe the memory
EXTERNAL
0xFFFF
INTERNAL
0xFF
0x00
0x0000
RD WR
73/175
Part 2
Intel 8051: Data Memory

Internal Memory Addresses
are one byte wide 128 bytes address space
(256 - Intel 8052)
 Direct addressing higher then 0x7F
access one memory space,
indirect addressing higher then 0x7F
access a different memory space
 Upper 128 and SFR space
occupying same block of addresses,
although they are
physically separate entities
INTERNAL
0xFF
UPP ER
128
ACCES SIBLE
BY INDIRECT
ADDRES SING
O NLY
ACCES SIBLE
BY DIRE CT
ADDRES SING
O NLY
0x7F
LOW ER
128
ACCES SIBLE
BY DIRE CT
AND INDIRECT
ADDRES SING
SP ECIAL
FUNCTION
REG ISTE RS
PO RTS
STATUS BITS
CO NTO L BITS
TIM ER RE GISTERS
STACK P OINTER
ACCUMULATOR
(E TC.)
0x00
74/175
Part 3
Intel 8051: Data Memory

The lowest 32 bytes are grouped
into 4 banks of 8 registers
 Program instructions call out
these registers R0 through R7
 Two bits in the PSW
selects register bank
– Register instructions are shorter
LOW ER 128 BYTES OF
IN TE R N A L R A M
0x 7F
0x 2F
B A N K S E L E C T B ITS
IN P S W
B IT A D D R E S S A B LE S P A C E
(B IT A D D R E S S E S 0 -7 F )
0x 20

The next 16 bytes form a
block of bit-addressable space
0x 1F
11
0x 18
0x 17
10
0x 10
4 BANKS OF
8 R E G IS T E R S
R 0 -R 7
0x 0F
01
0x 08
0x 07
00
RESET VALUE OF
S T A C K P O IN T E R
0x 00
75/175
Part 1
Intel 8051: SFR

SFRs are accessed as if they were normal Internal RAM

SFR registers exist in the address range of 80h through FFh

Each SFR has an address and a name
76/175
Part 2
Intel 8051: SFR
0
1
2
3
4
5
6
7
F8
F0
FF
B
F7
E8
E0
EF
ACC
E7
D8
D0
DF
PSW
D7
C8
CF
C0
C7
B8
IP
BF
B0
P3
B7
A8
IE
AF
A0
P2
A7
98
SCO N
90
T1
88
TCON
TM OD
TL0
TL1
80
T0
SP
DPL
DPH
SBUF
9F
97
TH0
TH1
8F
PCO N
87
77/175
Part 3
Intel 8051: SFR

– The Stack Pointer is
initialized on 0x07
after a reset, and this causes
stack to begin at location
0x08
Accumulator (A)
– Accumulator register

B Register (B)
– Used during multiply and
divide operations

PSW
– Contains program status
information

Stack Pointer (SP)
– Eight bits wide
– Stack may reside anywhere
in on chip RAM

Data Pointer(DPTR)
– Consist high byte (DPH) and
low byte (DPL)
– It may be manipulated as a
16-bit register or as two
independent 8-bit registers
78/175
Part 4
Intel 8051: SFR

Ports 0 to 3 (P0, P1, P2, P4)

– (TH1, TL1) (TH0, TL0)
Counting Registers for
Timer/Counter 1 and 0
– Latches of Port 0 to 3,
respectively

Serial Data Buffer (SDBF)
– It is actually two separated
registers: receive and
transmit buffer registers
– When data is moved to SBUF
it goes to the transmit buffer
– When data is moved from
SBUF it comes from the
receive buffer
Timer Registers (T1, T0)

Control Registers
–
–
–
–
–
IP: Interrupt priority
IE: Interrupt enable
TMOD Timer/Counter mode
TCON Timer/Counter control
PCON Power control
79/175
Intel 8051: PSW
PSW
C a r ry flag
A u xilia r y C a r ry fla g
F la g 0
R e g is ta r B a n k
S e le ct b it 1
7
6
5
4
3
2
CY
AC
F0
R S1
R S0
OV
1
0
-
P
P a r ity fla g
O v er flo w fla g
R e g is ta r B a n k
S e le ct b it 1

Auxiliary Carry flag is used for BCD operations
 Flag 0 is available to user for general purposes
 The contest of (RS1, RS2) enable working register banks as follows:
00 - Bank 0 [0x00-0x07], 01 - Bank 1 [0x08-0x0f],
10 - Bank 2 [ 0x10-0x17], 11 - Bank 3 [0x18-0x1F]
80/175
Intel 8051: CPU Timing
S5
P1
P2
S6
P1
P2
S1
P1
P2
S2
P1
P2
S3
P1
P2
S4
P1
P2
S5
P1
P2
S6
P1
P2
S1
P1
P2
S2
P1
P2
S3
P1
P2
S4
P1
S5
P2
P1
ALE

The internal clock generator defines
the sequence of states that make up a machine cycle
 A machine cycle consists of 6 states, numbered S1 through S6
 Each state time lasts for two oscillator periods
 Each state is then divided into a Phase 1 and Phase 2 half
81/175
P2
Part 1
Intel 8051: Port Structures

Pseudo bi-directional
I/O port structure
– On Port0 R2 is disabled
except during bus operations
(open-collector output)



The address latch bit is updated by
direct addressing instructions
The value read is “OR-tied” function
of Q1 and the external device
To use a pin for input
latch must be set
+5V
R EA D /M O D IFY/
W R IT E
+5V
EN B
Q2
R1
S ET
D
IN TER N A L B U S
Q
I/O
PIN
W R IT E PU L SE
Q1
Q
CLR
B U S C YC L E
T IM IN G
EN B
R2
IN PU T
B U F FER
R EA D
82/175
Intel 8051: Port Interfacing

The output buffers of Ports 0, 1, 2 and 3
can each drive 4 LS TTL inputs
 Can be driven by open-collector and open-drain outputs
– 0-to-1 transitions will not be fast since
there is little current pulling the pin up


Port 0 output buffers can each drive 8 LS TTL inputs
(external bus mode)
As port pins PORT 0 requires external pull-ups
to be able to drive any inputs bit
83/175
Intel 8051: Special Peripheral Functions

There are few special needs
common among control-oriented computer systems:
–
–
–
–
keeping tracks of elapsed time
maintaining a count of signal transitions
measuring the precise width of input pulses
communicating with other systems
– closely monitoring asynchronous external events
84/175
Part 1
Intel 8051: Timers/Counters

Two 16-bit Timer/Counter registers
 Timer: Register is incremented every machine cycle
(1 machine cycle = 12 oscillator periods)
 Counter: Register is incremented in response to
1-to-0 transition at its corresponding external input pin (T0, T1)
– External input is sampled at S5P2 of every machine cycle
– When the samples show high in one cycle and low in the next,
the count is incremented
– The new count value is appears in S3P1
of the following detection cycle
– Max count rate is 1/24 of oscillator frequency

TMOD - Timer/Counter mode register
 TCON - Timer/Counter control register
85/175
Part 2
Intel 8051: Timers/Counters

GATE: Gating control when set
 C/T: Counter or Timer Selector
 M1 M0:
– 00: 8-bit Timer/Counter with 5-bit
prescaler
– 01: 16-bit Timer/Counter
– 10: 8-bit auto reload
Timer/Counter
– 11: (Timer0)
TL0 is 8-bit Timer/Counter
controlled by Timer0 control bits
TH0 is 8-bit timer only controlled
by Timer1 control bits
– 11: (Timer1) Timer/Counter is
stopped
TIMER0
TIMER1
GATE
C/T
M1
M0
86/175
Part 3
Intel 8051: Timers/Counters
TC O N

7
6
5
4
3
2
1
0
TF1
TR 1
TF0
TR 0
IE 1
IT 1
IE 0
IT 0
TF: Overflow flag
– Set by hardware on Timer/Counter overflow
– Cleared by hardware when processor vectors to interrupt routine

TR: Run control bit
– Set/Cleared by software to turn Timer/Counter on/off

IE: Interrupt Edge flag
– Set by hardware when external interrupt edge detected
– Cleared when interrupt processed

IT: Interrupt Type control bit
– Set/Cleared by software to specify
falling edge/low level triggered external interrupts
87/175
Part 4
Intel 8051: Timers/Counters
OSC
1/12
TL1
(5 bits)
TH1
(8 bits)
TF1
INTERRUPT
T1 PIN
TR1
GATE
MODE 0
INT1 PIN
88/175
Part 5
Intel 8051: Timers/Counters
OSC
1/12
C/T=0
TL1
(8 bits)
TH1
(8 bits)
TF1
INTERRUPT
C/T=1
T1 PIN
TR1
GATE
MODE 1
INT1 PIN
89/175
Part 6
Intel 8051: Timers/Counters
OSC
1/12
TL1
(8 bits)
TF1
INTERRUPT
T1 PIN
RELOAD
TR1
GATE
TH1
(8 bits)
MODE 2
INT1 PIN
90/175
Part 7
Intel 8051: Timers/Counters
OSC
1/12
C/T=0
TL0
(8 bits)
TF0
INTERRUPT
C/T=1
T0 PIN
MODE 3
TR0
GATE
INT0 PIN
1/12 fosc
TH0
(8 bits)
TF1
INTERRUPT
TR1
91/175
Part 1
Intel 8051: Serial Port Interface

Full-duplex
 Serial port receive and transmit registers
are both accessed at Special Function Register SBUF
– Writing to SBUF loads the transmit register
– Reading from SBUF accesses a physically separated receive register

Four modes of operation
– In all four modes transmission is initiated by
any instruction that uses SBUF as destination register
– Reception is initiated in Mode 0 by condition RI=0 and REN=1
In other modes by the incoming start bit if REN=1

SCON - Serial Port Control Register
92/175
Part 2
Intel 8051: Serial Port Interface
SCON

6
5
4
3
2
1
0
SM0
SM1
SM0
REN
TB8
RB8
TI
RI
SM0 SM1:
–
–
–
–

7
00: Mode 0, Shift register, fosc//12
01: Mode 1, 8-bit UART, variable
10: Mode 2, 9-bit UART, fosc//32 or fosc//64
11: Mode 3, 9-bit UART, variable
SM2: Enables multiprocessor features in Mode 2 and Mode 3
– When the stop bit is received,
the interrupt will be activated only if RB8=1 (9th bit =1)

REN: Enables serial reception
–
Set/Clear by software
93/175
Part 3
Intel 8051: Serial Port Interface
SCON

7
6
5
4
3
2
1
0
SM0
SM1
SM0
REN
TB8
RB8
TI
RI
TB8: 9th data bit that will be transmitted in Mode2 and Mode3
– Set/Clear by software

RB8: 9th data bit that was received in Mode2 and Mode3
In Mode 1, if SM2=0, is the stop bit that was received
 TI: Transmit interrupt flag
– Set by hardware. Must be cleared by software

RI: Receive interrupt flag
– Set by hardware. Must be cleared by software
94/175
Part 4
Intel 8051: Serial Port Interface

MODE 0:
–
–
–
–

Serial data enters and exits through RXD
TXD outputs shift clock
8 bits are transmitted/received: 8 data bits (LSB first)
The baud rate is fixed at 1/12 oscillator frequency
MODE 1:
– Serial data enters through RXD, exits through TXD
– 10 bits are transmitted/received:
start bit(0), 8 data bits (LSB first), stop bit(1)
– On receive the stop bit goes into RB8 in SCON register
– The baud rate is variable
95/175
Part 5
Intel 8051: Serial Port Interface

MODE 2:
– Serial data enters through RXD, exits through TXD
– 11 bits are transmitted/received:
start bit(0), 8 data bits (LSB first), a programmable 9th bit, stop bit(1)
– On transmit, the 9th bit is TB8 in SCON register
– On receive, the 9th bit goes into RB8 in SCON register
– The baud rate is programmable to either
1/32 or 1/64 the oscillator frequency

MODE 3:
– Same as MODE 2 in all respects except baud rate
– The baud rate is variable
96/175
Part 6
Intel 8051: Serial Port Interface

Mode 0 Baud Rate = Oscillator frequency/12
 Mode 2 Baud Rate =[(2SMOD)/64]*Oscillator frequency
– SMOD is bit in Special Function Register PCON

Mode 1 and Mode3 baud rate is
determined by Timer 1 overflow rate
 Mode 1,3 Baud Rate =[(2SMOD)/32]* Timer 1 Overflow Rate
– Timer mode, auto-reload :
Timer Overflow Rate=Oscillator frequency/[12*(256-TH1)]
97/175
Part 7
Intel 8051: Serial Port Interface
T im e r1
Baud
R a te
fosc
6 2 .5 K
12 M Hz
1 9 .2 K
SM OD
C /T
M ode
R e lo a d
V a lu e
1
0
2
FF
1 1 .0 59 M H z
1
0
2
FD
9 .6 K
1 1 .0 59 M H z
0
0
2
FD
4 .8 K
1 1 .0 59 M H z
0
0
2
FA
2 .4 K
1 1 .0 59 M H z
0
0
2
F4
1 .2 K
1 1 .0 59 M H z
0
0
2
E8
1 3 5 .5
1 1 .0 59 M H z
0
0
2
1D
110
6 MHz
0
0
2
72
110
12 M Hz
0
0
1
FEEB
98/175
Part 1
Intel 8051: Interrupt Control
IE

7
6
5
4
3
2
1
0
EA
-
-
ES
ET!
EX1
ET0
EX0
EA: Enable/Disable all interrupts
– If EA=0 no interrupts will be acknowledged
– If EA=1 each interrupt source is individually enabled/disbled

ES: Serial Port interrupt enable bit
 ET: Timer interrupt enabled bit
 EX: External interrupt enable bit
99/175
Part 2
Intel 8051: Interrupt Control
• 5 interrupt sources
IT0=0
• 2 external
INT0
(INT0, INT1)
• 2 timers
(TF0, TF1)
IE0
IT0=1
TF0
• Serial Port
(RI or TI)
IT1=0
INT1
IE1
INTERRUPT
SOURCE
IT1=1
TF1
RI
TI
100/175
Part 3
Intel 8051: Interrupt Control

External interrupts
–
–
–
–
IT 0 = 0
IN T 0
Level-activated or transition-activated
IT 0 = 1
depending on bits IT0, IT1 in register TCON
The flags that generate these interrupts are
IE0, IE1 in TCON
• Cleared by hardware if the interrupt was transition-activated
• if the interrupt was level-activated,
external source controls request bits
If external interrupt is level-activated,
the external source has to hold request active,
until the requested interrupt is actually generated.
External source has to deactivate the request
before interrupt service is completed,
or else another interrupt will be generated
IE 0
101/175
Part 4
Intel 8051: Interrupt Control

Timer interrupts
– Interrupts are generated by TF0 and TF1 in register TCON
– When a timer interrupt is generated, the flag that generated it is
cleared by hardware when the service routine is vectored to

Serial Port interrupt
– generated by the logical OR of bits RI and TI in register SCON
TI
RI
102/175
Part 5
Intel 8051: Interrupt Control
IP
7
6
5
4
3
2
1
0
-
-
-
PS
PT1
PX1
PT0
PX0

Priority bit=1: High Priority; Priority bit=0: Low Priority
 PS: Serial Port priority bit
 PT: Timer priority bit
 PX: External priority bit
103/175
Part 6
Intel 8051: Interrupt Control

A low-priority interrupt can be interrupted by a higher priority
interrupt, but not by another low-priority interrupt
 A high priority interrupt
cannot be interrupted by any other interrupt source
 If two requests are received simultaneously,
the request of higher priority level is serviced
 If requests of the same priority level are received simultaneously,
an internal polling sequence determines which request is serviced
– ``priority within level'' structure is only used
to resolve simultaneous requests of the same priority level.
104/175
Part 7
Intel 8051: Interrupt Control
In te rru p t P rio rity
w ith in L e ve l P o llin g S e q u e n c e
1 (H ig h e s t)
E x te rn al In te rru p t 0
2
T im e r 0
3
E x te rn al In te rru p t 1
4
T im e r 1
5 (L ow e s t)
S e ria l P o rt
105/175
Part 8
Intel 8051: Interrupt Control





The INT0 and INT1 levels are inverted and latched
into the Interrupt Flags IE0 and IE1 at S5P2 of every machine cycle
Serial Port flags RI and TI are set at S5P2
The Timer 0 and Timer 1 flags, TF0 and TF1,
are set at S5P2 of the cycle in which the timers overflow
If a request is active and conditions are right,
a hardware subroutine call to the requested service routine
will be the next instruction to be executed
In a single-interrupt system, the response time is always
more than 3 cycles and less than 9 cycles
106/175
Part 1
Intel 8051: Reset





The reset input is the RST pin, which has a Schmitt Trigger input
Accomplished by holding the RST pin high
for at least two machine cycles (24 oscillator periods)
while the oscillator is running
The RST pin is sampled during S5P2 of every machine cycle
While the RST pin is high,
the port pins, ALE and PSEN are weakly pulled high
Driving the ALE and PSEN pins to 0 while reset is active
could cause the device to go into an indeterminate state
107/175
Part 2
Intel 8051: Reset
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
RST
INTERNAL RESET SIGNAL
SAMPLE
RST
SAMPLE
RST
ALE
PSEN
P0
IN
S.
IN
A0-A7
IN
S.
IN
A0-A7
11 OSC. PERIODS
IN
S.
IN
A0-A7
IN
S.
IN
A0-A7
IN
S.
IN
A0-A7
IN
S.
IN
19 OSC. PERIODS
108/175
Intel 8051: Power On Reset

RST pin must be held high long enough to allow the oscillator to
start up plus two machine cycles
 The oscillator start-up time depend on the oscillator frequency
 Port pins will be in a random state until the oscillator has started
and the internal reset algorithm has written 1s to them
 Powering up the device without a valid reset could cause the CPU
to start executing instructions from an indeterminate location
109/175
Intel 8051: EPROM Versions

Electrically programmable by user
 Relative slow
 Limited number of erase/write cycles
110/175
Intel 8051: OTP Versions

One Time Programmable
 It is standard EPROM without erasing window
 It is used for limited production
111/175
Intel 8051: FLASH Versions






Supports in-system and in-board code changes
Electrically erasable
Reduces code inventory and scrap
Simplifies the task of upgrading code and
reduces upgrade cycle time
Provides just-in-time system software downloads
Truly non-volatile
112/175
Intel 8051: The On-Chip Oscillator

Intel 8051
microcontrollers have
an on-chip oscillator
 resonators are
connected between
XTAL1 and XTAL2
pins
 external oscillators
(HMOS or CMOS)
8051
QUARTZ CRYSTAL OR
CERAMIC RESONATOR
C1
C2
XTAL2
XTAL1
VSS
113/175
Intel 8051: Power Management

Low power devices
 Power saving
 Voltage monitoring
114/175
Intel 8051: Power Reduction Modes

CHMOS versions provides power reduced modes of operations
 There are two power reducing modes Idle and Power Down
 In the Idle mode oscillator continues to ran
Interrupt, Timer and Serial Port blocks continue to be clocked
clock signal is gated off to the CPU
 In the Power Down mode the oscillator is frozen
115/175
Part 1
Intel 8051: Instruction Set
A rith m e tic O p e ra tio n s
AD D
A d d itio n
AD D C
A d d itio n w ith C a rry F la g
SUBB
S u b tra c tio n
IN C
In c re m e n t
DEC
D e c re m e n t
MUL
M u ltip ly
D IV
D ivid e
DA
D e c im a l A d ju s t A c c u m u la to r
116/175
Part 2
Intel 8051: Instruction Set
L o g ic a l O p e ra tio n s
AN D
And
ORL
Or
XRL
E x c lu s ive -O r
CLR
A
C le a r (A c c u m u la to r)
CPL
A
C o m p le m e n t
RL
A
R o ta te L eft
RLC
A
R o ta te L eft th ro u g h C a rry F la g
RR
A
R o ta te R ig h t
RLC
A
R o ta te R ig h t th ro u g h C a rry F la g
SW AP
A
S w a p n ib b le s w ith in A c c u m u la to r
117/175
Part 3
Intel 8051: Instruction Set
D a ta T ra n s fe r
MOV
M o ve
M OVC
M o ve C o d e b yte
M OVX
M o ve E x te rn al R AM b yte /w o rd
PUSH
P u s h d ire ct b yte o n sta c k
POP
P o p d ire ct b yte fro m sta c k
XCH
Exchange
XCHD
E x c h a n g e low o rd e r D ig it
118/175
Part 4
Intel 8051: Instruction Set
B o o le a n V a ria b le M a n ip u la tio n
CLR
C le a r b it/fla g
SET
S e t b it/fla g
CPL
C o m p le m e n t b it/fla g
AN L
A N D b it a n d fla g
ORL
O R b it a n d fla g
MOV
M o ve b it
119/175
Part 5
Intel 8051: Instruction Set
P ro g ra m a n d M a c h in e C o n tro l # 1
AC ALL
A b s o lu te S u b ro u tin e C all
LC ALL
L o n g S u b ro u tin e C all
RET
R e tu rn fro m S u b ro u tin e
R ETI
R e tu rn fro m in te rru p t
AJM P
A b s o lu te J u m p
LJM P
Long Jum p
SJM P
S h o rt (R e lative ) J u m p
JM P
@ A+DPTR
J u m p in d ire c t rela tive to th e D P T R
120/175
Part 6
Intel 8051: Instruction Set
P ro g ra m a n d M a c h in e C o n tro l # 2
JZ
J u m p if Ac c u m u la to r is Z e ro
JN Z
J u m p if Ac c u m u la to r is N o t Z e ro
JC
J u m p if C a rry fla g is s e t
JN C
J u m p if N o C a rry fla g
JB
J u m p if B it s e t
JN B
J u m p if B it N o t s e t
JB C
J u m p if B it s e t & C le a r b it
C JN E
C o m p a re a n d J u m p if N o t Z e ro
D JN Z
D e c re m e n t a n d J u m p if N o t Z e ro
NOP
N o O p e ra tio n
121/175
Part 7
Intel 8051: Instruction Set
In s tru c tio n s th a t a ffe c t F la g S e ttin g s # 1
C
OV
AC
AD D
X
X
X
AD DC
X
X
X
SUBB
X
X
X
M UL
0
X
D IV
0
X
DA
X
RRC
X
RLC
X
122/175
Part 8
Intel 8051: Instruction Set
In s tru c tio n s th a t a ffe c t F la g S e ttin g s # 2
C
SET
C
1
CLR
C
0
CPL
C
X
ANL
X
ORL
X
MOV
C , b it
OV
AC
X
X
X
C JN E
X
O p e ra tio n s o n P S W
X
123/175
Intel 8051: Addressing Modes

Immediate Addressing
MOV A,#20h

Direct Addressing

Indirect Addressing
MOV A,30h
MOV A,@R0
– refers to Internal RAM, never to an SFR

External Direct
– only two commands that use External Direct
MOVX A,@DPTR
MOVX @DPTR,A
– DPTR holds the correct
external memory address

External Indirect

Code Indirect
MOVX @R0,A
MOVC A,@A+DPTR
124/175
Part 1
Intel 8051: Keil C Compiler

Keil Compiler C51 includes extensions (for ANSI C) for:
–
–
–
–
–
–
–
–
Memory Types and areas on the 8051
Memory Models
Memory Type Specifiers
Variable Data Type Specifiers
Bit variables and bit-addressable data
Special Function Registers
Pointers
Function Attributes
125/175
Part 2
Intel 8051: Keil C Compiler

Program Memory
– code specifier refers to to the 64Kbyte code memory
char code text[] = “ENTER PARAMETER”;
– Accessed by opcode MOVC @A+DPTR

Program Memory is read only; it cannot be written to
 It can reside within 8051 CPU, it may be external, or both
 Program code, including all functions and library routines are
stored in program memory
126/175
Part 3
Intel 8051: Keil C Compiler

Data Memory
– Up to 256 bytes of internal data memory are available
depending upon the 8051 derivate
– data refers to the first 128 bytes of internal memory
char data var1;
– idata refers to all 256 bytes of internal data memory
generated by indirect addressing
float idata x,y,z;
– bdata refers to 16 bytes of bit-addressable memory
in the internal data memory (20h to 2Fh)
char bdata flags;
127/175
Part 4
Intel 8051: Keil C Compiler

External Data Memory
– xdata specifier refers to any location
in the 64KByte address space of external data memory
unsigned long xdata array[100];
– pdata specifier refers to only 1 page of 256 bytes
of external data memory
unsigned char xdata vector[10][4][4];
128/175
Part 5
Intel 8051: Keil C Compiler

Special Function Register Memory
– SFRs are declared in the same fashion as other C variables
– sfr (rather then char or int)
sfr P0 = 0x80; /*Port0, address 80h*/
– sfr16 access 2 SFRs as 16-bit SFR (8051 derivatives)
sfr16 T2 = 0xCC /*Timer 2; T2L 0CCh, T2H 0CDh)
– sbit allows to access individual bits within an SFR
sfr PSW=0xD0;
sfr IE=0xA8;
sbit EA=IE^7;
sbit OV=0xD0^2;
sbit CY=0xD7;
129/175
Part 6
Intel 8051: Keil C Compiler

Unique C51 Data Types
– bit
static bit done_flag=0;
– sbit
sbit EA= oxAF; /*defines EA to be the SFR bit at 0xAF*/
– sfr(Special Function Registers, 0x80-0xFF)
sfr P0 = 0x80; /* Port-0, address 80h*/
sfr P2 = 0xA0; /* Port-2, address 0A0h */
– sfr16
sfr16 T2=0xCC; /* Timer 2: T2L 0CCh, T2H 0CDh
130/175
Part 7
Intel 8051: Keil C Compiler

Memory Models
– SmallModel all variables, by default, reside in the internal data memory
• All objects, as well as stack must fit into internal RAM
– Compact Model all variables, by default, reside in one page of external data memory
• Can accommodate a maximum of 256 variables
• Slower then small model
– Large Model all variables, by default, reside in external data memory
• The Data Pointer (DPTR) is used for addressing
• Memory access is inefficient
• Generates more code then small and compact model
131/175
Part 8
Intel 8051: Keil C Compiler

Memory-specific Pointers
– Include a memory type specification in the pointer declaration
– May be used to access variables in the declared memory area only
char data *str;
int xdata *numtab;
long code *powtab;
132/175
Part 9
Intel 8051: Keil C Compiler

Function Declarations Extensions allow to:
–
–
–
–
Specify a function as an interrupt procedure
Choose register bank used
Select the memory model
Specify reentrancy
[return_type] funcname ([args])
[{small|compact|large}]
[reentrant][interrupt n][using
n]
•
•
•
•
small, compact, large - memory model
reentrant - recursive function
interrupt - interrupt function
using - specify register bank
133/175
Part 10
Intel 8051: Keil C Compiler

Function Parameters and the Stack
– The stack pointer on the 8051 access internal data memory only
– C51 locates the stack area immediately following
all variables in the internal data memory
– The stack pointer access internal data memory inirectly
– C51 assigns a fixed memory location for each function parameter
– Only return address is stored on the stack
– Interrupts fuctions switch register banks and
save the values of few registers on the stack
– By default, the C51 compiler passes up to three arguments in registers
134/175
Part 11
Intel 8051: Keil C Compiler

Passing Parameters in Registers
A rg u m e n t
N um ber
char
1 b yte p tr
in t
2 b yte s p tr
lo n g
flo a t
g e n e ric p tr
1
R7
R 6& R 7
R 4 -R 7
R 1 -R 3
2
R5
R 4& R 5
R 4 -R 7
R 1 -R 3
3
R3
R 2& R 3
135/175
Part 12
Intel 8051: Keil C Compiler

Function Return Values
R e tu rn T yp e
R e g is te r
b it
C a rry F la g
char
R7
in t
R 6& R 7
M S B in R 6 , L S B in R 7
lo n g
R 4 -R 7
M S B in R 4 , L S B in R 7
flo a t
R 4 -R 7
3 2 -b it IE E E fo rm a t
g e n e ric p tr
R 1 -R 3
M e m o ry typ e in R 3 ,
M SB R 2, LSB R 1
D e s c rip tio n
136/175
Part 13
Intel 8051: Keil C Compiler

Specifying the Memory Model for a Function
#pragma small /*default small model */
extern int calc (char i, int b) large reentrant;
extern int func (char i, float f) large;
extern void *tcp (char xdata *xp, int ndx) small;
int mtest (int i, int y){ /*small model*/
return (i*y + y*i + func(-1, 4.75);}
int large_func (int i, int k) large { /*large model*/
return (mtest(i,k) * 2)}
137/175
Part 14
Intel 8051: Keil C Compiler

Specifying the RegisterBank for a Function
void rb_function (void ) using 3 { ... }
– The using attribute affects object code as follows:
• The currently selected register bank is saved on stack
• The specified register bank is set
• The former register bank is restored before the function is exited
– Register banks are useful when processing interrupts or
when using a real-time operating system
– The using attribute may not be used in
functions that returns a value in registers
138/175
Part 15
Intel 8051: Keil C Compiler

Register Bank Access
 The REGISTERBANK control directive allows you to specify which
default register bank to use
 Upon reset, 8051 loads the PSW with 00h, which selects register
bank 0. To change this, you sholud:
– Modify the startup code to select a different bank
– Specify the REGISTERBANK control directive along with the new
register bank number

By default, C51 generates code that accesses the registers R0-R7
using absolute addresses
 To make a function insensitive to the current bank, it must be
compiled using the NOAREGS control directive
139/175
Part 16
Intel 8051: Keil C Compiler

Interrupt Functions
void timer0 (void) interrupt 1 using 2 {
if (++interruptcnt == 4000){
second++;
Interruptcnt=0; }
}
– The interrupt attribute takes an argument
an integer constant in the 0 to 31 value range
– The interrupt attribute affects object code as follows:
• The contains of SFR ACC, B, DPH, DPL and PSW,
when required, are saved on stack
• All working registers are stored on stack
if a register bank is not specified
• SFRs and working registers are restored before exiting function
• The function is terminated by 8051 RETI instruction
140/175
Part 17
Intel 8051: Keil C Compiler

Reentrant Function can be shared by several processes at the
same time.
 When a reentrant function is executing, another process can
interrupt it and then begin to execute that same function. The
reentrant functions may be called recursively:
int calc (char i, int b) reentrant {
int x;
x=table[i];
return (x*b);
}
 Reentrant functions can be called simultaneously by two or more
processes.
 Reentrant functions are often required in real-time applications or
when interrupt and non-interrupt code must share a function.
141/175
Part 18
Intel 8051: Keil C Compiler

Functions may be selectively defined as reentrant, using the
reentrant attribute.
 For each reentrant function, a reentrant stack area is simulated in
internal or external memory.
 The following rules apply to reentrant functions:
–
–
–
–
–
–
bit type arguments or local variables may not be used
must not be called from alien functions or using alien attribute
may have other attributes like using or interrupt
return addresses are stored in the 8051 hardware stack
functions using different memory models may be intermixed
each of three reentrant models (small, compact and large) contains its
own reentrant stack and SP
142/175
Part 19
Intel 8051: Keil C Compiler

Control directives are used to control the operation of the
compiler and can be specified after the filename on the command
line or within a source file using the #pragma directive:
C51 testfile.c SYMBOLS CODE DEBUG
or
#pragma SYMBOLS CODE DEBUG

Directive categories:
– source controls define macros on the command line and determine
the name of the file to be compiled)
– object controls affect the form and content of the generated object
module; allow you to specify the optimizing level or include
debugging information in the object file
– listing controls govern various aspects of the listing file (format and
specific content)
143/175
Part 20
Intel 8051: Keil C Compiler

The C51 is an optimizing compiler.
 The C51 provides six different levels of optimizing:
–
–
–
–
–
constant folding, simple access optimizing, jump optimizing
dead code elimination, jump negation
data overlaying
peephole optimizing
register variables, extended access optimizing, local common
subexpression elimination, case/switch optimizing
– global common subexpression elimination, simple loop optimizing
– loop rotation
144/175
Part 21
Intel 8051: Keil C Compiler

General optimizations:
– constant folding: several constant values occurring in an expression
or address calculation are combined as a constant
– jump optimizing: jumps are inverted or extended to the final target
addresses when the program efficiency is thereby increased
– dead code elimination: code which cannot be reached is removed
– register variables: automatic variables and function arguments are
located in registers when possible
– parameter passing via registers: a maximum of three function
arguments can be passed in registers
– global common subexpression elimination: identical subexpressions
or address calculations that occur multiple times in a function are
calculated only once
145/175
Part 22
Intel 8051: Keil C Compiler

8051 - specific optimizations
– peephole optimization: complex operations are replaced by simplified
operations when memory space or execution time can be saved as a
result
– extended access optimizing: constants and variables are included
directly in operations
– data overlaying: data and bit segments of functions are overlaid with
other data and bit segments by the linker/locator
– case/switch optimization: any switch and case statements are
optimized by using a jump table or string of jumps
146/175
Part 23
Intel 8051: Keil C Compiler

Options for code generation:
– OPTIMIZE(SIZE): common C operations are replaced by subprograms,
thereby reducing the program code
– NOAREGS: C51 no longer uses absolute register access; program
code is independent of the register bank
– NOREGPARAMS: parameter passing is always performed in local data
segments
147/175
Part 24
Intel 8051: Keil C Compiler

You can easily interface C51 to routines written in 8051 assembler
 For an assembly routine to be called form C, it must be aware of
the parameter passing and return value conventions used in C
Function parameters
 By default C functions pass up to three parameters in registers.
The remaining parameters are passed in fixed memory locations.
 Functions that pass parameters in registers are prefixed with the
underscore character (_functionName)
148/175
Part 25
Intel 8051: Keil C Compiler
Parameter passing in registers
arg.no. char, 1byte ptr. Int, 2byte ptr
1
R7
R6&R7
2
R5
R4&R5
3
R3
R2&R3
long,float
R4-R7
R4-R7
gen.ptr
R1-R3
R1-R3
R1-R3
func1 (int a) - a is passed in R6 and R7
func2 (int b, int c, int *d) - b is passed in R6&R7, c in R4 & R3, d in R1, R2 & R3
func3 (long e, long f) - e is passed in R4, R5, R6 & R7, f cannot be located in
registers
func4(float g, char h) - g is passed in R4, R5, R6 & R7, h cannot be passed in
registers
149/175
Part 26
Intel 8051: Keil C Compiler
Parameter passing in fixed memory locations
 Parameters passed to assembly routines in fixed memory locations
use segments named ?function_name?BYTE and
?function_name?BIT to hold the parameter values passed to the
function function_name.
Function return values
 Function return values are always passed using CPU registers:
return type
register
bit
char/unsigned char/1-byte pointer
int/unsigned int/2-byte pointer
long/unsigned long/float
generic pointer
carry flag
R7
R6 & R7
R4 - R7
R1-R3
150/175
Part 27
Intel 8051: Keil C Compiler
Example:
#pragma SRC
#pragma SMALL
unsigned int asmfunc1(unsigned int arg) { return (1+arg); }
NAME ASM1
?PR?_asmfunc1?ASM1 SEGMENT CODE
PUBLIC _asmfunc1
RSEG ?PR?_asmfunc1?ASM1 USING 0
_asmfunc1:
mov A,R7
add A,#10h
MOV R7,A
CLR A
ADDC A,R6
MOV R6,A
?C0001: RET END
151/175
Intel 8051: Manufacturers

AMD

ARM Microcontrollers
 ARC Cores
 Atmel
 Dallas

Hitachi semiconductors

Intel

ISSI

Matra

Microchip

OKI
 Philips

Siemens

SMC

SSI

Texas Instruments
 ZiLog
 etc.
152/175
Intel 8051: Additional Features





Watch Dog Timers
Clock Monitor
Resident Program Loader
Software protection
P Supervisory Circuit
153/175
Watch Dog Timers

Provides a means of graceful recovery from a system problem
 If the program fails to reset the watchdog at some predetermined
interval, a hardware reset will be initiated
 Especially useful for unattended systems
154/175
Clock Monitor

If the input clock is too slow, a clock monitor can shut the
microcontroller down
 Usually software controlled status (on/off)
155/175
Resident Program Loader

Loads a program by initializing program/data memory from either a
serial or parallel port
 Eliminates the erase/burn/program cycle (typical with EPROM’s)
 Allows system updating from an offsite location
156/175
Software protection

Protect unauthorized snooping (reverse engineering,
modifications, piracy, etc.
 Only OTPs and Windowed devices option
157/175
Part 1
P Supervisory Circuit

Functions:
–
–
–
–
–
–
–
–
P reset (active low or high)
Manual reset input
Two stage power fall warning
Backup-battery switchover
Write protection of RAM
2.275 threshold detector
Battery OK flag indicator
Watch Dog timer
PF1
1
16
OUT
PF0
2
15
BATT OK
Vcc
3
14
BATT
WDI
4
13
BATT ON
GND
5
12
CE IN
MR
6
11
CE OUT
LOW LINE
7
10
WDO
RESET
8
9
RESET
MAXIM
MAX807
158/175
Part 2
P Supervisory Circuit
P IN
N AM E
1
PFI
P o w e r-F a ll In p u t
2
PFO
P o w e r-F a ll O u tp u t
3
VCC
In p u t S u p p ly V o lta g e
4
W DI
W a tc h d o g In p u t
5
GND
G ro u n d
6
MR
7
L O W L IN E
L o w -L in e C o m p a ra to r In p u t
8
R E S E T (H )
A c tive -H ig h R e s e t O u tp u t
F U N C T IO N
M a n u a l-R e s e t In p u t
159/175
Part 3
P Supervisory Circuit
P IN
N AM E
9
R E S E T (L )
10
W DO
11
CE OUT
12
C E IN
C h ip -E n a b le In p u t
13
B ATT O N
B a tte ry O n O u tp u t
14
B ATT
15
B ATT O K
16
OUT
F U N C T IO N
A c tive -L o w R e s e t O u tp u t
W a tc h d o g O u tp u t
C h ip -E n a b le O u tp u t
B a c k u p -B a tte ry In p u t
B a tte ry O K S ig n a l O u tp u t (V b a tt> 2 .2 6 5 )
O u tp u t S u p p ly V o lta g e to C M O S R A M
160/175
Part 4
P Supervisory Circuit
+5V
0.1uF
0.1uF
Vcc BATT OUT
ON
BATT
REAL
TIME
CLOCK
CMOS
RAM
CE OUT
MR
OTHER
SYSTEM
RESET
SOURCES
CE IN
PUSH
BUTTON
SWITCH
MAXIM
MAX807
WDI
LOW LINE
ADDRESS
DECODE
ADDRESS
I/O
NMI(INT)
RESET
+12V
RESET
BATT OK
RESET
INT
uP
PFI
PFO
WDO
+12V FAILURE
WATCHDOG FAILURE
GND
161/175
Comparative Characteristics
M an u factu re r
C loc k
[M H z]
V
[V ]
ROM
[K B ]
RAM
[b ytes]
I/O
T im e rs/
C ou n ters
com m u n ication
A tm el
24
2.7 to
6
2 to 8
128 to
256
32
U p to 3
full duplex
serial port
0 to 16
256-byte
to 1.2
k byte
3
tw o serial
U SA R T s
w atchdog,
pow er m onitor,
address and
data encryption
0 to 32
128 to
256
2 to 3
serial port
4 to 8 channel 8bit A D C ,
w atchdog,
PW M
32
2 to 3
serial port,
I2C
ROM
protection and
secret tag,
w atchdog
D allas
25 to 33
In tel
0.5 to
24
2.7 to
6
M atra
42
2.7 to
6
4 to 32
128 to
256
O ki
24
2.7 to
5.5
0 to 16
128 to
256
32
2 to 3
serial port
S iem en s
18 to 40
8 to 32
256-byte
to 2.2k byte
56
3 to 4
tw o serial
ports
24 to
56
A d d ition al
F eatu res
tw o w atchdog
tim ers, 16-bit
M P Y /D IV unit
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Intel 8051-Design Example
The complete design project using the 8051 microcontroller will be
presented here. All design phases mentioned earlier will be shown:
– specification
– circuit diagram
– pcb layout
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Specification
The idea is to design a small, simple PCB for test purposes. The
device will have:
– 8 driver outputs (ie. LEDs, relays)
– a speaker output
– a light sensor input
– 3 extra inputs
– optional serial port
The device will be based on Atmel AT89C2051microprocessor, a 20
pin 8051 variant with FLASH program memory.
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Circuit Diagram
165/175
Circuit Description

The battery power supply is connected on terminals T1 &T2. While the circuit diagram specifies
3v/4.5v battery, the part ULN2803 needs 4.5v-5v battery to get proper operation.

Switch SW2 allows the PCB to be turned on and off.

Capacitor C1 provides a reset signal to the microprocessor.

XTAL1 provides the oscillator timing component for the microprocessor. It is important to use a
crystal for XTAL1, not a ceramic resonator - prototype testing shows that a ceramic resonator
gives problems unless capacitors to ground are placed on X1 & X2.

Diode D1 provides some protection for the microprocessor in case of transients or
misconnection of the battery

Optodarlington TR1 is the light sensor
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Circuit Description

TR2 is a switch used to sense illumination (On=TR1 illuminated)

Pin 6 of the micro is the LiteOn input (Low=TR1 illuminated)

SW1 is in parallel with the LiteOn input - pushing SW1 is like illuminating TR1

Resistors R12 & R13 pull up the open collector outputs P1.0 and P1.1 of IC1

IC2 is the driver IC, with several hundred milliamps drive capability on each output

R1-R8 limit the current that can be taken from each output of IC2, and are most useful
when LEDs are connected directly to pins L1-L8. If other devices are used, such as relays,
the values may of R1-R8 may have to be changed, or replaced with links.

R10 limits the current from IC1 into the base of TR3
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PCB Diagram
Central to the board are the
two IC's: The AT89C2051 (in
an IC socket) and ULN2803
driver. The bank of resistors
to the right of the ULN2803
are primarily for limiting the
current through LEDs, when
they are being driven direct
from the outputs. You may
wish to use another value
instead of the 27 ohm shown
on the circuit. The circuitry
to the left of the CPU is
primarily for the light sensor
- this is just a simple
darlington phototransistor,
sensitivity pot and switch
transistor.
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PCB Artwork, overlay
The overlay
diagram is used
for the silkscreen
(legend) of the
circuit board.
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PCB Artwork, top layer
The top layer
diagram is used
for the tracks
that go on the
component side
of the circuit
board.
170/175
PCB Artwork, bottom layer
The bottom layer
diagram is used for
the tracks that go on
the solder side of the
circuit board. The
layer is printed as if
you are viewing
through the circuit
board (this is a
convention used so
that the layers line
up) and will have to
be reversed left-forright before the
copper tracks are
printed.
171/175
PCB Art, Hole drilling diagram
172/175
Parts description

RB.06/.15 - Radial polarised capacitor, 0.060 inch pitch lead space, 0.15 inch diameter

RB.1/.2 - Radial polarised capacitor, 0.1 inch (2.5mm) pitch lead spacing, 0.2 inch (5mm) diameter

DIODE0.3 - Axial diode, 0.3 inch (7.5mm) pitch lead spacing

DIP20 - IC, standard 0.3 inch pitch 20 pin DIP package

DIP18 - IC, standard 0.3 inch pitch 18 pin DIP package

TP - Test point or terminal

PCLAMINATE - The part being specified here is the etched PCB laminate
173/175
Parts notes

2.2UF50VMM - Radial polarised capacitor, Microminiature style, eg Rubycon, elna

AT89C2051 - Atmel microprocessor, see Atmel site for data and a programmer

ULN2803A - Manufacturer: Allegro (formerly known as Sprague)

27E - Resistor, value 27 ohm - substitute if required for different outputs

MEL12 - Phototransistor - many substitutes will work, but darlington types offer the best
sensitivity. We have used BP103B (Farnell 212-763 in Australia). Flat goes toward TR2 for two
leaded devices.

3.57945Mhz - Frequency depends on application program. Use a crystal, rather than a ceramic
resonator (otherwise fit extra capacitors to gnd on X1 and X2).
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Using the Device
The diagram on the
left shows a typical
circuit using the
HSETI PCB, with
the optional serial
port in place also.
The serial port
does not have
strict RS232 level
signals, but will
work with just
about all PC clones
with reasonable
cable lengths.
175/175
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Embedded Systems