FPGA Two Day Advanced FPGA Workshop Instructors Craig Kief Deputy Director, COSMIAC email@example.com Brian Zufelt Engineer, COSMIAC Brian.firstname.lastname@example.org Karl Henry Instructor, JF Drake State Karl.Henry@DrakeState.edu Ui Luu Instructor, Glendale email@example.com Bassam Matar Instructor, Chandler-Gilbert firstname.lastname@example.org Pete Lomeli Instructor, Central Arizona Pete.Lomeli@centralaz.edu 1 Introductions • Who are you? • Where are you from? • What do you want to learn from this? • Where are the objectives? Labs we will cover Spin up Counter Testbench FSM Seq Det IP Cores Why we are here again Method: Immersive hands-on design for every student Students learn more, faster, and better with unrestricted access to design tools… …overall learning improves when applied design skills taught early; …overall performance improves when design skills used frequently; …and they like it* *results published in 2008 and 2009 ASEE proceedings I never teach my pupils; I only attempt to provide the conditions in which they can learn. Albert Einstein Technology keeps moving forward faster – get on the train or be left behind In a meeting the first week in June, Xilinx announced the following: • The new Virtex 7 devices use approximately 20 watts • They are actually four chips on a single chip connected with an interposer • The contain approximately 6.8 billion transistors Low-cost kits and Free CAD tools for every engineering student Digilent Basys2 Terasic DE0 Xilinx Spartan 3E Altera Cyclone III $59 $79 Digilent Nexys2 Terasic DE1 Xilinx Spartan 3E Altera Cyclone II $99 $125 No Lab Required! Students work on real designs at a time and place of their choosing FPGA’s Across the Curriculum Please interrupt and ask questions Overview All Xilinx FPGAs contain the same basic resources Logic Resources Slices (grouped into CLBs) Contain combinatorial logic and register resources Memory Multipliers Interconnect Resources Programmable interconnect IOBs Interface between the FPGA and the outside world Other resources Global clock buffers Boundary scan logic What makes up an FPGA? Simplified Slice Structure Slice 0 LUT Carry PRE D Q CE CLR Groups of Slices make up a Complex Logic Block (CLB) Each slice has four outputs Two registered outputs, two non-registered outputs LUT Carry D PRE Q CE CLR Spartan-3E Architecture CLB Slice DESIGN SYNTHESIS Hardware Descriptive Languages (HDL) VHDL VERILOG C++ SYSGEN Schematic Capture EDK IP Cores Limitless Tools Many files in – one file out One File = EDIF Syntax Checking Less Tool Choices IMPLEMENTATION PLACE AND ROUTE PROGRAM Place Logic onto the CLBs PROGRAM JTAG FPGA Route IOB CLB IOB UCF EDIF .BIT PROM ADEPT vs JTAG Chain ONE TOOL BEHAVIORAL SIMULATION TIMING SIMULATION Design How are FPGA projects Designed? There are many different methodolgies for programming (or designing) with FPGAs Hardware Descriptive Language (HDL) VHDL Verilog Schematic Capture C Code EDK System Generator VHDL Code The title of the article is "Analysis of the programmable logic usage and assurace survey results“ revision 10.1, sept 25,2002 Glenn research center, Cleveland, Ohio. Quote: It is a serious mistake to equate VHDL programming to software. At best it is firmware, but for the most part there isn't a good name for programming FPGA logic. In a high performance design like ours, the minute you forget that you are designing hardware and think you are writing software, you fail. VHDL Code Forest Level View Architecture Declaration VHDL Recap and Objects Variables Not limitless Operators Available Operators Picking off bits Data types, operators and conversion CASE STATEMENT 00 01 10 11 SELECTED SIGNAL ASSIGNMENT SELECT X WHEN “00”, Y WHEN “01”, Z WHEN “10”, Z WHEN “OTHERS”; * USED WHEN NO PRIORITY EQUIVALENT TO CASE STATEMENT (get code) IF STATEMENT X 0 1 Y A 0 1 OUT Z B CONDITIONAL SIGNAL ASSIGNMENT PROCESS (X, Y, Z, A, B) SENSITIVITY LIST. ANYTHING READ MUST BE HERE NOTHING HERE IS EVER ON LEFT SIDE OF ASSIGNMENT – Everything on Right hand side of assignment is read IF B = ‘1’ THEN OUT <= Z ELSIF A = ‘1’ OUT <= Y ELSE OUT <= X END IF END PROCESS * PRIORITY EXISTS Assignment Operators <= Used to assign a value to a SIGNAL a <= ‘1’; := Used to assign an value to a VARIABLE, CONSTANT, or GENERIC. Used also for establishing initial values constant N: integer:=18; => Used to assign values to individual vector elements or with OTHERS display_out : display_controller port map( clk => clk, reset => reset, • q_reg <= (others=>'0'); RULES DON’T USE PROCESS IF DON’T HAVE TO – Simple, concurrent and selected signal assignments can be done outside of a process. Danger of using a process is you might get a inferred latch (unwanted clock cycle) MULTIPLE ASSIGNMENTS TO SAME SIGNAL, LAST ONE HOLDS FOR EVERY OUTPUT SIGNAL THAT CAN BE ASSIGNED, ALL POSSIBLE CONDITIONS MUST BE ADDRESSED– Always assign default values at the top of the block before case and if statements ALL INPUT SIGNALS READ MUST BE IN THE SENSITIVITY LIST FOR COMBINATIONAL LOGIC FOR SEQUENTIAL USE CLK/RESET I wish to help all of you to begin teaching FPGAs Start the Learning The key from this workshop is to learn what you need to know to successfully teach with FPGAs Create a 2 input AND gate! Create the VHDL, Testbench, UCF and download it Get Started! Steps: 1. Start ISE 2. New Source – VHDL Module 3. Use Wizard to do I/O 4. New Source – Create UCF for pin assignment 5. New Source – VHDL Testbench 6. Simulate 7. Program FPGA Things to discuss before the labs Slow clock Using it, changing it for simulations Debouncing Alex material ISE 7 vs 14 Labs we will cover Spin up Counter Testbench FSM Seq Det IP Cores Lab 6 - Counters Download ISE 14.1 version of Lab 6 from http://cosmiac.org/Projects_FPGA.html Create New Project Add Source Files: counter.vhd display_controller.vhd counter_TB.vhd counter4.ucf Download and Review FPGA Reference Manual Change clk pin assignment as needed Change UCF pin assignments as needed Review vhd and ucf code Review Testbench Counters - Eloquent Example Counter Counter – cont. (2) Counter – cont. (3) Display_Controller Display_Controller – cont. (2) Display_Controller – cont. (3) UCF – Spartan 6 pins We are using a Nexys 2, Spartan-3 for this class. We will need to change the pin assignments using the diagram. Labs we will cover Spin up Counter Testbench FSM Seq Det IP Cores Autogenerated Test Benches Build a module test a module, …., build a system of modules and test the system Excellent job for technician or junior engineer Creating the framework of the test bench is easy and painless Need to have directory of files and test benches and need to be able to quickly pick them out and mate the source file to its test file Counter Test Bench - 1 Counter Test Bench - 2 Counter Test Bench - 3 Counter Test Bench - 4 Labs we will cover Spin up Counter Testbench FSM Seq Det IP Cores LAB 10 Finite State Machine (FSM) Ui Luu Glendale Community College Bassam Matar Chandler-Gilbert Community College Moore vs. Mealy State Machines Learning Objectives Create a top-level HDL structure Write VHDL code to describe a Finite State Machine Apply VHDL codes previously developed in workshop #1 (source codes are provided in this lab template): (TIMER_DISPLAY.vhd, MEM16.vhd, SECURITY.ucf module) for timer display Implement INDICATORS.vhd (to provide visual feedback for NEXYS2 on board switches & buttons) Verify system operations using NEXYS2 evaluation board Security Monitor System I/O ARM INDICATOR ARM FRONT_DOOR REAR_DOOR FRONT_DOOR INDICATOR SECURITY REAR_DOOR INDICATOR WINDOW INDICATOR WINDOW SIREN Figure 1. Security System I/O Security System State Diagram ARM = ‘0’ DISARMED ARM = ‘1’ SIREN = ‘0’ ARM = ‘0’ ARM = ‘0’ ALARM SIREN = ‘1’ ARMED ARM = ‘0’ SIREN = ‘0’ SENSORS /= “000” COUNT_DONE = ‘1’ WAIT_DELAY (7 s) SIREN = ‘0’ Figure 2. SECURITY SYSTEM STATE DIAGRAM Security State Machine / System Block Diagram TIMER_DISPLAY CLK CLK 7-Segment LEDs ANODE_CONTROL(3:0) ANODE_CONTROL(3:0) ADDR(3:0) RUN_TIMER ADDR_BUS(3:0) ADDR(3:0) DATA(7:0) CATHODE(7:0) CLK_DIV MEM16 CLK_DIV_SIG FSM CLK RUN_TIMER CLK_DIV RUN_SIG ARM (SW0) ARM FRONT_DOOR (Button 3) FRONT_DOOR REAR_DOOR (Button 2) REAR_DOOR WINDOW (Button 1) SIREN SIREN LED 7 Always start with a block diagram or dry erase board before you start to write your VHDL WINDOW INDICATORS ARM FRONT_DOOR REAR_DOOR WINDOW ARM_SIG FRONT_DOOR_SIG REAR_DOOR_SIG WINDOW_SIG ARM_IND FRONT_DOOR_IND REAR_DOOR_IND LED 0 LED3 LED2 WINDOW_IND LED1 7/25/2011-REVA Ui Luu TIMER_DISPLAY Module TIMER_DISPLAY module objectives: Provides 1 second CLK_DIV signal to Finite State Machine Provides control signals to display timer using NEXYS2 onboard 7-segment LED display CLK_DIV signal Functional Requirement: Provides 1 second CLK_DIV signal to Finite State Machine Code Implementation: process (CLK,REG) begin if rising_edge(CLK) then REG <= REG + 1; end if; CLK_DIV_INT<='0'; if REG = X"2FAF080" then -- For 1 Hz use X"2FAF080" = 50,000,000 (Decimal) -- 50 MHz / 50,000,000 = 1 Hz CLK_DIV_INT<='1'; REG<=X"0000000"; --would be cleaner with “others” end if; end process; TIMER_DISPLAY Functional Description When RUN_TIMER (from FSM) = 1: Timer counts up at 1 second rate Display the timer count at 7-Segment LED When RUN_TIMER = 0: Timer resets to 0 TIMER_DISPLAY Implementation (Note: This implementation was covered in Workshop May,2011) process (CLK,CLK_DIV_INT,RUN_TIMER) begin if RUN_TIMER = '0' then Q_INT <= (others => '0'); elsif rising_edge(CLK) then if (CLK_DIV_INT='1') then -- Note: CLK_DIV_INT provides 1-second clock Q_INT <= Q_INT + '1'; end if; end if; end process; -- Outputs: ADDR(3 downto 0) <= Q_INT (3 downto 0); ANODE_CONTROL <= "1110"; -- Enable 1st digit only, active Low CLK_DIV <=CLK_DIV_INT; Review NEXYS2 I/O Device (Ref. Nexys2_m.pdf) Note the difference entity MEM16 is Port ( ADDR : in STD_LOGIC_VECTOR (3 downto 0); DATA : out STD_LOGIC_VECTOR (7 downto 0)); end MEM16; architecture Behavioral of MEM16 is type ROM_ARRAY is array (0 to 15) of std_logic_vector(7 downto 0); constant MY_ROM :ROM_ARRAY :=( -- Cathode Control for 7-SEGMENT LED Digit (0-F): 0 => X"03", --0 note: Cathode control is active Low 1 => X"9F", --1 2 => X"25", --2 3 => X"0D", --3 4 => X"99", --4 4 = 10011001 5 => X"49", --5 6 => X"41", --6 7 => X"1F", --7 8 => X"01", --8 9 => X"09", --9 10 => X"11", --A 11 => X"C1", --B 12 => X"63", --C 13 => X"85", --D 14 => X"61", --E 15 => X"71" --F ); begin DATA <= MY_ROM(conv_integer(ADDR)); end Behavioral; MEM16.vhd a=1 b=0 f=0 g=0 e=1 c=0 d=1 DP = 1 FSM / IO port assignments (Reference: System Block Diagram) entity FSM is Port ( CLK : in STD_LOGIC; CLK_DIV:in STD_LOGIC; ARM : in STD_LOGIC; FRONT_DOOR : in STD_LOGIC; REAR_DOOR : in STD_LOGIC; WINDOW : in STD_LOGIC; RUN_TIMER:out STD_LOGIC; SIREN : out STD_LOGIC); end FSM; Type & Signal names Declarations type SECURITY_STATE is (ARMED,DISARMED,WAIT_DELAY, ALARM); signal CURR_STATE,NEXT_STATE: SECURITY_STATE; signal START_COUNT,COUNT_DONE: std_logic; signal SENSORS:std_logic_vector (2 downto 0); --combine inputs signal TIMER_CNTR: std_logic_vector (2 downto 0) := (others => '0'); FSM / Reading Sensors & SYNC Process SENSORS <= FRONT_DOOR & REAR_DOOR & WINDOW; SYNC: process (CLK,ARM) begin if ARM = '0' then CURR_STATE <= DISARMED; elsif rising_edge (CLK) then CURR_STATE <= NEXT_STATE; end if; end process SYNC; & = concatenation New State each clock cycle STATE_MACHINE: process (CURR_STATE,SENSORS,ARM,COUNT_DONE) begin START_COUNT <= '0'; -- establish default case (CURR_STATE) is when DISARMED => if ARM = '1' then NEXT_STATE <= ARMED; else NEXT_STATE <= DISARMED; end if; -- Output: SIREN <= '0'; RUN_TIMER <= '0'; when ARMED => if (SENSORS /= "000") then NEXT_STATE <= WAIT_DELAY; else NEXT_STATE <= ARMED; end if; -- Output: SIREN <= '0'; RUN_TIMER <= '0'; when WAIT_DELAY => START_COUNT <= '1'; if (COUNT_DONE = '1') then NEXT_STATE <= ALARM; elsif (ARM ='0') then NEXT_STATE <= DISARMED; else NEXT_STATE <= WAIT_DELAY; end if; -- Output: SIREN <= '0'; RUN_TIMER <= '1'; when ALARM => if (ARM = '0') then NEXT_STATE <= DISARMED; else NEXT_STATE <= ALARM; end if; -- Output: SIREN <= '1'; RUN_TIMER <= '0'; end case; end process STATE_MACHINE; Implement Security System State Diagram (Figure 2) Four States DELAY_TIMER Process DELAY_TIMER: process(CLK_DIV,CURR_STATE,START_COUNT,TIMER_CNTR) begin COUNT_DONE <= '0'; -- default value if (rising_edge (CLK_DIV) and (START_COUNT = '1')) then TIMER_CNTR <= TIMER_CNTR + 1; end if; -- *** Note: START_COUNT is set to 1 by the STATE_MACHINE when CURR_STATE = WAIT_DELAY if (CURR_STATE/=WAIT_DELAY) then TIMER_CNTR <= "000"; end if; if (TIMER_CNTR = "111") then COUNT_DONE <= '1'; end if; end process DELAY_TIMER; -- Note: /= means NOT equal to -- Note: this timer times out at 7 seconds just for convenience INDICATORS.vhd entity INDICATORS is Port ( ARM : in STD_LOGIC; FRONT_DOOR : in STD_LOGIC; REAR_DOOR : in STD_LOGIC; WINDOW : in STD_LOGIC; ARM_SIG : out STD_LOGIC; FRONT_DOOR_SIG : out STD_LOGIC; REAR_DOOR_SIG : out STD_LOGIC; WINDOW_SIG : out STD_LOGIC); end INDICATORS; architecture Behavioral of INDICATORS is begin ARM_SIG<=ARM; FRONT_DOOR_SIG <= FRONT_DOOR; REAR_DOOR_SIG <= REAR_DOOR; WINDOW_SIG <= WINDOW; end Behavioral; (provides visual feedback for NEXYS2 on board switches and buttons) # SECURITY.ucf # 7/6/2011: Operation verified with NEXYS2-1200 NET "CLK" LOC = B8; NET "ARM" LOC = G18; # Switch 0 NET "FRONT_DOOR" LOC = H13; # Button 3 NET "REAR_DOOR" LOC = E18; # Button 2 NET "WINDOW" LOC = D18; # Button 1 SECURITY.ucf (I/O assignments for NEXYS2-1200) NET "ARM_IND" LOC = J14; #LED 0 NET "FRONT_DOOR_IND" LOC = K14; #LED3 NET "REAR_DOOR_IND" LOC = K15; #LED2 NET "WINDOW_IND" LOC = J15; #LED1 NET "CATHODE" LOC = C17; #DP NET "CATHODE" LOC = H14; #CG NET "CATHODE" LOC = J17; #CF NET "CATHODE" LOC = G14; #CE NET "CATHODE" LOC = D16; #CD NET "CATHODE" LOC = D17; #CC NET "CATHODE" LOC = F18; #CB NET "CATHODE" LOC = L18; #CA NET "ANODE_CONTROL" LOC = F17; NET "ANODE_CONTROL" LOC = H17; NET "ANODE_CONTROL" LOC = C18; NET "ANODE_CONTROL" LOC = F15; NET "SIREN" LOC = P4; #LED7 P4 for NEXYS2-1200 (R4 for NEXYS2-500 series) Hands On Practice (Work in Team of 2) Download / Copy “VHDL-SecurityStateMachine-Starter(NEXYS2-1200)” project folder to your desktop Follow Lab 10 Finite State Machine (FSM) Instructions Verify the Security State Machine operates as prescribed Demonstrate to your lab coordinator Sample Solution For reference, Sample solution is available at project Folder “VHDL-SecurityStateMachineSampleSolution(NEXYS2-1200)” Labs we will cover Spin up Counter Testbench FSM Seq Det IP Cores Sequence Detectors Sequence Detectors Practical applications Facial recognition Searching for correct patterns DSP Labs we will cover Spin up Counter Testbench FSM Seq Det IP Cores IP Cores What are Cores? CoreGen Wizard IP Cores IP Cores Datasheets IP Cores Lessons Learned Don’t assume you know the way the core will work Build a project with only the core in it and test it alone until you are sure you know how it works If you can’t see any of the cores: Setting environment variable XIL_CG_LOAD_ALL_FAMILIES=true Especially for 14.4. Other “STUFF” Obtaining, licensing and service contract with Xilinx If you decide to go with Xilinx, we can help you the most (with currently available resources) Register with XUP Get software Pay annual fee Put one person in charge Synthesizing Designs Generate a netlist file using XST (Xilinx Synthesis Technology) 1 Highlight HDL Sources 2 Synthesis Processes and Analysis • Access report • View Schematics (RTL or Technology) • Check syntax • Generate Post-Synthesis Simulation Model Double-click to Synthesize Implementation Consists of three phases Translate: Merge multiple design files into a single netlist Map: Group logical symbols from the netlist (gates) into physical components (slices and IOBs) Place & Route: Place components onto the chip, connect the components, and extract timing data into reports Access Xilinx reports and tools at each phase Timing Analyzer, Floorplanner, FPGA Editor, XPower Netlist Generated From Synthesis . . . Implement Translate Map Place & Route . . . ... Device Implementation Place & Route Design Flow Specification Gates of the design ... libraries HDL Schematic Capture Synthesis netlist ... are placed ... Verification Simulation 0100 1110 1100 1111 test vectors Implementation Translate Fitting/ Place & Route ... and routed Simulations 1 Highlight source file Configuring FPGAs Configure FPGAs from computer Use iMPACT to download bitstream from 2 computer to FPGA via Xilinx download cable (ie. Platform USB) Double-click to generate .bit Configure FPGAs from External Memory Xilinx Platform Flash Use iMPACT to generate PROM file and download to PROM using Xilinx download cable Generic Parallel PROM Use iMPACT (or in our case Adept) to generate PROM file - no support for programming Compact Flash (Xilinx System ACE required) Use iMPACT to generate SysACE file - no support for programming 3 Double-click to invoke iMPACT programming tools JTAG – IEEE Standard Six Signals TMS TCK TDI TDO Pwr Gnd Demo Impact Webpack This is the really great benefit to students. Xilinx makes a free version of their ISE software. This means that students can do entire projects at home and only come to the lab to demo. http://www.xilinx.com/ise/logic_design_prod/webpack .htm Altera has a similar product Webpack vs Full Version Webpack Plan Ahead In the near future Xilinx ISE will transition from the traditional Project Navigator to Plan Ahead. Easier integration of various design types PlanAhead Very similar to project navigator EDK Very similar to project navigator Default Locations for SW When you are setting up the software, regardless of if it is at the lab or at home, only install the software at the default locations. Licensing Node Lock (Ethernet versus Hard Drive Serial Number) Server Licensing Student versus Lab Digilent (cont.) Clint’s boards Educational Materials Available Clint’s web site www.eecs.wsu.edu/~ee214 Digilent website www.digilentinc.com Our XUP site www.ece.unm.edu/vhdl XUP site www.cosmiac.org Quick start tutorials – launch within ISE What we are developing! Educational Materials Available http://www.digilentinc.com/classroom/realdigital/ Donated SW and HW Software Register with XUP Mention working with us Don’t chase releases Hardware 10 boards Beginners and Advanced Workshops We offer a series of free two-day workshops for instructors and professors to allow them to be able to learn the basics of establishing FPGA programs at their schools Coming in the Fall of 2012 – Beginners Microcontroller workshops! Collaboration We do collaborations very well ATE proposals due October 2013 Help with Writing Proposals www.teachingtechnicians.org Hi Craig, By cc of this message, I am asking Charlotte Forrest (Mentor-Connect Project Manager) to provide you with information that can be shared at your next ATE workshop. Thanks so much for asking! We will start work with a new cohort of potential grantees in fall 2013. We are currently working with a cohort of 20 colleges that were selected in fall 2012. The cycle starts with an orientation webinar in September and is followed by an application process. Those selected receive considerable help in preparing a successful proposal and are paired with an experience ATE mentor for all of the months leading up to their proposal submission. The program serves those who have not previously received NSF ATE funding that was awarded directly to their institution within the past 10 years. If they have been a partner on a grant awarded to another institution, they are eligible. If their institution is a branch of a larger institution but there is a chief academic officer for their branch campus, they are eligible even if another branch of the organization has been a grantee (for example, the Ivy Tech system in Indiana where college locations within the system have their own administration). Also, this opportunity is for associate degree granting institutions (primarily two-year technical and community colleges). Again, many thanks for contacting me and for helping spread the word about this opportunity. Elaine Deploying Curriculum Website: http://cosmiac.org/FPGA.html Conclusions Painful survey We need your help in statistics. We will be contacting you!