```Design
Methodologies
Digital Integrated Circuits
Design Methodologies
The Design Problem
Source: sematech97
A growing gap between design complexity and design productivity
Digital Integrated Circuits
Design Methodologies
Design Methodology
• Design process traverses iteratively between three abstractions:
behavior, structure, and geometry
• More and more automation for each of these steps
Digital Integrated Circuits
Design Methodologies
Design Analysis and Verification



Accounts for largest fraction of design time
More efficient when done at higher levels of
abstraction - selection of correct analysis
level can account for multiple orders of
magnitude in verification time
Two major approaches:
» Simulation
» Verification
Digital Integrated Circuits
Design Methodologies
Digital Data treated as Analog Signal
VD D
Sp
Vin
Vou t
5.0
G n ,p
In
D n, p
Ou t
V o ut (V)
Bp
3.0
tpHL
1.0
Bn
Sn
–1.0
0
0. 5
1
1.5
2
t (nsec)
Circuit Simulation
Both Time and Data treated as Analog Quantities
Also complicated by presence of non-linear elements
(relaxed in timing simulation)
Digital Integrated Circuits
Design Methodologies
Representing Data as Discrete Entity
V
0
1
VDD
0
VM
Rp
t1
t
t2
CL
Discretizing the data using
switching threshold
Rn
The linear switch model
of the inverter
Digital Integrated Circuits
Design Methodologies
Circuit versus Switch-Level Simulation
5 .0
Circuit
CI N
O U T [2]
3 .0
O U T [3 ]
1 .0
–1 .0
0
5
10
15
20
Switch
tim e ( n sec)
Digital Integrated Circuits
Design Methodologies
Structural Description of Accumulator
ent it y accu m ul ato r i s
po rt ( -- def in it io n of in pu t an d o ut pu t ter mi na ls
DI: in b it _v ecto r(15 do wn to 0 ) -- a vecto r of 16 bi t w id e
DO : i no ut b it _v ecto r(15 do wn to 0 );
C LK : i n bi t
);
end accum u lat or;
archi tect ure s tru ctu re o f accum u lat or is
com p on ent reg -- def in it io n of regi st er po rt s
po rt (
DI : i n b it _v ecto r(15 d ow nt o 0 );
DO : ou t b it _v ecto r(15 d ow nt o 0 );
C LK : in bi t
);
end com p on ent ;
com p on ent add -- d efi ni ti on o f a dd er po rt s
po rt (
IN0 : in bi t_ vect or(1 5 do wn to 0);
IN1 : in bi t_ vect or(1 5 do wn to 0);
OU T0 : ou t b it _v ecto r(15 d ow nt o 0 )
);
end com p on ent ;
-- def in it io n of accu mu la to r st ru ctu re
si gn al X : bi t_ vect or(1 5 do wn to 0);
beg in
po rt m ap (D I, D O, X); -- d efi nes po rt co nn ect ivi ty
reg1 : reg
po rt m ap (X , D O, C LK );
end st ruct ure;
Digital Integrated Circuits
Design defined as composition of
Data represented as {0,1,Z}
Time discretized and progresses with
unit steps
Description language: VHDL
Other options: schematics, Verilog
Design Methodologies
Behavioral Description of Accumulator
ent it y accu m ul ato r i s
po rt (
DI : i n i nt eger;
DO : in ou t i nt eger := 0 ;
C LK : in bi t
);
end accum u lat or;
archi tect ure b ehav io r o f accum u lat or is
beg in
pro cess (C LK )
vari abl e X : i nt eger := 0 ; -- in ter med ia te var ia bl e
beg in
if C L K = '1' t hen
X < = DO + D 1;
DO < = X ;
end if;
end pro cess ;
end beh avi or;
Digital Integrated Circuits
Design described as set of input-output
relations, regardless of chosen
implementation
Data described at higher abstraction
level (“integer”)
Design Methodologies
Behavioral simulation of accumulator
Discrete time
Integer data
(Synopsys Waves display tool)
Digital Integrated Circuits
Design Methodologies
Timing Verification
Critical path
Enumerates and rank
orders critical timing paths
No simulation needed!
(Synopsys-Epic Pathmill)
Digital Integrated Circuits
Design Methodologies
Issues in Timing Verification
In
M UX
Out
False Timing Paths
Digital Integrated Circuits
Design Methodologies
bypass
Implementation Methodologies
D igital C ircu it Im p lem en tation A p p roach es
S em i-cu stom
C u stom
C ell-B ased
S tandard C ells
M acro C ells
C om piled C ells
Digital Integrated Circuits
Design Methodologies
A rray-B ased
P re-diffused
P re-w ired
(G ate A rrays)
(F P G A )
Custom Design –
Layout Editor
Magic Layout Editor
(UC Berkeley)
Digital Integrated Circuits
Design Methodologies
Symbolic Layout
V DD
3
O ut
In
1
• Dimensionless layout entities
• Only topology is important
• Final layout generated by
“compaction” program
GND
Stick diagram of inverter
Digital Integrated Circuits
Design Methodologies
Cell-based Design (or standard cells)
L ogic C ell
R ow s o f C ells
F eedthrough C ell
Digital Integrated Circuits
R outing
C hannel
F unctional
M odule
(R A M ,
m ultiplier,  )
Design Methodologies
Routing channel
requirements are
reduced by presence
of more interconnect
layers
Standard Cell — Example
[Brodersen92]
Digital Integrated Circuits
Design Methodologies
Standard Cell - Example
3-input NAND cell
(from Mississippi State Library)
characterized for fanout of 4 and
for three different technologies
Digital Integrated Circuits
Design Methodologies
Automatic Cell Generation
Random-logic layout
generated by CLEO
cell compiler (Digital)
Digital Integrated Circuits
Design Methodologies
Module Generators —
Compiled Datapath
buffer
reg1
reg0
bus2
m ux
bus0
bus1
routing area
feed-through
bit-slice
Digital Integrated Circuits
Design Methodologies
Macrocell Design Methodology
Macrocell
Interconnect Bus
Floorplan:
Defines overall
topology of design,
relative placement of
modules, and global
routes of busses,
supplies, and clocks
Digital Integrated Circuits
Routing Channel
Design Methodologies
Macrocell-Based Design
Example
SRAM
SRAM
Data paths
Standard cells
Video-encoder chip
[Brodersen92]
Digital Integrated Circuits
Design Methodologies
Gate Array — Sea-of-gates
polysilicon
VD D
row s of
uncom m itted
cells
m etal
possible
conta ct
GN D
In 1
In 2
In 3
Uncommited
Cell
In4
routing
channel
Committed
Cell
(4-input NOR)
O ut
Digital Integrated Circuits
Design Methodologies
Sea-of-gate Primitive Cells
Oxide-isolation
PMOS
PMOS
NMOS
NMOS
NMOS
Using oxide-isolation
Digital Integrated Circuits
Using gate-isolation
Design Methodologies
Sea-of-gates
Random Logic
Memory
Subsystem
LSI Logic LEA300K
(0.6 mm CMOS)
Digital Integrated Circuits
Design Methodologies
Prewired Arrays
Categories of prewired arrays (or fieldprogrammable devices):
 Fuse-based (program-once)
 Non-volatile EPROM based
 RAM based
Digital Integrated Circuits
Design Methodologies
Programmable Logic Devices
PLA
Digital Integrated Circuits
PROM
Design Methodologies
PAL
EPLD Block Diagram
Macrocell
Primary inputs
Courtesy Altera Corp.
Digital Integrated Circuits
Design Methodologies
Field-Programmable Gate Arrays
Fuse-based
I/O Buffers
Program/Test/Diagnostics
Vertical routes
I/O Buffers
I/O Buffers
Standard-cell like
floorplan
Rows of logic modules
Routing channels
I/O Buffers
Digital Integrated Circuits
Design Methodologies
Interconnect
Prog ram med in terconn ectio n
Inpu t/ou tpu t pin
Cell
Antifuse
Horizon tal
tra cks
Vertica l tracks
Digital Integrated Circuits
Programming interconnect using anti-fuses
Design Methodologies
Field-Programmable Gate Arrays
RAM-based
CLB
C LB
switching m atrix
Hor izontal
routing
channel
Inter connect point
C LB
CL B
Ve rtical r outing channel
Digital Integrated Circuits
Design Methodologies
RAM-based FPGA
Basic Cell (CLB)
Combinationa l logic
Sto ra ge eleme nts
R
A
B /Q1/Q 2
D in
An y fun ction of up t o
4 var iab le s
C/Q 1/Q 2
R
F
F
D Q1
G
F
CE
D
A
B /Q1/Q 2
An y fun ction of u p t o
4 var iable s
R
G
F
C/Q 1/Q 2
G
D
E
D Q2
CE
G
Clock
CE
Courtesy of Xilinx
Digital Integrated Circuits
Design Methodologies
RAM-based FPGA
Xilinx XC4025
Digital Integrated Circuits
Design Methodologies
S truc tural V iew
B eh avio ral View
Architectural Level
Logic Level
Circuit Level
state
a
b
0
(i: 1..16) ::
–1
sum = sum*z +
–1
coeff[i]*In*z
2
1
tp
Logic
Architecture
Synthesis
4
fsm
c
*
Digital Integrated Circuits
Circuit
Synthesis
Synthesis
a
b
mem
x
c
3
x
D
Design Methodologies
a
2
b
2
1
c
Design
for Test
Digital Integrated Circuits
Design Methodologies
Validation and Test of
Manufactured Circuits
Goals of Design-for-Test (DFT)
Make testing of manufactured part swift and
comprehensive
DFT Mantra
Provide controllability and observability
Components of DFT strategy
• Provide circuitry to enable test
• Provide test patterns that guarantee reasonable
coverage
Digital Integrated Circuits
Design Methodologies
Test Classification

Diagnostic test
» used in chip/board debugging
» defect localization

“go/no go” or production test
» Used in chip production

Parametric test
» x e [v,i] versus x e [0,1]
» check parameters such as NM, Vt, tp, T
Digital Integrated Circuits
Design Methodologies
Design for Testability
N inputs
N inputs
C om binational
K outputs
C om binational
K outputs
L ogic
L ogic
M odule
M odule
M state regs
(a) C om binational function
(b) S equential engine
2 N patte rn s
2 N + M patte rn s
Exhaustive test is impossible or unpractical
Digital Integrated Circuits
Design Methodologies
Problem:
Controllability/Observability

Combinational Circuits:
controllable and observable - relatively easy to
determine test patterns

Sequential Circuits: State!
Turn into combinational circuits or use self-test

Memory: requires complex patterns
Use self-test
Digital Integrated Circuits
Design Methodologies
Test Approaches
 Scan-based Test
 Self-Test
Problem is getting harder

» increasing complexity and heterogeneous
combination of modules in system-on-a-chip.
» Advanced packaging and assembly techniques
extend problem to the board level
Digital Integrated Circuits
Design Methodologies
Generating and Validating
Test-Vectors

Automatic test-pattern generation (ATPG)
» for given fault, determine excitation vector (called test vector)
that will propagate error to primary (observable) output
» majority of available tools: combinational networks only
» sequential ATPG available from academic research

Fault simulation
» determines test coverage of proposed test-vector set
» simulates correct network in parallel with faulty networks

Both require adequate models of faults in
CMOS integrated circuits
Digital Integrated Circuits
Design Methodologies
Fault Models
Most Popular - “Stuck - at” model
sa 0
(o u tp u t)
0
1
sa 1
(in p u t)
Covers almost all (other)
occurring faults, such as
opens and shorts.
Z
x1


x2
Digital Integrated Circuits

Design Methodologies
x3
,  : x1 sa1
 : x1 sa0 or
x2 sa0
 : Z sa1
Problem with stuck-at model:
CMOS open fault
x1
x2
Z
x1
x2
Sequential effect
Needs two vectors to ensure detection!
Other options: use stuck-open or stuck-short models
This requires fault-simulation and analysis at the switch or
transistor level - Very expensive!
Digital Integrated Circuits
Design Methodologies
Problem with stuck-at model:
CMOS short fault
C
D
A
B
‘0 ’
Causes short circuit between
Vdd and GND for A=C=0, B=1
‘0 ’
‘0 ’
A
C
‘1 ’
B
D
Digital Integrated Circuits
Possible approach:
Supply Current Measurement (IDDQ)
but: not applicable for gigascale
integration
Design Methodologies
Path Sensitization
Goals: Determine input pattern that makes a fault
controllable (triggers the fault, and makes its impact
visible at the output nodes)
Fault enabling
1
1
1
1
Fault propagation
0
sa0
1
O ut
1
0
Techniques Used: D-algorithm, Podem
Digital Integrated Circuits
Design Methodologies
data
data
test
Memory
Memory
select
Processor
Processor
I/O bus
I/O bus
Inserting multiplexer improves testability
Digital Integrated Circuits
Design Methodologies
Scan-based Test
ScanIn
Digital Integrated Circuits
Combinational
Logic
A
R egister
R egister
In
ScanOut
Design Methodologies
Combinational
Out
Logic
B
Polarity-Hold SRL
(Shift-Register Latch)
S yste m D ata
D
Q
S yste m C lock C
S can D a ta
S hift A C lock
SI
L1
Q
A
SO
S hift B C lock
B
L2
SO
Introduced at IBM and set as company policy
Digital Integrated Circuits
Design Methodologies
Scan-Path Register
OUT
SCAN
PHI2
PHI1
SCANIN
SCANOUT
IN
Digital Integrated Circuits
KEEP
Design Methodologies
Scan-based Test —Operation
In 0
Test
In1
Tes t
Tes t
In 2
Test
Test
In 3
Tes t
Test
Tes t
ScanIn
ScanO ut
L atch
L atc h
L atch
L atch
O ut0
O ut 1
O ut 2
O ut3
Test
1
2
N cycles
scan-in
Digital Integrated Circuits
1 cycle
evaluation
Design Methodologies
N cycles
scan-out
Scan-Path Testing
A
B
REG[1]
REG[0]
REG[2]
REG[3]
SCANIN
+
REG[4]
COMPIN
COMP
REG[5]
SCANOUT
OUT
Partial-Scan can be more effective for pipelined datapaths
Digital Integrated Circuits
Design Methodologies
Boundary Scan (JTAG)
P rinted-circuit board
L ogic
Scan-out
si
so
scan path
no rm al in terco nn ect
Scan-in
P ackaged IC
Board testing becomes as problematic as chip testing
Digital Integrated Circuits
Design Methodologies
Self-test
(S ub)-C ircuit
S tim ulus G enerator
U nder
R esponse A nalyzer
Test
Test C ontroller
Rapidly becoming more important with increasing
chip-complexity and larger modules
Digital Integrated Circuits
Design Methodologies
Linear-Feedback Shift Register (LFSR)
R
R
R
S0
S1
S2
1
0
1
1
1
0
0
1
0
1
0
1
1
1
0
0
0
0
1
0
1
1
1
0
Pseudo-Random Pattern Generator
Digital Integrated Circuits
Design Methodologies
Signature Analysis
In
C ounte r
R
Counts transitions on single-bit stream
 Compression in time
Digital Integrated Circuits
Design Methodologies
BILBO
D0
B0
D1
D2
B1
ScanO ut
m ux
ScanIn
R
R
S0
Digital Integrated Circuits
R
S1
B0 B1
O peration m ode
1
1
N orm al
0
0
1
0
0
1
S can
P attern generation or
S ignature analysis
R eset
Design Methodologies
S2
BILBO Application
Digital Integrated Circuits
Combinational
Logic
B IL B O -B
In
ScanOut
B IL B O -A
ScanIn
Design Methodologies
Combinational
Out
Logic
Memory Self-Test
data - in
M em ory
data-out
S ignature
FSM
U nder Test
A nalysis
R / W control
Walking 0s, 1s
Galloping 0s, 1s
Digital Integrated Circuits
Design Methodologies
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