ACOE361 – Digital Systems Design Useful information • • • • Instructor: Lecturer K. Tatas Office hours: Mo5, Tu3, We6-8, Fri5 Prerequisites: ACOE201 (ACOE161) Teaching: 4 periods/week – 3 Lecture – 1 Lab • ECTS: 6 (6x25 = 150h) • Enrollment key: ACOE361_FALL12 Course Objectives • Introduce students to advanced topics in Digital System Design – Synchronous Sequential Circuit Design using State/ASM diagrams – Hardware Description Languages – EDA tools – ASIC/FPGA implementation technologies Course Outcomes • Understand the digital system design flow • Understand the role of EDA tools in ASIC/VLSI design • Be familiar with ASIC, PLD, FPGA technologies • Design hazard-free synchronous and asynchronous digital systems using ASM • Implement Mealy and Moore ASMs using PROMs, multiplexers, PLDs, FPLAs, FPGAs • Become fluent in VHDL • Understand Verification concepts and design testbenches Course Description • Digital Systems Design - ASMs: – – – – ASMs, Mealy and Moore machines. ASM charts. VEΜ minimization. IFL/OFL minimization and implementation. State machine implementation using PROMs and multiplexers. – Finite state machine implementation using FPLAs. – Timing. Glitch minimization techniques. – Asynchronous input systems. Asynchronous input synchronization Course Description • ASIC architectures and Implementation Options – Synthesis and EDA tools for ASIC and FPGA implementation – Semi-custom / full custom ASICs. – Gate Array, Standard Cell, Full Custom, CMOS/BI-CMOS technologies – PLDs and FPGAs. Course Description • VHDL – – – – – – – – – Top-Down Design. File organization. Entity and Architecture. Structural and Behavioural Description. VHDL Primitives. Signal Queues and Delta times. Concurrent and sequential statements. Procedures and functions. Packages and design for reuse. Course Description • Verification – Basic verification methodology – Testbenches • directed and constrained-random testing • self-checking testbenches Course Description • EDA Tools – Synthesis • VHDL Synthesis coding guidelines • Synthesis optimization options – Implementation Course Outline • Week 1: – – • Week 2: – – • Lecture 1: VHDL Lecture 2: Lab 1 Week 6: – – • Lecture 1: Test 1 Lecture 2: Design Flow Week 5: – – • Lecture 1: Synchronous Design Lecture 2: Examples Week 4: – – • Lecture 1: Sequential circuits – Examples Lecture 2: ASMs Week 3: – – • Lecture 1: Digital Revision Lecture 2: FSMs Lecture 1: VHDL Lecture 2: Lab 2 Week 7: – – Lecture 1: VHDL Lecture 2: Lab 3 •Week 8: •Lecture 1: VHDL •Lecture 2: Lab 4 •Week 9: •Lecture 1: Verification •Lecture 2: Lab 5 •Week 10: •Lecture 1: Logic Synthesis •Lecture 2: Lab 6 •Week 11: •Lecture 1: Test 2 •Lecture 2: Assignment/Group project •Week 12: •Lecture 1: Assignment/Group project review – Case study •Lecture 2: Lab 7 •Week 13: •Lecture 1: Assignment/Group project assessment •Lecture 2: Revision Course Evaluation • Final exam: 40% • Coursework: 60% – Test: 20% – Assignment/Group project: 20% – Laboratory work: 20% Textbooks and References • J. F. Wakerly, Digital Design: Principles and Practices, Prentice Hall, 2003. • V. Pedroni, The student’s guide to VHDL, Morgan Kaufmann, 1998. • M. Mano, Digital Design, Prentice Hall, 2002. • T. Floyd, Digital Fundamentals, Prentice Hall, 2002. Basic Logic Gates B uffer A AND X A OR X B A E X -O R X B A X B X = A X = AB X = A + B X = A + B A X A B X A B X A B X 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 1 1 0 1 1 1 0 0 1 0 1 1 0 1 1 1 1 1 1 1 1 1 0 Logic Function Gate Symbol Logic Expression Truth Table Basic Logic Gates with Inverted Outputs NOT A NAND X A NOR X B A E X -N O R X B A X B X = A X = A B X = A + B A X A B X A B X A B X 0 1 0 0 1 0 0 1 0 0 1 1 0 0 1 1 0 1 0 0 1 0 1 0 1 1 0 0 1 0 0 1 1 0 1 1 0 1 1 1 X = A + B Revision on MSI Devices M. Mano & C. Kime: Logic and Computer Design Fundamentals (Chapter 5) MSI Devices • Medium Scale Integration (MSI) devices are digital devices that are build using a few tens to hundreds of logic gates. • MSI devices are used as discrete devices packed in a single Integrated Circuit (IC), or as building blocks for other, more complex devices such as memory devices Examples of MSI Devices Decimal to BCD Encoder 4-to-1 Multiplexer DEC/BCD 1 2 3 4 5 6 7 8 9 0 I3 1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 0 1 I1 0 I0 1 4/1 Mux BCD to Decimal Decoder 1 1 1 1 0 0 0 0 0 1 0 1 0 1 0 1 0 BCD/DEC A0 A1 A2 A3 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 1 2 3 4 5 3 I2 1 Y3 Y2 Y1 Y0 1 2 6 7 8 9 Decoders • • • A decoder is a combinational digital circuit with a number of inputs ‘n’ and a number of outputs ‘m’, where m= 2n Only one of the outputs is enabled at a time. The output enabled is the one specified by the binary number formed at the inputs of the decoder. On the circuit below, the inputs of the decoder are connected on three switches, forming the number 5 [(101)2], thus only the lamp #5 will be ON 0 1 1 1 0 0 0 1 0 1 0 0 1 3/8 D E C . Y0 A0 A1 A2 Y1 Y2 Y3 Y4 Y5 Y6 Y7 1 2 3 4 5 6 7 2 to 4 Line Decoder: 2 -to -4 L in e D e co d e r A1 A0 Y0 Y1 Y2 Y3 Y0 = A1 A0 0 0 1 0 0 0 Y1 = A1 A Y1 0 1 0 1 0 0 Y2 = A1 A0 Y2 1 0 0 0 1 0 Y3 = A1 A 0 1 1 0 0 0 1 Logic E xpressions 2/4 D E C Y0 A1 A0 Y3 Logic S ym bol Truth Table Y0 A1 0 Y1 Y2 A0 Y3 Logic C ircuit 2 -to -4 L in e D e co d e r w ith E n a b le In p u t 2/4 D E C A1 A0 E Y0 Y1 E A1 A0 Y0 Y1 Y2 Y3 Y0 A1 0 1 X 0 X 0 0 1 0 0 0 0 0 1 0 1 0 1 0 0 Y3 1 1 0 0 0 1 0 1 1 1 0 0 0 1 Truth Table Y1 = E A1 A 0 0 Y2 Logic S ym bol Y0 = E A1 A0 Y2 = EA 1 A0 Y3 = EA 1 A Logic E xpressions 0 Y1 E Y2 A0 Y3 Logic C ircuit 3 to 8 Line Decoder: 3 -to -8 L in e D e co d e r w ith E n a b le In p u t 3/8 D E C Y0 E A1 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 0 X X X 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 A2 Y2 1 0 0 1 0 1 0 0 0 0 0 0 A1 Y3 1 0 1 0 0 0 1 0 0 0 0 0 E Y4 Y1 A2 Y1 A0 Y0 Y2 Y3 A1 1 0 1 1 0 0 0 1 0 0 0 0 Y5 1 1 0 0 0 0 0 0 1 0 0 0 Y6 1 1 0 1 0 0 0 0 0 1 0 0 Y7 1 1 1 0 0 0 0 0 0 0 1 0 1 1 1 1 0 0 0 0 0 0 0 1 Y4 Y5 A0 Y6 Y7 E Logic S ym bol Truth Table Logic C ircuit Multiplexers • A multiplexer is a device that has a number of data inputs “m”, and number of control inputs “n” and one output, such that m=2n. The output has always the same value as the data input specified by the binary number at the control inputs. • The rotary switch (selector) shown in figure (a) below, is equivalent to a 4to-1 multiplexer. • The sliding switch shown in figure (b) below, is equivalent to an 8-to-1 multiplexer. (a) 4-to-1 M ultiplexer (b) 8-to-1 M ultiplexer 1 1 1 0 1 I3 1 0 1 0 1 1 1 2 0 3 I2 I0 I1 I2 I3 I4 I5 I6 I7 1 I1 Y I0 0 4 /1 M u x 0 8 /1 M u x Internal structure of a 2-to-1 multiplexer. • The design of a 2-to-1 multiplexer is shown below. • If S=0 then the output “Y” has the same value as the input “I0” • If S=1 then the output “Y” has the same value as the input “I1” 2-to-1 M ultiplexer 2/1 M U X S I1 I0 Y I0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 1 1 0 0 1 1 1 1 0 0 1 1 1 0 0 0 1 0 1 0 I0 Y I1 S Logic S ym bol S Y I1 I0 0 I0 1 1 0 1 1 I1 1 1 1 1 Logic Function Truth Table 00 01 11 10 S Y = S I0 + S I 1 Logic E xpression 1 /2 D e c . S Y I1 Logic C ircuit 1-bit Full Adder A B Cin Cout Sum 0 0 0 0 0 0 0 1 0 1 0 1 0 0 1 0 1 1 1 0 A Sum B Cin Cout 0 8/1 Mux I0 0 I1 0 I2 1 I3 0 I4 I5 0 4/1 Mux I0 Y Cout 1 0 0 0 1 1 1 0 1 1 0 1 I6 A I1 1 I7 S2 S 1 S0 A I2 1 I3 S1 S0 1 1 0 1 0 1 1 1 1 1 Truth Table 1-Bit Full Adder using gates A 3/8 Dec. A Y0 B B Y1 C Y2 Cin A B Cin 1-Bit F.A. Cout Sum Logic Symbol En A B Y Cout B Cin Cin Y3 0 S2 S 1 S0 I0 Y4 1 I1 A S1 S0 I0 Y5 1 I2 A' I1 Y6 0 I3 A' I2 Y7 1 I4 A 0 I5 I3 4/1 Mux 0 I6 1 I7 8/1 Mux Cout Sum 1-Bit Full Adder using a decoder Y Sum Y Sum 1-Bit Full Adder using 4/1 multiplexers 1-Bit Full Adder using 8/1 multiplexers 4-bit Full Adder (Ripple-Carry Adder) • To obtain a 4-bit full adder we cascade four 1-bit full adders, by connecting the Carry Out bit of bit column M to the Carry In of the bit column M+1, as shown below. The Carry In of the Least Significant column is set to zero. A3 B3 A2 B2 A1 B1 A0 B0 0 A B C in 1-B it F.A . C o ut S um A B C in 1-B it F.A . C o ut S um A B C in 1-B it F.A . C o ut S um A B C in 1-B it F.A . C o ut S um Cout S3 S2 S1 S0 • Example: Find the bit values of the outputs {Cout,S3..S0} of the full adder shown below, if {A3..A0 = 1011} and {B3..B0 = 0111}. Magnitude Comparator X3 X2 X1 X0 X=Y Y3 Y2 Y1 Y0 The D Edge Triggered Flip Flop The D edge triggered flip flop can be obtained by connecting the J with the K inputs of a JK flip through an inverter as shown below. The D edge trigger can also be obtained by connecting the S with the R inputs of a SR edge triggered flip flop through an inverter. P o sitive E d g e D F lip F lo p D J Q N e g a tive E d g e D F lip F lo p Q D C LK Q Q K Q Q C LK K L o g ic S ym b o l D J Q C LK Q C LK Q D Q N+1 X Q 0 0 1 1 Q F u n ctio n L o g ic S ym b o l D Q C LK Q C LK D Q N+1 X Q 0 0 1 1 F u n ctio n The Toggle (T) Edge Triggered Flip Flop The T edge triggered flip flop can be obtained by connecting the J with the K inputs of a JK flip directly. When T is zero then both J and K are zero and the Q output does not change. When T is one then both J and K are one and the Q output will change to the opposite state, or toggle. Positive Edge T Flip Flop T J Q Negative Edge T Flip Flop Q T CLK T Q CLK Q Q Q K Q Q T QN+1 Function X Q 0 Q 1 Q΄ CLK K Logic Symbol J CLK Q Q T QN+1 Function X 0 Q Q 1 Q΄ Logic Symbol T Q CLK Q CLK D and T Edge Triggered Flip Flops :- Example Complete the timing diagrams for : (a) Positive Edge Triggered D Flip Flop (b) Positive Edge Triggered T Flip Flop (c) Negative Edge Triggered T Flip Flop (d) Negative Edge Triggered D Flip Flop (b) (a) CLK CLK D D Q Q (d) (c) CLK CLK T T Q Q Flip Flops with asynchronous inputs (Preset and Clear) Two extra inputs are often found on flip flops, that either clear or preset the output. These inputs are effective at any time, thus are called asynchronous. If the Clear is at logic 0 then the output is forced to 0, irrespective of the other normal inputs. If the Preset is at logic 0 then the output is forced to 1, irrespective of the other normal inputs. The preset and the clear inputs can not be 0 simultaneously. In the Preset and Clear are both 1 then the flip flop behaves according to its normal truth table. P o sitive E d g e JK F lip F lo p w ith P re se t a n d C le a r C LK PR C LR J K Q N+1 0 0 X X 0 1 X X 1 1 0 X X 0 1 1 0 0 Q 1 1 0 1 0 1 1 1 0 1 1 1 1 1 Q’ PRESET J K PR C LR Q Q C LE A R F u n ctio n JK Flip Flop With Preset and Clear:- Example Complete the timing diagrams for : (a) Positive Edge Triggered JK Flip Flop (b) Negative Edge Triggered JK Flip Flop. Assume that for both cases the Q output is initially at logic zero. (a) (b) CLK CLK J J K K CLR CLR PR PR Q Q Sequential circuit example 1 A0 2 -to -1 MUX D SET Q A1 Q CLR S C lo ck 1 Clock A0 A1 S D Q 2 3 4 5 6 7 8 9 10

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