CPE 323 Introduction
to Embedded Computer Systems:
Introduction
Instructor: Dr Aleksandar Milenkovic
Lecture Notes
CPE 323
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Syllabus
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Prerequisites
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textbook & other references
grading policy
important dates
course outline
memory organization
decoding
combinatorial and sequential logic
important for system architecture
Microcomputer Lab (EB 106)
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Introduction sessions
Lab instructor CPE/EE 421/521 Microcomputers
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CPE 323
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LAB Session
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on-line LAB manual
Access cards
Accounts
Lab Assistant: Joel Wilder
Lab sessions
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#1 - Mon: 5:30 – 7:00pm
#2 - Tues: 5:30 - 7:00pm
Backup - Tues: 7:00 – 8:30pm
Sign-up sheet - if needed
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Outline
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Embedded systems:
structure and organization
Applications
Technology Trends
Historical perspective
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Embedded Computer Systems
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Stand alone system
based on a microprocessor
An embedded system –
dedicated to a specific application
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control system/monitoring system
optimization for a single function
(system resources, extension, …)
block diagram
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inputs  processing  outputs
Number of microprocessors
in our environment?
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A Microcontroller-Based System
LCD
Adj. Vol. Regul.
RS232
RS232
controller
Analog I/O
2-axes
joystick
LEDs
Thermistor
Keypad
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Switches
mC
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Wireless Body Area Network
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Data Flow
t, states
A/D
mP
system
D/A
Input
Processing
Output
Temperature
sensor
control signals
mP
INPUT
PROCESSING
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OUTPUT
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Microcomputer Block Diagram
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Microprocessor System Architecture
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System Architecture
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System bus
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Single Board Computers (SBC)
block diagram (modules, cards)
Multibus, VME, ISA, PCI, …
Multiple masters
CPU
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Clock and CPU Control Circuits
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1 MHz - 1 GHz
power-up and reset circuits
Address Decoder
Address and Data Bus Buffers
Bus Arbitration Control
Memory management
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Microprocessor System Architecture
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Memory Module
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Virtual memory / Physical memory
ROM, RAM, video memory
static/dynamic
Peripheral Module
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serial interface
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parallel interface
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RS232 (CRT, mouse), USB, Firewire (IEEE 1394)
printer interface
timer
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time/frequency measurement
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Microprocessor System Architecture
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PC architecture
CPU
Memory
PCI
ISA
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Von Neumann Architecture
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Processing Elements
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Read/Write Memory
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sequential execution
linear array of fixed size cells
Data and instruction store
I/O unit
Address/Data/Control bus
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Von Neumann Architecture
Memory
Von Neumann Architecture
W bits
0
PE
Read/Write
Memory
1
address
control
data
2
(Processing Element)
Control Unit
ALU
3
I/O
(peripherals)
N
log2N
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Von Neumann vs. Harvard
Von Neumann Architecture
Read/Write
Memory
address
data
PE
(Processing Element)
Harvard Architecture
Program
Memory
Data
Memory
address
data
address
PE
(Processing Element)
data
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Block Diagram of a Personal Computer
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A Typical Small Embedded System –
Digital Thermometer
Todd D. Morton
Embedded Microcontrollers
Copyright ©2001 by Prentice-Hall Inc.
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A Microcontroller-Based System
Todd D. Morton
Embedded Microcontrollers
Copyright ©2001 by Prentice-Hall Inc.
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Computing History
Eniac, 1946
PlayStation Portable (PSP)
(first stored-program computer)
Occupied 50x30 feet room,
weighted 30 tonnes,
contained 18000 electronic valves,
consumed 25KW of electrical power;
capable to perform 100K calc. per second
Approx. 170 mm (L) x 74 mm (W) x 23 mm (D)
Weight: Approx. 260 g (including battery)
CPU: PSP CPU (clock frequency 1~333MHz)
Main Memory: 32MB
Embedded DRAM: 4MB
Profile: PSP Game, UMD Audio, UMD Video
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Understanding computers ….
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User perspective
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Applications: What do we do with them?
Price: How much do they cost?
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To purchase and to operate
Convenience: How difficult is to use them?
Designer perspective
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Size: How large are they? (UP)
Speed: How many operations …? (UP)
Power: What is energy consumed? (UP)
Complexity: How complex are they to build?
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Engineering Computers
Market
Implementation
Complexity
Evaluate Existing
Systems for
Bottlenecks
Applications
Benchmarks
Technology
Trends
Implement Next
Generation System
Simulate New
Designs and
Organizations
Workloads
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Intel: First 30+ Years
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Intel 4004
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November 15, 1971
4-bit ALU, 108 KHz, 2,300 transistors,
10-micron technology
 Intel Pentium 4
 August 27, 2001
 32-bit architecture, 1.4
GHz (now 3.08), 42M
transistors (now 55+M),
0.18-micron technology
(now 0.09)
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Technology Directions: SIA Roadmap
Year
F e a tu re size (n m )
2
L o g ic tra n s/cm
C o st/tra n s (m c)
# p a d s/ch ip
C lo ck (M H z)
2
C h ip size (m m )
1999 2002 2005 2008 2011 2014
180
130
6 .2 M 1 8 M
1 .7 3 5 .5 8 0
1867 2553
1250 2100
340
430
100
39M
.2 5 5
3492
3500
520
70
50
35
84M 180M 390M
.1 1 0 .0 4 9
.0 2 2
4776 6532 8935
6000 10000 16900
620
750
900
W irin g le ve ls
6 -7
7
7 -8
8 -9
9
10
P o w e r su p p ly (V )
1 .8
1 .5
1 .2
0 .9
0 .6
0 .5
H ig h -p e rf p o w (W )
90
130
160
170
175
183
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Trends & Challenges
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Processor/memory discrepancy
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Microprocessor execution
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Fetch > Decode > Execute
System on a chip - Microcontroller
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Memory hierarchy
On-chip/off-chip memory
Cost, smaller PCB, reliability, power.
Applications
Evolution
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Microprocessor
Microprocessor-on-a-chip
System-on-a-chip
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Distributed-system-on-a-chip
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More on Challenges
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Scalability
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Availability
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billions of small devices
performance
hardware changes
system upgrade
failures
code enhancements
Fault tolerance
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Performance Trends
Year Proc.
1969 4004
1970’s 808x
1982 286
1985 386
1989 486
1993 Pentium
1996 P II
1999 P III
2000 P 4
MIPS
0.06
0.64
1
5
20
100
250
500
1500
1600
1400
1200
1000
800
600
400
200
0
286
386
486 Pentium P II
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P III
P 4
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Performance Trends
P e r fo rm a n ce
100
Supercomputers
10
Mainframes
Microprocessors
Minicomputers
1
0.1
1965
1970
1975
1980
1985
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1990
1995
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Clock Frequency Growth Rate
P4
C lock rate (M H z)
1,000
100

10
i8086



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



R10000















 Pentium100
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




 
 





 





i80386

i80286



i8080
1


 i8008
i4004
0.1
1970
1975
1980
1985
1990
1995
2000
2005
• 30% per year
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Transistor Count Growth Rate
100,000,000

Tr a nsisto rs
10,000,000
1,000,000
i80286
100,000






 
 R10000




  Pentium












 






P4
i80386
  R3000
 R2000
 i8086
10,000


i8080

 i8008
i4004
1,000
1970
1975
1980
1985
1990
1995
2000
2005
Moore’s Law
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General Technology Trends
•
•
•
•
Microprocessor performance increases 50%-100% per year
Transistor count doubles every 3 years
DRAM size quadruples every 3 years
Huge investment per generation is carried by huge
commodity market
180
160
140
120
100
80
60
40
20
0
Integer
FP
Sun 4 MIPS
260 M/120
HP 9000
750
DEC
Alpha
IBM
RS6000
MIPS
540
M2000
1987 1988 1989 1990 1991 1992
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Storage
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Divergence between memory capacity and speed
more pronounced
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Capacity increased by 1000x from 1980-95, speed only 2x
Gigabit DRAM by c. 2000, but gap with processor speed much greater
Larger memories are slower, while processors get faster
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Need to transfer more data in parallel
Need deeper cache hierarchies
How to organize caches?
Speed
Size
Registers
ns
~KB
Cache
10ns
~MB
Main memory
100ns
~100MB
Hard disk
10ms
~10GB
Archive
>100ms
~TB
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Instruction Sets
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Software costs growing faster
than hardware costs (1970s)
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CISC - Complex Instruction Set Architecture
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Machine language v.s. HLL
Support for high-level languages
Gap between high level languages
and computer hardware - semantic gap
Variety of instructions and addressing modes
DEC VAX
HLLCA - High Level Language Computer
Architecture
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RISC Architectures
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Resolve problems using simpler architecture
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"The case for the reduced instruction set computers"
Patterson & Ditzel [1980]
Stanford MIPS (Hennessy, 1981)
Commercial processors: MIPS R2000 (1986),
IBM RS6000, SPARC, PowerPC, etc.
Good design methodology
Efficient pipelining and compiler-assisted
scheduling of pipeline
Make the Common Case Fast

favor the frequent case
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Program Execution Time
T 

n i  CPI i  T cycle
i
For all instructions
in the instruction set
processor cycle time [s]
cycles per instruction
instruction count
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80x86 Instruction Mix
for SPECint92 Programs [PatHen96]
Instruction
Frequency
(%)
load
cond. branch
compare
22
20
16
store
add
and
12
8
6
sub
mov reg-reg
5
4
or
xor, not, etc.
uncond. branch
1
1
1
call
return, jmp indirect
shift
1
1
1
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70%
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Instruction Execution
A=B+C
result = op1 OPERATION op2
IF
ID
OF
A+=C
ADD R1, M(1000)
EX
ST
IF
…
Mem
PC
1000
When f = 5MHz
(’70s)
When f = 1000MHz
(’90s)
1000
Tcycle = 200ns
Tmem = 200ns
Tcycle = 1ns
Tmem = 50ns
…
100ns
100ns
1ns
t
1ns
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3 × 100ns = 300ns
2 × 1ns = 2ns
302ns
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Pipeline
INSTR
#1
IF
#2
#2
ID
OF
EX
ST
IF
IF
ID
OF
EX
ST
IF
ID
OF
EX
IF
ID
OF
IF
ID
#4
#5
program
#1
if( ) …
#2
#3
#4
time
CPI = 1
#100
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