Figure 12–1
Basic computer block diagram.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
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Figure 12–2
gray block.
Basic block diagram of a typical computer system including common peripherals. The computer itself is shown within the
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–3
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–4
The 8086/8088 has two separate internal units, the EU and the BIU.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–5
The internal organization of the 8088 microprocessor.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–6
Nonoverlapping and overlapping segments in the first 1 MB of memory. Each segment represents 64 kB.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–7
Formation of the 20-bit physical address from the segment base address and the offset address.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–8
Illustration of the segmented addressing method.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–9
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Figure 12–10
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–11
The general register set.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–12
The status and control flags.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–13
Registers for the Intel processors from 8086/8088 through Pentium.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–14
Hierarchy of programming languages relative to computer hardware.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–15
Assembly to machine conversion using an assembler.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–16
High-level to machine conversion with a compiler.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–17
Machine independence of a program written in a high-level language.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–18
Flowchart for adding a list of numbers.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–19
Steps in beginning to execute the addition program with Debug.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–20
Last portion of tracing the addition program. The sum 00F1 is shown in blue with the low part (F1) given first.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–21
Flowchart. The variable BIG represents the largest value.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–22
Listing of Debug portion of program.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–23
Data before and after a run.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–24
The basic polled I/O configuration.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–25
A basic interrupt-driven I/O configuration.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–26
A memory I/O transfer handled by the CPU.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–27
A DMA transfer.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–28
The interconnection of microprocessor-based system components by a bidirectional, multiplexed bus.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–29
An example of a handshaking sequence.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–30
Tristate buffer interface to a bus.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–31
Method of indicating tristate outputs on an IC device.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–32
Tristate buffer symbols.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–33
Tristate buffer operation.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–34
Multiplexed I/O operation.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–35
Simplified illustration of the basic bus system in a typical personal computer.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–36
The RS-232C 25-pin connector plug.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–37
The RS-232C pin assignments and signals for both connector versions.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–38
Example of a computer system with USB interfacing.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–39
A typical IEEE 488 (GPIB) connection.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–40
Timing diagram for the GPIB handshaking sequence.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–41
A bus extender and modem can be used for interfacing remote GPIB systems.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–42
SCSI 25-pin connector.
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–43
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Figure 12–44
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–45
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Figure 12–46
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
All rights reserved.
Figure 12–47
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–48
Thomas L. Floyd
Digital Fundamentals, 9e
Copyright ©2006 by Pearson Education, Inc.
Upper Saddle River, New Jersey 07458
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Figure 12–1 Basic computer block diagram.