Hardware Synthesis
Based on
RASSP Education & Facilitation Program and
Prof. P. P. Chu “RTL Hardware Design Using VHDL”
Definition
Hardware synthesis:
The process of producing a control sequence and
logical structure that will implement a given
abstract behavior satisfying a given set of
constraints (e.g., I/O rates, MIPS, sample period)
while trying to improve upon a set of objective
metrics (e.g., area, speed, power dissipation) of a
design.
Steps in the
Synthesis Process
Synthesis to the gate-level of abstraction consists of three
major steps Design specification (in a machine-readable form)
Design implementation
Design validation and verification
Design specification implies a description of the design
where functional, performance, and cost constraints (area,
power, speed) are captured in a form that is executable in a
CAD environment.
Two common methods for capturing the specification are:
Graphical methods
Language-based methods
Graphical Methods
Graphical methods include:
Block diagrams, state diagrams, schematics, data flow
graphs, timing diagrams, truth tables, etc.
Advantages:
Faster learning curve,
Intuitive documentation, and
Reusability of design.
Disadvantages:
Limited support for functional and timing hierarchy in
complex digital systems
Limited support for multiple views (e.g., simulation
versus hardware generation).
Language-based Methods
Language based methods include:
Hardware description languages (HDLs), high level
algorithmic macro descriptors (such as Matlab), or
application-specific languages (such as Silage and DSP/C
for signal processing).
Advantages:
Ability to serve as a standard medium of communication
between the algorithm developer and the synthesis expert
Robustness through well-defined semantics
Ability for representing complex behavior and data
structures
Language-based Methods (Cont.)
Support for synthesis and its verification in the
same environment,
Their system-independent nature that facilitates
design documentation.
Disadvantages:
Specification is harder to visualize, and requires
a longer learning curve.
Steps in the
Synthesis Process (Cont.)
Design Implementation consists of a number
of intermediate steps:
Algorithm design:
Evaluates the performance of the implemented
algorithm in terms of:
The precision of the word length,
The number of iterations, and
The quality of the results obtained with respect to the
design requirements.
Behavioral simulations:
Done after the algorithm design is complete to verify
the detailed functional behavior of the system.
Steps in the
Synthesis Process (Cont.)
Data and control flow graph generation:
Module selection
determining which modules are used in design
estimation and allocation of the modules to be used
Transformations
optimize the control/data flow graph without changing the
input/output functional properties
improve on its synthesis metrics (area, power, speed)
Scheduling
determines when a certain operation will be executed
determines the module on which the operand will be
executed (e.g., an addition on an adder module).
Steps in the
Synthesis Process (Cont.)
•
•
•
At the completion of this stage the result is called
a register-transfer level (RTL) model of the circuit
The RTL model is then converted to a logic level
implementation through a process called logic
synthesis
After completion of the logic synthesis, the
verification process is carried out at the gate level.
The Integrated Circuit Design
Process
Why Use Synthesis?

Shorter design cycles



Fewer errors



Hit market window sooner
Lower development costs
Greater likelihood of meeting initial specification
Less debugging time
Ability to search design space


Encourages top-down design
Can explore tradeoffs among many possible designs
Why Use Synthesis? (Cont.)
 Allows
technology independent design
 A popular
use is migrating FPGA designs to
ASICs

Documents the design process
 Records
and justifies decisions made
 Provides design description in structured formats

Makes IC technology more accessible
 Provides
capability to non-experts
 Lowers IC design costs
Synthesis Goals
 Goals
include producing designs with:
 Maximum
speed
 Minimum cost (area, package count, etc.)
 Minimum pin count
 Minimum power consumption
 Minimum design time
 Maximum reliability
 Maximum testability
Design Constraints
 Design
 Time
constraints:
delays for and between significant events
 Area or package count upper bounds
 Maximum number of pins
 Upper bound on power consumption
 Upper bound on software run times
 Lower bound on reliability
 Lower bound on testability
VHDL Support for Synthesis
VHDL-Based
Synthesis
Design
Capture
Design
Simulation
Design
&
Specification
Verification
Design
Documentation
Design Capture
VHDL captures the details of a digital design in a
machine-readable form, entered into a CAD
system.
VHDL is an alternative to a schematic-based
design entry.
Logic synthesis and RTL synthesis tools are
design capture environments.
Over 90% of designers use VHDL for this purpose
(EE Times, 1996).
Design Specification
In a structured design flow, VHDL captures
the behavioral, interface and performancerelated aspects of the design.
The VHDL representation can then be
synthesized using behavioral synthesis and
advanced RTL synthesis.
Design Simulation and
Verification
VHDL is used to simulate key properties of
a design prior to and after synthesis.
VHDL can verify those properties at various
levels of the synthesis process.
Various levels of functional and timing
simulation includes both technology
dependent and independent aspects of the
design
Design Documentation
A design represented in VHDL is well-documented,
and is accepted by the US Department of Defense.
 VHDL, an IEEE standard, represents designs in a
non-proprietary, technology -independent manner.
 VHDL represents both the design and its test
environment in a tool-environment, technologyneutral manner, improving design productivity, reuse,
and its rapid upgrade.

Definitions
Control-flow
The operation of hardware in terms of the loops,
conditional branches, and ordering of functions
Data paths
The hardware which stores and performs operations
on data
Gate level
The operations and storage elements can be
described by logic gates such as NAND and OR
Definitions (Cont.)
Register-transfer level
The hardware is described in terms of transfers of
data between registers and operations on the data
usually expressed as bit vectors rather than as
single-bit values;
includes register-transfer behavior and structure
Gajski and Kuhn’s Y Chart
Behavioral
Architectural
Structural
Algorithmic
Functional Block
Processor
Systems
Hardware Modules
Algorithms
Logic
ALUs, Registers
Register Transfer
Circuit Gates, FFs
Logic
Transistors
Transfer Functions
Rectangles
Cell, Module Plans
Floor Plans
Clusters
Physical Partitions
Physical/Geometry
Synthesis Categories
Algorithm synthesis
Synthesis from design requirements to control-flow
Largely a manual process
Behavioral to Register-transfer synthesis
Also referred to as “high-level” synthesis
Synthesis from either abstract, control-flow, or registertransfer behavior to register-transfer structure
Logic synthesis
Synthesis from register-transfer structures or Boolean
equations to gate-level logic
Behavioral Synthesis
E(7:0)
A(7:0) B(7:0)
C(7:0) D(7:0)
+
f <= (a + b) * e;
g <= (a + b) * (c + d);
+
*
*
F(15:0)
G(15:0)
E(7:0)
A(7:0) B(7:0)
C(7:0) D(7:0)
t1
+
t2
+
*
*
F(15:0)
G(15:0)
t3
[Parker84]
Behavioral Synthesis (Cont.)
Data Path Behavior
Control Flow
(not all shown)
E(7:0)
A(7:0) B(7:0)
C(7:0) D(7:0)
t1
+
t2
+
*
*
F(15:0)
G(15:0)
t3
A(7:0) B(7:0) C(7:0) D(7:0)
Select A;
Load R1;
Register
R2
Register
R1
E(7:0)
Select B;
Load R2;
Add;
Load R4;
+
Register
R3
Register
R4
*
Register
R3
Register
R4
F(15:0)
G(15:0)
[Parker84]
RTL Level Synthesis
Data Path Behavior
A(7:0) B(7:0) C(7:0) D(7:0)
Control Flow
(not all shown)
RTL Structure
(not all shown)
A(7:0) B(7:0)
Select A;
Load R1;
C(7:0) D(7:0)
RTL Control Flow
(not all shown)
Select B;
Load R2;
Register
R2
Register
R1
E(7:0)
+
Register
R3
Select A;
Load R1;
Add;
Load R4;
Select B;
Load R2;
R2
R1
Add;
Load R4;
Register
R4
ALU
*
Register
R3
Register
R4
F(15:0)
G(15:0)
[Parker84]
Behavioral Synthesis
The input to a behavioral synthesis system describes the dataflow,
input/output constraints, memory accesses, and user defined
constraints (sample period, latency…).
The output of the behavioral synthesis system provides the datapath,
registers, memories, I/O structures, and a state machine-based
controller that satisfies the same test bench as the input.
Dataflow
Input/Outputs
Memory accesses
Constraints
Behavioral
Synthesis
Datapath
Memory
Controller
(State
machine)
Behavioral Synthesis Example
(Cont.)
Design Specification:
I/O Constraints
Data flow
User Constraints
Complex Multiplication: Z = ( a + b j) * ( c + d j ).
Input Data: Available serially a, b, c, d.
Real { Z } = Real part of Z = a*c - b*d
Im { Z } = Imaginary part of Z = a*d + b*c
Output Constraints: Real { Z } and Im { Z } to be available
on separate ports
Find Best Design (Area, Latency, Throughput, …)
Algorithmic level description
Input to Behavioral Synthesis
Cycle
I/O, Memory
Data flow Graph Representation
a
5 bits
10 bits
Re{Z}
x
-
b
c
x
Im{Z}
x
+
d
0
Input A
1
Input B
2
Input C
3
Input D
4
Compute Re(Z),Im(Z)
..
x
The data flow graph and I/O schedule are
captured in a VHDL input description
N
Output Results
Input in Behavioral VHDL
IEEE Synthesis Package
Library IEEE
Use IEEE.Numeric_STD.all
Entity complexb_nty is
port ( datain_p: in unsigned (4 downto 0);
output_re, output_im :
out unsigned (9 downto 0));
end complexb_nty;
I/O Constraints
wait until clk’event and clk =‘1’;
c := datain_p;
wait until clk’event and clk = ‘1’;
d := datain_p;
-- Computation begins
Dataflow
Output_re <= a*c - b*d ;
Architecture complexb_a of complexb_nty is
Output_im <= a*d - b*c ;
begin
behave: process
User specifies
end loop;
variable a, b, c, d : unsigned (4 downto 0);
arithmetic ops
begin
independent of
end process;
calc: loop
clock (clk) event.
wait until clk’event and clk =‘1’;
endarchitecture
complexb_a;
Single process
a := datain_p;
wait until clk’event and clk =‘1’;
b := datain_p;
Results from Behavioral
Synthesis
Cycles
READ
0
A
1
2
B
C
3
Design Objective 1: Fast Implementation
Clock cycle: 50 ns
4
Metric
D
Value
MULT_1
A*C
A*D
Area
1700 gates
MULT_2
B*C
B*D
Latency
250 ns
ADD_1
AC*-B*D
Multipliers
Two
ADD_2
A*D+B*C
Adders
Two
Area = 1700 gates
Latency = 5*50 = 250 ns
Multipliers = Two
Adder = Two
Design Objective
Fast
Small
Power
Results from Behavioral
Synthesis (Cont.)
Design Objective 2: Small Area
Clock period: 50 ns
Cycles
0
1
2
3
READ
A
B
C
D
A*C
A*D
MULT_1
ADD1
Area = 1250 gates
Latency = 7*50 = 350 ns
Multipliers = One
Adder = One
4
B*C
5
6
7
B*D
A*D+B*C A*C+B*D
Design Objective
Fast
Small
Power
Characteristics of Behavioral
Synthesis
Pros
User inputs behavioral-level
VHDL code that is short, easy
to write, and verify
The synthesis tools perform
the resource allocation,
assignment, scheduling
They optimize area, latency,
and power dissipation
Output from a behavioral
synthesis tool can be starting
point for further optimization.
Cons
Supports a small subset of
VHDL (e.g., single process
architectures).
Non-standard implementations
Currently supports application
specific areas (such as DSP)
Cannot handle larger graphs
Needs high level libraries of
components
RTL Synthesis
o
o
Input to the RTL synthesis includes data path components (adders,
multipliers,…), the mapping of operations, and a controller that
contains the schedule of computations, I/O, and memory operations.
Output of the RTL synthesis provides logic level implementations
obtained through the optimization of the data path, memory, and
controller components, and mapping to gate-level component libraries.
Datapath
Controller
(State machine)
Clock-edge timing
RTL Synthesis
Random logic
Datapath blocks
Registers
Inferred memories
Clock-edge timing
RTL Synthesis Example
Design Specification
Multiply Accumulate (MAC):
Z = A*B + C
Input data:
Available serially
Computation:
Z = A*B + C
Available Hardware:
1 Multiplier, 1 Adder
Output:
Z available at end of computation.
A
Clock
B
REG2
REG1
Data path
Le_Z
REG3
MULT
C
REG4
REG5
Z
Le_add
ADD
Le_mult
Finite State
Machine (FSM)
RTL VHDL Input
The architecture consists of a datapath and two finite state machine (FSM) processes
Datapath: process
variable reg_1, reg2 : unsigned (4 downto 0);
variable reg_3, reg_4, reg_5: unsigned (9 downto 0);
begin
wait until clk’event and clk’event=‘1’;
if le_reg1 = ‘1’ then reg1 := a;
end if;
if le_reg2 = ‘1’ then reg2 := b;
end if;
if le_reg3 = ‘1’ then reg3 := c ;
end if;
if le_mult = ‘1’ then reg4 := reg1 * reg2;
end if ;
if le_add = ‘1’ then reg5 := reg4 + reg3;
end if
if le_z = ‘1’ then output <= reg5 ;
end if;
end process;
Behavior at each clock edge is specified
Area = 1400 gates, Latency = 300ns
Fsm: process(clk, reset); begin
if clk’event and clk =‘1’ then
ir reset = ‘1’ then cur_state <= s0;
else cur_state <= next_state;
end if; end process;
state_machine:
process (cur_state, reset)
begin case cur_state is
when s0 => next_state <= s1;
le_reg1 <= ‘1’;
when s1 => next_state <= s2;
le_reg2 <= ‘1’;
when s2 => next_state <= s3;
le_reg3 <= ‘1’;
when s3 => next_state <= s4;
le_mult <= ‘1’;
when s4 => next_state <= s5;
le_add <=‘1’;
when s5 => next_state <= s0;
le_z <= ‘1’;
end case; end process;
Characteristics of RTL Synthesis
Pros
Cons
Allows capture of a design at the
Vendors support different RTL
RTL level - improving productivity
subsets of VHDL
over logic synthesis
Requires specification of the
Allows manual mapping to libraries
datapath, registers, controller, and
of high-level components
cycle-by-cycle behavior
(multipliers, adders)
Resource sharing, resource allocation,
More control over the synthesis
scheduling, and mapping have to be
process in terms of final architecture
carried out prior to coding at the RTL
level.
Provides templates for VHDL state
machine optimization
Allows no architectural exploration,
and the synthesizer optimizes at the
IEEE RTL VHDL standard, ‘97
level of the components
Supports a large subset of VHDL
Logic Synthesis
Realizes the circuit with the optimal number
of “generic” gate level components
 Two categories:

Logic Synthesis
RTL Structure
(not all shown)
A(7:0) B(7:0)
C(7:0) D(7:0)
RTL Control Flow
(not all shown)
Select A;
Load R1;
Select B;
Load R2;
R2
R1
Add;
Load R4;
ALU
© IEEE 1984
[Parker84]
Logic Synthesis
Logic synthesis optimizes the Boolean equations and
maps them to technology specific gate-level
implementations utilizing functional and timing
information from technology libraries.
The operations in the logic synthesis include multilevel
minimization, factorization, and equation flattening so
that area, power, and timing metrics are optimized.
Few EDA vendors, such as Synopsys, do not
distinguish between the tasks of RTL synthesis and
logic synthesis.
Logic Synthesis Tasks
(e.g., Mentor Graphics’ AutoLogic)
Flattening
Changing from multi-level to a two-level description
Factorization
Performing Boolean factorization and reduction in the
combinational logic
Transduction
Removing redundant logic while maintaining logical
functionality
Technology Mapping
Mapping the logic to particular cells in the target
technology
Summary of VHDL-Based
Synthesis
VHDL Specification
Behavioral Synthesis
RTL Simulation
RTL Synthesis
Verification
Gate-level Simulation
Logic Synthesis
Test Insertion/Gate-level
Timing/Optimization
To
Vendor
Floor plan, place & route
IEEE Support for Synthesis
IEEE Std 1076-1993 VHDL Language Reference Manual
(LRM)
IEEE Std 1164-1993, IEEE Standard Multivalue Logic
System for VHDL Model Interoperability
STD_LOGIC_1164
IEEE Std 1076.3-1997 IEEE Standard Synthesis Packages
NUMERIC_BIT and NUMERIC_STD
IEEE Std 1076.6-1999 IEEE VHDL Register Transfer Level
(RTL) Synthesis
VHDL Packages for Synthesis
Arithmetic Packages
All synthesis tools support some type of arithmetic
packages
Synopsys developed packages based on std_logic_1164
package - supported by many other synthesis tools
std_logic_arith
std_logic_signed
std_logic_unsigned
Actel synthesis tools support their own package
asyl.arith
IEEE Synthesis Packages
IEEE has developed standard packages for synthesis IEEE
Std. 1076.3
Numeric_Bit
Numeric_Std

1076.3 NUMERIC_STD and 1076.3 NUMERIC_BIT
packages define numeric types and arithmetic/logic
functions for synthesis.

Vendors may not change the specified interfaces or
simulation descriptions of the package declarations.
VHDL Packages for Synthesis
Base Types
 Standard bit types may be used
 Typically IEEE Std. 1164 types are used
USE IEEE.std_logic_1164.ALL;
 std_ulogic type
 Values ‘U’, ‘X’, ‘W’, and ‘-’ are called metalogical values for
synthesis
TYPE std_ulogic IS ( 'U', -- Uninitialized
'X', -- Forcing Unknown
'0', -- Forcing 0
'1', -- Forcing 1
'Z', -- High Impedance
'W', -- Weak
Unknown
'L', -- Weak
0
'H', -- Weak
1
'-'
-- Don't care
);
 std_logic
type - resolved std_ulogic type
VHDL Packages for Synthesis
Base Types (Cont.)

The std_logic_1164 package also contains:
 Vectors of std_ulogic and std_logic
 Subtypes of std_logic - X01, X01Z, UX01, UX10Z
 Logic functions - std_ulogic, std_logic, std_logic_vector
FUNCTION
FUNCTION
FUNCTION
FUNCTION
FUNCTION
FUNCTION
FUNCTION
“and”
“nand”
“or”
“nor”
“xor”
“xnor”
"not"
(l,r
(l,r
(l,r
(l,r
(l,r
(l,r
(l,r
:
:
:
:
:
:
:
std_ulogic;) RETURN UX01;
std_ulogic;) RETURN UX01;
std_ulogic;) RETURN UX01;
std_ulogic;) RETURN UX01;
std_ulogic;) RETURN UX01;
std_ulogic;) return ux01;
std_ulogic) RETURN UX01;
Conversion functions
FUNCTION To_bit(s:std_ulogic) RETURN bit;
FUNCTION To_bitvector(s:std_ulogic_vector) RETURN bit_vector;
FUNCTION To_StdULogic(b:bit) RETURN std_ulogic;
VHDL Packages for Synthesis
Base Types (Cont.)
Clock edge functions
FUNCTION rising_edge (SIGNAL s:std_ulogic) RETURN boolean;
FUNCTION falling_edge (SIGNAL s:std_ulogic) RETURN boolean;
Unknown functions
FUNCTION Is_X (s:std_ulogic_vector) RETURN boolean;
FUNCTION Is_X (s:std_logic_vector) RETURN boolean;
FUNCTION Is_X (s:std_ulogic) RETURN boolean;
Predefined Synthesis Types


A compliant synthesis tool shall support the following types:
 BIT, BOOLEAN and BIT_VECTOR (defined in IEEE VHDL
LRM)
 INTEGER (defined in IEEE VHDL LRM)
 STD_LOGIC, STD_LOGIC_VECTOR, STD_ULOGIC,
STD_ULOGIC_VECTOR (defined in IEEE Std 1164-1993)
 SIGNED and UNSIGNED (defined in NUMERIC_STD in IEEE
1076.3)
 SIGNED and UNSIGNED (defined in NUMERIC_BIT IEEE
1076.3)
In addition, the synthesis tool shall support user-defined types and
derived types according to a set of rules.
VHDL RTL Keywords
abs
access
after
alias
all
and
architecture
array
assert
attribute
begin
block
body
Buffer
bus
case
component
configuration
constant
disconnect
downto
else
elsif
end
entity
Exit
file
for
function
generate
generic
group
guarded
if
impure
in
Inertial
inout
is
Next
nor
not
null
label
library
linkage
literal
loop
of
on
open
or
others
out
map
mod
nand
new
• word (bold italic) implies that the keyword is not supported in synthesis
• underlined word implies the construct is ignored during synthesis
package
port
postponed
VHDL RTL Keywords
(cont.)
procedure
process
pure
range
record
register
reject
rem
report
return
rot
ror
select
severity
shared
signal
sla
sll
sra, srl
use
variable
wait
when
subtype
then
to
transport
type
while (in loop)
with
xnor
xor
unaffected
units
until
• word (bold italic) implies that the keyword is not supported in synthesis
• underlined word implies the construct is ignored during synthesis
VHDL RTL Syntax Key
Design Entities
Entities &
Architectures
Packages
Package body
Configuration
Subprograms
Declarations
Type & subtype
Objects
Attributes
Components
Group
Specifications
attributes
configurations
names
Expressions
arithmetic
logic
comparison
shift, resize
Sequential Constructs
wait
report, assert
signal assignment
procedure
if, case, loop & next
Note: many allowed features are
supported partially.
Types
scalar
composite
access
file
Concurrent Statements
process
block
concurrent procedure call
concurrent assertion
concurrent signal assignment
component instantiation
generate statement
• word (bold italic) implies that the keyword is not supported in synthesis
• underlined word implies the construct is ignored during synthesis
VHDL RTL Types
Scalar
Enumeration
Integer
Physical
Floating point
Access
Composite
Array
Record
File
• word (bold italic) implies that the keyword is not supported in synthesis
• underlined word implies the construct is ignored during synthesis
Support for Additional VHDL
Provisions

Attributes





Can be associated with arrays, blocks, signal, types, etc.
Standard set generally supported for arrays and types
Standard set generally not supported for blocks
Some in standard set for signals supported
Types

Support generally specific to tool


E.g., Autologic supports bit_vector and integer, but not
floating_point or real
Operators

Support often additionally dependent on type of operands
Synthesis of Combinational Circuits

Combinational circuits include






logic/arithmetic
multiplexers and demultiplexers
encoders and decoders
comparators
Arithmetic Logic Units (ALUs)
Both concurrent statements and sequential VHDL
statements can be used to model combinational
circuits.
Combinatorial Example
Process with Intermediate Signal
ARCHITECTURE rt1 of ao IS
SIGNAL result : BIT;
BEGIN
PROCESS (i0, i1, i2, result)
BEGIN
result <= i0 AND i1;
o0 <= result OR i2;
END PROCESS;
END rt1;
Combinatorial Example
Process with Intermediate Signal
Synthesized circuit:
i2
i0
i1
o0
Combinatorial Example
Selected Signal Assignment
ARCHITECTURE rt1 of mux4 IS
BEGIN
WITH sel SELECT
o0 <= i0 WHEN “00”,
i1 WHEN “01”,
i2 WHEN “10”,
i3 WHEN OTHERS;
END rt1;
MUX41
i0
A
i1
B
i2
C
i3
D
S0
sel (1:0)
Z
S1
o0
Synthesizing Flip Flops using
“if”

Guidelines for modeling FFs using “if” statement
The template for modeling a positive-edge FF with an “if” statement is
Template:
Example:
process (<clock signal>)
process(clock)
<declarations>
<declarations>
if <clock edge> then
if rising_edge(clock) then
<sequential statements>
Only clock signal
in sensitivity list
Q <= D;
end if;
end if;
end process
end process;
Note: D is read before it is written to, so this infers storage required.
Inferring FFs Using “if”
An edge sensitive FF is inferred under the following conditions.
1. Synchronous assignment is defined for both signals and
variables using edge-sensitive storage elements.
2. If the value of the variable is read before write, then an edge
sensitive FF is modeled.
3. Only the clock signal (and asynchronous signals) shall be
included in the sensitivity list of the process with the if
statement.
4. No statements shall precede or succeed the if statement in
the process.
Synthesis of IF-ELSE Statement
VHDL Description
ARCHITECTURE rt1 OF if_else_test IS
BEGIN
PROCESS (select0, in0, in1)
BEGIN
IF (select0 = ‘1’) THEN;
out0 <= in0;
ELSE
out0 <= in1;
END IF;
END PROCESS;
END rt1;
Synthesis of IF-ELSE Statement
in1
in0
A
B
MUX21
Resulting Schematic
S
select0
Z
out0
Synthesis of Simple If Statement
VHDL Description
ARCHITECTURE rt1 OF if_test IS
BEGIN
PROCESS (select0, in0)
BEGIN
IF (select0= ‘1’) THEN;
out0 <= in0;
END IF;
END PROCESS;
END rt1;
Synthesis of Simple If Statement
Resulting Schematic
in0
D
Q
select0
E
out0
Internal State Example
Incorrect Version
ARCHITECTURE incorrect OF u_internal_e IS
BEGIN
PROCESS (in1)
VARIABLE x : qsim_state;
BEGIN
IF (in1 = ‘1’) THEN
x:= ‘1’;
ELSIF (in1 = ‘0’) THEN
x:= ‘0’;
-- if in1 not ‘1’ nor ‘0’ then
END IF;
-- no value assigned to variable x
output <= x;
END PROCESS;
END incorrect;
Internal State Example
Corrected Version
ARCHITECTURE correct OF u_internal_e IS
BEGIN
PROCESS (in1)
VARIABLE x : qsim_state;
BEGIN
x := ‘0’;
IF (in1 = ‘1’) THEN
x:= ‘1’;
END IF;
output <= x;
END PROCESS;
END correct;
Internal State for Signal Example
Unsynthesizable Version
ARCHITECTURE incorrect OF int_state IS
SIGNAL reslt : qsim_state;
BEGIN
PROCESS (en1, in1, in2)
BEGIN
IF (en1 = ‘1’) THEN
reslt <= in2 AND in1; -- reslt not on sensitivity list
END IF;
output <= reslt;
-- sequential signal assignment
END PROCESS;
END incorrect;
Internal State for Signal Example
Synthesizable Feedback Version
ARCHITECTURE correct OF int_state IS
SIGNAL reslt : qsim_state;
BEGIN
PROCESS (en1, in1, in2, reslt)
BEGIN
IF (en1 = ‘1’) THEN
reslt <= in2 AND in1;
END IF;
output <= reslt;
END PROCESS;
END correct;
Internal State for Signal Example
Feedback Version
in1
B
in2
MUX21
A
Z
D
Q
S
en
E
output
Internal State for Signal Example
Synthesizable without Feedback
ARCHITECTURE incorrect OF int_state IS
SIGNAL reslt : qsim_state;
BEGIN
PROCESS (en1, in1, in2)
BEGIN
IF (en1 = ‘1’) THEN
reslt <= in2 AND in1;
END IF;
END PROCESS;
output <= reslt;
-- concurrent signal assignment
END correct;
Internal State for Signal Example
No Feedback Version
in1
D
in2
Q
en
E
output
Registers and Clocks


Clock types:
Allowed types for clock signals -- BIT, STD_ULOGIC
and their subtypes (STD_LOGIC),



with a minimum subset of ‘0’ and ‘1’, without the metalogical
values (U, X, W, or “-”).
Clock edges
Can be specified either



using the VHDL functions FALLING_EDGE and RISING_EDGE
declared in STD_LOGIC_1164 or
by NUMERIC_BIT, or
through the use of if and wait statements (with some restrictions).
Clock Edge Specification

Positive/negative edge clocks
 if
statement can be used as follows
1. If RISING_EDGE (clk_signal_name)
2. If clk_signal_name’EVENT and clk_signal_name = ‘1’
3. If not clk_signal_name’STABLE and clk_signal_name = ‘1’
Note: The negative clock edge can be modeled similarly using
FALLING_EDGE and clk_signal_name =‘0’ in the above
statements.
Clock Edge Specification (Cont.)

Positive/negative clock edge specification
 Using
the wait until statement in VHDL, the
following statements are equivalent
1. Wait until RISING_EDGE (clk_signal_name)
2. Wait until Clk_signal_name = ‘1’
3. Wait until Clk_signal_name’EVENT and clk_signal_name =‘1’
4. Wait until not clk_signal_name’STABLE and clk_signal_name =‘1’
The wait statement should be the first statement in the process, which
can cause problems when the process is required to be sensitive to
other asynchronous inputs.
Inferring FFs Using“wait”
Only one wait statement is allowed per process, and it
shall be the first statement in the process.
This implies that asynchronous conditions cannot be
modeled in the same process using the wait until construct.
Label: Process -- note labels are allowed for processes
begin
wait until CLOCK = ‘0’; -- Negative edge
COUNT := COUNT + 1; -- COUNT may model edge-sensitive FF
VAR := COUNT
-- VAR is written to before it is read - no FF
VAR := VAR + 1;
Q <= D;
-- Q also infers FF
end process;
Clocked Register with Logic
VHDL Description
ARCHITECTURE rt1 OF example IS
SIGNAL temp : BIT := ‘0’;
BEGIN
latch: PROCESS
BEGIN
WAIT UNTIL (clk = ‘1’);
temp <= NOT i0;
END PROCESS latch;
o0 <= temp;
END rt1;
Clocked Register with Logic
Resulting Schematic
i0
D
Q
clk
CP
output
Logic after the Register
VHDL Description
ARCHITECTURE rt1 OF example IS
SIGNAL temp : BIT := ‘0’;
BEGIN
latch: PROCESS
BEGIN
temp <= NOT i0;
WAIT UNTIL (clk = ‘1’);
END PROCESS latch;
o0 <= temp;
END rt1;
Logic after the Register
Resulting Schematic
i0
D
Q
clk
CP
output
Synthesizing Asynchronous
Signals
Asynchronous signals such as SET/RESET are frequently
included in synchronous circuits. The wait until construct does
not support this feature, however the if construct can.
Async_dff: process (clock, reset, set)
begin
if reset = ‘1’ then Q <= ‘0’;
elsif set = ‘1’ then Q <= ‘1’;
elsif clock’event and clock = ‘1’ then Q <= D;
end if ;
end process;
Level Sensitive D Latch

Use IF statement without Else clause
library IEEE;
use IEEE.std_logic_1164.all;
ENTITY d_latch is
PORT(d
: IN std_logic;
clk : IN std_logic;
q
: INOUT std_logic;
qn : OUT std_logic);
END d_latch;
ARCHITECTURE behavior OF d_latch IS
BEGIN
seq : PROCESS(d,clk)
BEGIN
IF(clk = '1') THEN
q <= d;
END IF;
END PROCESS seq;
qn <= not q;
END behavior;
Inferring Level-Sensitive Logic
Level sensitive logic shall be synthesized
under the following conditions:
1. A signal or variable is assigned in a process that
does not contain clock edges, and
2. There are executions of the process that do not
have an explicit assignment to the signal or variable
(requiring it to store older values), and
3. All signals and variables read by the process
have well defined values.
Lev_sen: process (en, D)
begin
if en = ‘1’ then
Q <= D;
end if ;
end process;
Note: The code does not
specify what is to be done
if en is not ‘1’.
Note: When the executions of the process require reading before
assignment, then level sensitive logic may be synthesized.
Synchronous RTL Synthesis
Example
NAND
A
Int1
NAND
B
Y
C
Int2
D
NOR
DFF
Previous value of
int2 used – need DFF
DFF
Clock
Note:variable int1 does not infer FF (because it is
assigned to before being read, however
Y and int2 infer FFs. Sensitivity list only
contains the clock and asynchronous set/reset
(if present). A, B, C, are not included.
Process (clock)
variable int1: std_logic
begin
if rising_edge (clock) then
int1 := A nand B;
int2 <= C nor D;
Y <= int2 nand int1 ;
end if ; end process;
Keys to Success with Synthesis

Designer must “think in hardware”
aware of tool-specific “templates” (e.g., latch, mux)
 Be aware of relative timing of signals wrt the clock edge
 Be

VHDL process is basic unit of RTL description
 Combinational process
 Sensitivity lists include all signals in right-hand-side of logic equations
 Register-instantiation process
 Only clock and/or reset signals in sensitivity lists
 Inputs should not feed non-registered outputs
Theoretical limitation
Synthesis software does not know your
intention
 Synthesis software cannot obtain the optimal
solution
 Synthesis should be treated as transformation
and a “local search” in the “design space”
 Good VHDL code provides a good starting
point for the local search

Realization of VHDL operator

Logic operator
 Simple,

direct mapping
Relational operator
=, /= fast, simple implementation exists
 >, < etc: more complex implementation, larger
delay

Addition operator
 Other arith operators: support varies

Operator with one constant
operand
 Can
significantly reduce the hardware
complexity
 E.g.,
adder vs. incrementor
y <= rotate_right(x, y); -- barrel shifter
y <= rotate_right(x, 3); -- rewiring
y <= x(2 downto 0) & x(7 downto 3);
 E.g.,
4-bit comparator: x=y vs. x=0
An example 0.55 um standard-cell
CMOS implementation
a – optimized for area,
d – optimized for delay time
Use and synthesis of ‘Z’

Tri-state buffer:
 Output
with “high-impedance”
 Not a value in Boolean algebra
 Need special output circuitry (tri-state buffer)
Major application of ‘Z’
 Bi-directional
 Tri-state

I/O pins
bus
VHDL description:
y <= 'Z' when oe='1' else
a_in;

‘Z’ cannot be used as input or manipulated
f <= 'Z' and a;
-- not good
y <= data_a when in_bus='Z' else
data_b;
Separate tri-state buffer from regular code:
Less clear:
with sel select
y <= 'Z' when "00",
'1' when "01"|"11",
'0' when others;
better:
with sel select
tmp <= '1' when "01"|"11",
'0' when others;
y <= 'Z' when sel="00" else
tmp;
Bi-directional i/o pins
Bi-directional i/o pins
Tri-state bus
Tri-state bus

Problem with tri-state bus
 Difficult

to optimize, verify and test
Alternative to tri-state bus: mux
Synthesis Entry Points

High-level language description
 E.g.,

Tool-specific language description
 May

VHDL, Verilog
include parameterizable primitives
Truth tables
 May
be in a form “borrowed” from another
target technology, such as PLDs

Logic equations
Common Synthesis Targets

ASICs



FPGAs



“Simple” ASIC development is greatly simplified
Expertise required for aggressive speed, size, or power
designs
Design can be retargeted to an FPGA for a low-cost
rapid-turnaround prototype to test functionality
Routing and layout problems similar to ASICs
PLDs

Routing and layout largely replaced by design
partitioning
Common Synthesis Targets
E.g., mapping in
standard-cell ASIC

Device library
Mapping in standard-cell ASIC

Cost in design area :
31 vs. 17 units
Mapping in FPGA

With 5-input LUT (Look-Up-Table) cells
Synthesis Shortcomings

Design partitioning
 A difficult

problem requiring much user interaction
Circuit timing estimates
 High-level
synthesis tools use pre-layout estimates
- not accurate for large (e.g. >6000 gates) circuits

May be difficult to associate resulting design with
original description
Propagation delay
Delay: time required to propagate a signal
from an input port to an output port
 Cell level delay: most accurate
 Simplified model:

Gate delay

Parasitic effect
The impact of wire becomes more dominant as
devices get smaller
Propagation delay
C load 
C
i
gi
 C wi
System delay
The longest path (critical path) in the system
 The worst input to output delay

“False path” may exists:
Synthesis with timing constraint
Multi-level synthesis is flexible
It is possible to reduce by delay by adding extra logic
Synthesis with timing constraint



1.
2.
3.
Obtain the minimal-area implementation
Identify the critical path
Reduce the delay by adding extra logic
Area-delay trade-off curve
Timing Hazards
Propagation delay: time to obtain a stable
output
 Hazards: the fluctuation occurring during
the transient period

 Static
hazard: glitch when the signal should be
stable
 Dynamic hazard: a glitch in transition

Due to the multiple converging paths of an
output port
Timing Hazards

Static-hazard
consider
sh=ab’+bc;
for a=c=1
Timing Hazards

Dynamic hazard
consider changing
b for (a=c=d=1)
Dealing with hazards

Some hazards can be eliminated in theory
Dealing with hazards
Eliminating glitches is very difficult in reality,
and almost impossible for synthesis
 Multiple inputs can change simultaneously

 e.g.,

1111=>0000 in a counter
How to deal with it?
 Ignore
glitches in the transient period and retrieve
the data after the signal is stabilized
Delay sensitive design and its danger

Boolean algebra
 the
theoretical model for digital design and
most algorithms used in synthesis process
 algebra deals with the stabilized signals

Delay-sensitive design
 Depend
on the transient property (and delay) of
the circuit
 Difficult to design and analyze
Delay sensitive design and its danger

What’s can go wrong:

E.g., pulse <= a and (not a);





During logic synthesis, the logic expressions will be rearranged and
optimized.
During technology mapping, generic gates will be re-mapped
During placement & routing, wire delays may change
It is bad for testing verification
If delay-sensitive design is really needed, it
should be done manually, not by synthesis
Hardware Synthesis Flow
Procedural
Specification of
Hardware in
VHDL
Target
Architecture
Constrains
Multicomponent
Partitioning
Technology
Database
Behavioral
Specifications
and Constraints
for MCMs
Behavioral
Specifications
and Constraints
for ASICs
Behavioral
Specifications
and Constraints
for FPGAs
Multichip
Synthesis
System
(MSS)
ASIC
Synthesis
(DSS)
FPGA
Synthesis
Integration
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Test Technology Overview Module