RIFLE: a Research Instrument
for FLash Evaluation
Active Technologies
Presentation
This file contains a RIFLE instrument presentation
A RIFLE’s user demo is shown in the Rifle demo file
This demo has been designed for Office 2002, but
it may run quite well under Office 2000
Active Technologies - RIFLE presentation - October 2003
Index
Select the section to visit by clicking on the section name
• Introduction
( 1 min. 15”)
• Hardware features
( 7 min. 10”)
• System performances
• Software architecture
• Scientific references
( 1 min. 55”)
( 2 min. 10”)
( 1 min. 10”)
• Role of Active Technologies and N-plus-T
• End of presentation
Active Technologies - RIFLE presentation - October 2003
( 20”)
Project history
• 1996 – Kick-off of the RIFLE project, at the
Università di Ferrara, Italy
• 1998 – First prototype: beginning of research
activity
• 2001 – First industrialized release
• 2002 – Second industrialized release
• 2003 – Creation of the Academic spin-off
Active Technologies for RIFLE commercialization
and support
Active Technologies - RIFLE presentation - October 2003
Aims of the project
• Development of a “flexible” instrument
research/characterization activities
for
• ATE-like hardware performances
• Standard software support (C, C++ languages
and LabVIEW)
• Ultra-friendly use
Active Technologies - RIFLE presentation - October 2003
Flexible instrument: why
• New products development and characterization
require high flexibility (data acquisition, signal
waveforms, voltages, …)
• “What if” philosophy
• Possibility of identify and track selected cells
• Possibility of evaluating the impact of any
modification on long-term reliability
• Possibility of immediate availability of measure’s
results
Active Technologies - RIFLE presentation - October 2003
End of Section
Make your choice by using the PC mouse
Index page
End of presentation
Active Technologies - RIFLE presentation - October 2003
Instrument architecture
Active Technologies - RIFLE presentation - October 2003
P.C.I. BUS
Features
• Standard Bus
• DUT (Device Under Test) is treated as an
extension of the PC memory: it is simply
accessed like an array structure during
read/write cycles
• PC’s storing and computational capabilities
are fully exploited
• Storing and computational capabilities can
be upgraded by upgrading the PC
• Address space: 512Mbytes
• Bus width: 8, 16, 32 bits
• Bus speed: up to 33 MHz
Active Technologies - RIFLE presentation - October 2003
Timing Generator
A Programmable state machine translates the PCI cycles
into the DUT cycles to match its timing requirements
Active Technologies - RIFLE presentation - October 2003
Waveform generators
RIFLE can be equipped with up to 16 arbitrary waveform generators.
The impact on device performance and long term reliability of any shape
and duration modification in the waveform applied during writing operations
can be easily evaluated
Unused slots for waveform generators can be used to plug-in customized
cards to add new hardware features
Active Technologies - RIFLE presentation - October 2003
DAC
Waveform generators
Top
Bottom
The generator architecture is based on a
high speed 32ksample (or 128ksample)
SRAM, managed as a FIFO, where the
waveform samples are stored during the
measurement setup
Control
Block
Active Technologies - RIFLE presentation - October 2003
DAC
Waveform generators
Top
Bottom
When the waveform is generated, its samples are popped from
the FIFO memory and converted into an analog signal by a high
speed (125 Msps) D/A converter and a current feedback output
Control
buffer (140Mhz Bandwidth,
2500 V/s Slew-Rate)
Block
Active Technologies - RIFLE presentation - October 2003
DAC
Waveform generators
Top
• Bottom
Output buffer performances:
•
•
•
•
•
Output voltage range: up to ± 13 V (trimmerable)
Maximum output current:
± 50 mA
Control
Bandwidth: 140 MHzBlock
Slew rate: 2500 V/s
Different requirements can be obtained by substituting the
output buffer or by plugging a specific generator into the
motherboard
Active Technologies - RIFLE presentation - October 2003
DAC
Waveform generators
Top
Single pulse or periodic arbitrary waveforms can be generated
Bottom
The sampling rate is programmable:
- The maximum time resolution is 10 ns (@100Mhz)
with a maximum
Control pulse duration of 327.68 s
(with a 32KBlock
sample FIFO)
- The minimum time resolution is 327.68 s with a
maximum pulse duration of 10.7 s (with the clock
signal divided by 32768)
Active Technologies - RIFLE presentation - October 2003
Waveform generator synchronization

RIFLE has advanced synchronization capabilities to keep the timing
requirements of the DUT and to synchronize all its data acquisition
and generation circuits:

All generators can be simultaneously triggered

All generators can be triggered by external events

Waveforms can be arbitrarily and mutually delayed


3 specific waveform generators have the alternative function of
synchronization generators to generate the trigger events for the
analog acquisition circuits or for the other arbitrary waveform generators
Analog signal acquisitions can be synchronized with the applied voltage
waveforms
Active Technologies - RIFLE presentation - October 2003
General purpose I/O
16 digital outputs and 8 digital inputs are provided
to drive the DUT internal logic circuits
Active Technologies - RIFLE presentation - October 2003
Level Translators
• All the digital signal levels are translated into
the programmable DUT power supply voltage
level to support devices with different power
requirements
• The DUT power supply can be programmed from
5V down to 1.2 V
• The DUT power supply is provided by a 3Amps
programmable voltage
generator
Active Technologies
- RIFLE presentation - October 2003
Current Generator
A programmable Current Generator provides the
reference current required for read and verify
operations
Active Technologies - RIFLE presentation - October 2003
Direct Memory Access
A circuit called DMA is provided to measure the current
characteristics of any cell.
Both 2D or 3D characteristic can be evaluated.
Active Technologies - RIFLE presentation - October 2003
Direct Memory Access
I
I/V Converters
Switch Matrix
Data Bus
Voltage
Generator
A/D
A/D
By means of a switch matrix two data bus
lines are selected and a voltage is applied by
means of a voltage generator
Active Technologies - RIFLE presentation - October 2003
Direct Memory Access
I
I/V Converters
Switch Matrix
Data Bus
Voltage
Generator
A/D
A/D
The currents supplied on these lines are converted into
voltages and then digitized in parallel by two 12 bit
ADCs with a 2.5s conversion time
Active Technologies - RIFLE presentation - October 2003
Direct Memory Access
I
I/V Converters
Switch Matrix
Data Bus
Voltage
Generator
A/D
A/D
The trigger command can be generated by means of a
synchronism generator so that the acquisition can start at any
desired and synchronized time
Active Technologies - RIFLE presentation - October 2003
Power Zero
RIFLE has a circuit called Power Zero that performs
synchronized high speed current waveform measurements
on any DUT signal
Active Technologies - RIFLE presentation - October 2003
Power Zero
control signals
Switch Matrix
Video Diff. Amp.
ADC
By means of a switch matrix any DUT
signal (power supply included) can be
selected and connected to the PW0 unit
Active Technologies - RIFLE presentation - October 2003
FIFO
Power Zero
A pulse generator applies a waveform on
the selected device pin
control signals
Switch Matrix
Pulse Generator
Video Diff. Amp.
ADC
Active Technologies - RIFLE presentation - October 2003
FIFO
Power Zero
control signals
Switch Matrix
Pulse Generator
A high speed differential
Amplifier reads the voltage
drop across a sensing
resistance
due
to
the
current flowing
Video Diff. Amp.
ADC
Active Technologies - RIFLE presentation - October 2003
FIFO
Power Zero
control signals
Switch Matrix
Pulse Generator
Third
state
Video Diff. Amp.
ADC
Any pin of the DUT can also be connected to
an alternative voltage generator
Active Technologies - RIFLE presentation - October 2003
FIFO
Power Zero
control signals
Switch Matrix
Pulse Generator
Video Diff. Amp.
ADC
The current waveform is then sampled at up to
40Msps by a 10 bit A/D converter
Active Technologies - RIFLE presentation - October 2003
FIFO
Power Zero
control signals
Switch Matrix
Pulse Generator
Video Diff. Amp.
ADC
FIFO
The samples are stored in a FIFO memory
(4Ksample deep)
Active Technologies - RIFLE presentation - October 2003
Power Zero
control signals
Switch Matrix
Pulse Generator
Video Diff. Amp.
ADC
FIFO
The current waveform conversion and storing can be triggered by means of a
synchronism generator so that the waveform acquisition can start at any
desired time, synchronously with the applied pulse
Active Technologies - RIFLE presentation - October 2003
Calibration
The hardware calibration is made during the first factory
system testing and doesn’t need any user intervention.
A further software fine calibration can be periodically
executed by the user.
By means of a dedicated calibration board and a
multimeter, the user can adjust both the offset and gain
errors of all analog circuits following the step by step
procedure of the calibration software provided with the
calibration board.
Active Technologies - RIFLE presentation - October 2003
End of Section
Make your choice by using the PC mouse
Index page
End of presentation
Active Technologies - RIFLE presentation - October 2003
Performances
Current unit resolutions and full-scales
DMA current measurement unit:
2 full-scales: ±500 A, 12 bit resolution
± 50 A, 12 bit resolution
Active Technologies - RIFLE presentation - October 2003
Performances
Current unit resolutions and full-scales
PW0 current measurement unit:
3 full-scales:
 500 A, 10 bit resolution
 5 mA, 10 bit resolution
 50 mA, 10 bit resolution
Active Technologies - RIFLE presentation - October 2003
Performances
Current unit resolutions and full-scales
Current generator:
2 full-scales:
 600 A, 12 bit resolution
 60 A, 12 bit resolution
Active Technologies - RIFLE presentation - October 2003
Performances
Time requirements (examples)
The time requirements for standard
operations strongly depend on device
speed and bandwidth
Time limitations are usually imposed by
the device itself
The following time requirements refer to a
8.6 Mbit sector of a commercial device
Active Technologies - RIFLE presentation - October 2003
Performances
Time requirements (examples)
Minimum read cycle (@32 bit bus width, 0 wait-states):
4 clock periods  200 ns (@20Mhz)
Active Technologies - RIFLE presentation - October 2003
Performances
Time requirements (examples)
Programming:
1 sector (8.6 Mcells), with verify, 1 single pulse
applied to each cell, 8bit parallelism: 1.9 s
Active Technologies - RIFLE presentation - October 2003
Performances
Time requirements (examples)
Erasing:
8.6 Mcells sector, with verify, 1 pulse applied: 1.20 s
Active Technologies - RIFLE presentation - October 2003
Performances
Time requirements (examples)
Threshold Voltage Distributions
with 20 resolution levels: 18 s
Active Technologies - RIFLE presentation - October 2003
Performances
Time requirements (examples)
Threshold Voltage Maps
with 20 resolution levels: 1’ 29 s
Active Technologies - RIFLE presentation - October 2003
Performances
Time requirements (examples)
Criterion based subset identification:
identification of 1000 cells complying with a
particular requirement (i.e., the lowest, the
highest, etc.): 40.1 s
Active Technologies - RIFLE presentation - October 2003
Performances
Time requirements (examples)
Vth tracking for subset of cells:
threshold voltage measure of the identified
1000 cells : 5.4 s
Active Technologies - RIFLE presentation - October 2003
End of Section
Make your choice by using the PC mouse
Index page
End of presentation
Active Technologies - RIFLE presentation - October 2003
Software
Architecture
The
instrument
software
is
hierarchically organized to hide
the implementation details and, by
means of different programming
languages, to create a powerful
and easy to use environment
RIFLE
instrument
Active Technologies - RIFLE presentation - October 2003
Software
Instrument Driver
System Level Interface:
Virtual Device Driver
RIFLE
instrument
At the lowest level, just above the
hardware, there is the instrument
driver.
It belongs to the PC Operating
System and it must not be
modified by the user. It’s written
in “C” and assembler languages.
Active Technologies - RIFLE presentation - October 2003
Software
API
Application Program Interface:
Dynamic Link Libraries
System Level Interface:
Virtual Device Driver
At a higher layer we find the API.
It’s a library of functions that
work as an interface between the
driver routines and the higher
level programming languages.
Also this layer must not be
modified by the user.
RIFLE
instrument
Active Technologies - RIFLE presentation - October 2003
Software
Chip Dependent Interface
Chip Dependent Interface:
Dynamic Link Libraries
Application Program Interface:
Dynamic Link Libraries
This is the first layer that can be
modified by the user.
It consists of a library of functions
specific for the DUT.
It’s written in “C” or “C++” to
achieve high efficiency and must
be implemented for any new
device.
System Level Interface:
Virtual Device Driver
RIFLE
instrument
Active Technologies - RIFLE presentation - October 2003
Software
High Level Program Interface:
LabVIEW Virtual Instrument Libraries
Chip Dependent Interface:
Dynamic Link Libraries
Application Program Interface:
Dynamic Link Libraries
High level Program Interface
The High Level Program Interface
is written in the “G” language of
the National Instrument LabVIEW
program.
At this level, by means of several
panels, the user can control any
instrument operation, execute
measurements and graphically
analyze data.
System Level Interface:
Virtual Device Driver
RIFLE
instrument
Active Technologies - RIFLE presentation - October 2003
High level software structure
Any measurement can be set up and launched in a
completely graphical environment developed under
the National Instruments LabVIEW platform
Active Technologies - RIFLE presentation - October 2003
Executing standard measurements
By means of a navigator window it is possible to
set up the parameters for any measurement
(program, erase, IV measures, distributions and
maps, stresses, ..), to browse among 2D and 3D
maps and distributions of threshold voltages or
current gains, 2D and 3D I-V characteristics
Active Technologies - RIFLE presentation - October 2003
End of Section
Make your choice by using the PC mouse
Index page
End of presentation
Active Technologies - RIFLE presentation - October 2003
Scientific references
RIFLE has been extensively used for research
purposes at the Università di Ferrara
Several papers have been published on
international journals or presented at
international conferences thanks to RIFLE
A list of paper published on int. journals is
here reported
Active Technologies - RIFLE presentation - October 2003
Scientific references
P. Pellati et al, “Automated Test Equipment for Research on Nonvolatile Memories”
IEEE Trans. Instrum. Meas. vol. 50, p. 1162, Oct. 2001
A. Chimenton et al, "Threshold voltage spread in Flash memories under a constant
DQ erasing scheme", Microelectronic Engineering, vol. 59, p. 109, Nov. 2001
A. Chimenton et al. "Analysis of Erratic Bits in Flash Memories", IEEE Trans. on
Device and Materials Reliability, vol. 1, p. 179, Dec. 2001
G. Cellere et al., "Radiation Effects on Floating-Gate Memory Cells", IEEE Trans. on
Nucl. Sc., vol.48, p. 2222, Dec 2001
A. Chimenton et at, "Constant Charge Erasing Scheme for Flash Memories", IEEE
Trans. on Electron Devices, vol. 49, p. 613, Apr.2002
G. Cellere et al., "Anomalous charge loss from Floating-Gate Memory Cells due to
heavy ions irradiation", IEEE Trans. on Nucl. Sc., vol. 49, p. 3051, Dec. 2002
Active Technologies - RIFLE presentation - October 2003
Scientific references
A. Chimenton et al., "Erratic bits in Flash Memories under Fowler-Nordheim
programming", Jpn. J. Appl. Phys., vol. 42, p. 2041, April 2003
A. Chimenton et al., "Flash Memory Reliability: an Improvement Against Erratic
Erase Phenomena Using the Constant Charge Erasing Scheme", Jpn. J. Appl.
Phys., vol. 42 , p. 2025, Apr. 2003
A. Chimenton et al., "An Insight Into Flash Memory Reliability: Erratic, Fast and
Tail bits", Proceedings of the IEEE, Vol. 91, p. 617 - 626, Apr. 2003
A. Chimenton et al., “Erratic Erase in Flash Memories (part I): Basic Experimental
and Statistical Characterization” IEEE Trans. on Electron Devices, Vol. 50, p. 1009,
Apr. 2003
A. Chimenton et al., “Erratic Erase in Flash Memories (part II): Dependence on
Operating Conditions” IEEE Trans. on Electron Devices, Vol. 50, p. 1015, Apr. 2003
Active Technologies - RIFLE presentation - October 2003
End of Section
Make your choice by using the PC mouse
Index page
End of presentation
Active Technologies - RIFLE presentation - October 2003
Role of AT and N-plus-T

RIFLE production
Service and maintenance
Test head design and production

RIFLE commercialization


Active Technologies - RIFLE presentation - October 2003
Role of AT and N-plus-T
&



Training
Software upgrade
Driver design
Active Technologies - RIFLE presentation - October 2003
End of Section
Make your choice by using the PC mouse
Index page
End of presentation
Active Technologies - RIFLE presentation - October 2003
The staff of Active Technologies
thanks you for your kind
attention
www.activetechnologies.it
[email protected]
Active Technologies - RIFLE presentation - October 2003
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RIFLE: a Research Instrument for FLash Evaluation