Slovak University of Technology
Faculty of Material Science and Technology in Trnava
THE PROGRAMMABLE
LOGIC CONTROLLER
Programmable Logic Controller (PLC)

PLCs have been gaining popularity on the factory
floor is because of the advantages they offer:
 Cost
effective for controlling complex systems.
 Flexible and can be reapplied to control other systems
quickly and easily.
 Computational abilities allow more sophisticated
control.
 Trouble shooting aids make programming easier and
reduce downtime.
 Reliable components make these likely to operate for
years before failure.
A PLC illustrated with relays
Origins of Ladder Diagram




The Ladder Diagram (LD) programming language originated from
the graphical representation used to design an electrical control
system
 Control decisions were made using relays
After a while Relays were replaced by logic circuits
 Logic gates used to make control decisions
Finally CPUs were added to take over the function of the logic
circuits
 I/O Devices wired to buffer transistors
 Control decisions accomplished through programming
Relay Logic representation (or LD) was developed to make program
creation and maintenance easier
 Computer based graphical representation of wiring diagrams that
was easy to understand
 Reduced training and support cost
Origins of Ladder Diagram
CPU
What is a Rung?

A rung of ladder diagram code can contain both
input and output instructions
 Input
instructions perform a comparison or test and
set the rung state based on the outcome

Normally left justified on the rung
 Output
instructions examine the rung state and
execute some operation or function


In some cases output instructions can set the rung state
Normally right justified on the rung
Input Instruction
Output Instruction
Series Vs Parallel Operations


Ladder Diagram input instructions perform logical AND and
OR operations in and easy to understand format
 If all Input Instructions in series must all be true for
outputs to execute (AND)
 If any input instruction in parallel is true, the outputs will
execute (OR)
Paralleling outputs allows multiple operations to occur based
on the same input criteria
A
B
OR
D
C
AND
E
F
Branches
IF ((A OR B) AND (NOT C) AND D) THEN E=1; F=1 END_IF
Ladder Logic Execution
Rungs of Ladder diagram are solved from
Left to right and top to bottom
 Branches within rungs are solved top left
to bottom right Ladder Rung

Left Power Rail
A
D
E
B
Branch
F
I
G
H
P
S
J
K
R
Right Power Rail
Non Retentive Coils

The referenced bit is reset when processor power
is cycled
 Coil -( ) Sets a bit when the rung is true(1) and resets the bit when the
rung is false (0)
 PLC5 calls this an OTE Output Enable
 Negative coil -( / ) Sets a bit when the rung is false(0) and resets the bit when the
rung is True(1)
 Not commonly supported because of potential for confusion
 Set (Latch) coil -(S) Sets a bit (1) when the rung is true and does nothing when the
rung is false
 Reset (Unlatch) Coil -(R) Resets a bit (0) when the rung is true and does nothing when the
rung is false
Contacts

Normally Open Contact -| | Enables
the rung to the right of the instruction if the rung
to the left is enabled and underlining bit is set (1)

Normally Closed Contact -|/| Enables
the rung to the right of the instruction if the rung
to the left is enabled and underlining bit is reset (0)

Positive transition contact -|P| Enables
the right side of the rung for one scan when the
rung on left side of the instruction is true
 Allen Bradley PLC5 uses -[ONS]
Negative transition contact -|N| Enables
the right side of the rung for one scan when the
rung on left side of the instruction is false
Retentive Vs Non-retentive Operation

Definitions
 Retentive
values or instructions maintain their last state
during a power cycle
 Non-retentive values or instructions are reset to some
default state (usually 0) after a power cycle

IEC1131 permits values to be defined as retentive
 A contradiction
to this is ladder diagram where 3
instructions are classified as retentive
 In most PLCs only timer and coil instructions operate as
non-retentive
Retentive Coils

The referenced bit is unchanged when
processor power is cycled
 Retentive

Sets a bit when the rung is true(1) and resets the bit when
the rung is false (0)
 Set


Retentive (Latch) coil -(SM)-
Sets a bit (1) when the rung is true and does nothing when
the rung is false
PLC5 uses OTL Output Latch
 Reset


coil -(M)-
Retentive (Unlatch) Coil -(RM)-
Resets a bit (0) when the rung is true and does nothing when
the rung is false
PLC5 uses OUT Output Unlatch
Transition Sensing Coils

Positive transition-sensing coil -(P) Sets
the bit bit (1) when rung to the left of the
instruction transitions from off(0) to on(1)
 The bit is left in this state
 PLC5 use OSR (One Shot Rising)

Negative transition-sensing coil -(N) Resets
the bit (0) when rung to the left of the
instruction transitions from on(1) to off(0)
 The bit is left in this state
 PLC5 uses OSF (One Shot Falling)
IEC Comparison Instructions in Ladder


If the rung input (EN) is enabled, the instruction performs
the operation and sets the rung output (ENO) based on
the comparison
 Example: when EN is true, EQ (=) function compares
In1 and to In2 and sets ENO
Comprehensive instruction set
 EQ(=), GT (>), GE (>=), LT (<), LE (<=), NE (<>)
EQ
EN
Tank1_Level
IN1
100.000
Tank_max
IN2
78.251
ENO
Timers in Ladder Diagram

There three timer instructions in
IEC1131
Pump_Tmr

TP - Pulse timer
 TON - Timer On Delay
 TOF - Timer Off Delay

Time values
TON
T#200ms
IN
Q
PT
ET
178

Time base is 1msec (1/1000 of a
sec)
 Values entered using duration literal
format

Pump_Tmr
Two possible visualizations
Depending on use of EN/ENO
TON

1st method requires extra
programming if timer done status
needs to be referenced on other
rungs
 2nd method sets a bit with Q which
can be referenced by other logic,
ENO=EN
IN
ENO
Q
T#200ms
PT
ET
Pump_Tmr_DN
178
Timer Operation




IN = Rung input
condition
Q = Comparison output
results
 Varies with timer
types
PT = Preset Time
ET = Elapse Time
Pulse (TP) Timing
IN
Q
ET
PT
|
0
On-Delay (TON) Timing
IN
Q
ET
PT
|
0
Off-Delay (TOF) Timing
IN
Q
ET
PT
|
0
Counters in Ladder Diagram

There three counter
instructions in IEC1131
Load_Cnt
CTU

CTU - Count Up Counter
 CTD - Count Down Counter
 CTUD - Count Up/Down Counter


All three count rung
transitions
Two possible visualizations
Depending on use of
EN/ENO
200
IN
ENO
R
Q
PV
CV
178
Load_Cnt

1st method requires extra
programming if timer done status
needs to be referenced on other
rungs
 2nd method sets a bit with Q
which can be referenced by other
logic, ENO=EN
Load_Cnt_DN
CTU
IN
Q
R
200
PV
CV
178
Counter Operation

Parameters
 CU/CD = Count up/Down
 Q/QU/QD = Comparison
Output
 R = Reset to Zero
 LD = Load CV with PV
 PV = Preset Value
 CV = Count Value
Count Up (CTU) Counter
IN
PV
CV 0|
R
Count Down (CTD) Counter
...
...
IN
Q
QD
PV
CV |
0
R
LD
...
Q
Count Up/Down (CTUD) Counter
CU
QU
CD
...
PV
|
CV 0
LD
...
...
Execution Control Elements

Jump / Label Instructions




Jump to a label skips a
block of code without it
being scanned
LBL - Named target for a
jump operation
JMP - Performs a jump
when the rung conditions
are true
|
Skip_Calc |
|-| |-------------(JMP)--|
| ...
|
| Skip_Calc
|
|---[LBL]---...
CALL / RETURN Instructions
 Used to encapsulate logic and
call it as a subroutine
 Causes execution to change
between functions or
subroutines
 CAL - Passes control to
another named function
 PLC5 uses JSR
 RET - Exits a function and
returns control back to the
calling routine
CAL
CAL
RET
RET
Different Instruction Presentations

The look and feel of IEC 1131-3 is somewhat different
from the 1Million+ PLC’s that Allen Bradley has running
in factories throughout the world
TON
ADD
Source A
Tank1_In
Source B
100.000
Offsetr
Destination
78.251
Tank_Level
178.251
EN
Tank1_In
100.000
Offsetr
78.251

+
(EN)
Pump_Tmr
Timer
Preset
200.000
Accum
178.251
(DN)
Pump_Tmr
TON
IN
ENO
Tank_Level
178.251
ENO
Q
T#200ms
PT
ET
Pump_Tmr_DN
178
IEC places the input parameters on the outside of the
instruction block vs the PLC5 where they are presented
inside of the block
Extending the IEC1131-3 Instruction Set

IEC1131-3 Provides a very basic set of instructions to do simple operations
(81 Ladder Diagram Instructions)












Data Type Conversion - Trunc, Int_to_Sint, Dint_to_Real, Bcd_To_Int …
Boolean Operations - Bit Test, Bit Set, One Shot, Semaphores …
Timers / Counters - Ton, Tp, Ctu, Ctd, Ctud
Simple Math - Add, Sub, Mul, Div, Mod, Move, Expt
Misc. Math - Abs, Sqrt, Ln, Log, Exp, Sin, Cos, Tan, Asin, Acos, Atan
Bit Shift - Shl, Shr, Ror, Rol
Logic - And, Or, Xor, Not
Selection - Sel, Max, Min, Limit, Mux
Compare - GT, GE, EQ, LE, LT, NE
String - Len, Left, Right, Mid, Concat, Insert, Delete, Replace, Find
Control - JMP, LBL, JSR, RET
All complex operations are left to the user or vendor to define

File Operations, PID, Diagnostic, For/Nxt Loop, Search, Sort are not in IEC11313
 Extensions to the instruction set are permitted so that vendors can add
instructions that their customers need
 All vendors have defined their own set of extensions
 Rockwell Automation controllers have significantly more capability
with over 130 Ladder Instructions
PLC HARDWARE

The most essential components PLC are:

Power Supply - 24Vdc, 120Vac, 220Vac.
 CPU (Central Processing Unit) - This is a
computer where ladder logic is stored and
processed.
 I/O (Input/Output) - A number of input/output
terminals must be provided so that the PLC can
monitor the process and initiate actions.
 Indicator lights - These indicate the status of
the PLC including power on, program running,
and a fault. These are essential when
diagnosing problems.
PLC HARDWARE

Typical configurations are listed below from largest to
smallest:






Rack - A rack is often large (up to 18” by 30” by 10”) and can
hold multiple cards. When necessary, multiple racks can be
connected together. These tend to be the highest cost, but
also the most flexible and easy to maintain.
Mini - These are similar in function to PLC racks, but about
half the size.
Shoebox - A compact, all-in-one unit (about the size of a
shoebox) that has limited expansion capabilities. Lower cost,
and compactness make these ideal for small applications.
Micro - These units can be as small as a deck of cards. They
tend to have fixed quantities of I/O and limited abilities, but
costs will be the lowest.
Software - A software based PLC requires a computer with an
interface card, but
allows the PLC to be connected to sensors and other PLCs
across a network.
INPUTS FOR A PLC

Inputs for a PLC come in a few basic varieties,
the simplest are AC and DC inputs. Sourcing
and sinking inputs are also popular:


Sinking - When active the output allows current to
flow to a common ground. This is best selected
when different voltages are supplied.
Sourcing - When active, current flows from a supply,
through the output device and to ground. This
method is best used when all devices use a single
supply voltage.
INPUTS FOR A PLC
In smaller PLCs the inputs are normally
built in and are specified when purchasing
the PLC.
 For larger PLCs the inputs are purchased
as modules, or cards, with 8 or 16 inputs
of the same type on each card.
 Inputs are normally high impedance. This
means that they will use very little current.

INPUTS FOR A PLC

There are many trade-offs when deciding which type of
input cards to use.
 DC voltages are usually lower, and therefore safer
(i.e., 12-24V).
 DC inputs are very fast, AC inputs require a longer
on-time. For example, a 60Hz wave may require up to
1/60sec for reasonable recognition.
 DC voltages can be connected to larger variety of
electrical systems.
 AC signals are more immune to noise than DC, so
they are suited to long distances, and noisy
(magnetic) environments.
 AC power is easier and less expensive to supply to
equipment.
 AC signals are very common in many existing
automation devices.
PLC Input Circuits
Output Modules

External power supplies are connected to the output card
and the card will switch the power on or off for each output.
Typical output voltages are listed below, and roughly
ordered by popularity.
 120
Vac
 24 Vdc
 12-48 Vac
 12-48 Vdc
 5Vdc (TTL)
 230 Vac
PLC Output Circuits
24Vdc Output Card (Sinking)
24Vdc Output Card With a Voltage Input (Sourcing)
Relay Output Card
MEMORY TYPES
RAM (Random Access Memory) - this memory is fast, but it will
lose its contents when power is lost, this is known as
volatile memory. Every PLC uses this memory for the central
CPU when running the PLC.
ROM (Read Only Memory) - this memory is permanent and cannot
be erased. It is often used for storing the operating
system for the PLC.
EPROM (Erasable Programmable Read Only Memory) - this is
memory that can be programmed to behave like ROM, but
it can be erased with ultraviolet light and reprogrammed.
EEPROM (Electronically Erasable Programmable Read Only
Memory) - This memory can store programs like ROM. It
can be programmed and erased using a voltage, so
it
is becoming more popular than EPROMs.
MEMORY ADDRESSES
The memory in a PLC is organized by data type as shown in
Figure
PROGRAM FILES

In a PLC-5 (Allen-Bradley PLCs ) the first three
program files, from 0 to 2, are defined by default:




File 0 contains system information and should not
be changed
File 1 is reserved for SFCs.
File 2 is available for user programs and the PLC
will run the program in file 2 by default.
Other program files can be added from file 3 to 999.
Typical reasons for creating other programs are for
subroutines.
DATA FILES

Data files are used for storing different information types,
as shown in Figure
Allen-Bradley Data Types
Bit Level Addressing
Memory bits are normally indicated with a forward slash
followed by a bit number /n.
Integer Word Addressing


Entire words can be addressed as shown in Figure.
These values will normally be assumed to be 2s
compliment, but some functions may assume otherwise
Literal Data Values


Data values do not always need to be stored in memory,
they can be define literally.
Figure shows an example of two different data values
File Addressing


Sometimes we will want to refer to an array of
values, as shown in Figure.
This data type is indicated by beginning the
number with a pound or hash sign ’#’.
Indirect Addressing


Indirect addressing is a method for allowing a
variable in a data address, as shown in Figure.
The indirect (variable) part of the address is
shown between brackets ’[’ and ’]’.
Expression Data Values

Expressions allow addresses and functions to be typed
in and interpreted when the program is run.

The example in Figure will get a floating point number
from file 8, location 3, perform a sine transformation, and
then add 1.3.
An Example of Ladder Logic Functions

The basic operation is such that while input A is
true the functions will be performed.
User Bit Memory

The bit memory can be accessed with individual
bits or with integer words.
Status Bits and Words
(Allen-Bradley Micrologic )
BOOLEAN LOGIC DESIGN

Boolean Operations
The Basic Axioms of Boolean Algebra
Duality
interchange AND and OR operators, as
well as all Universal, and Null sets.
The resulting equation is equivalent to the
original.
Reverse Engineering of a Digital Circuit
KARNAUGH MAPS
KARNAUGH MAPS
KARNAUGH MAPS
Sequential Design Techniques
PROCESS SEQUENCE BITS

The steps for this design method are:






Understand the process.
Write the steps of operation in sequence and give
each step a number.
For each step assign a bit.
Write the ladder logic to turn the bits on/off as the
process moves through its states.
Write the ladder logic to perform machine functions
for each step.
If the process is repetitive, have the last step go
back to the first.
Process Sequence Bits Without Latches
TIMING DIAGRAMS

Timing diagrams can be valuable when
designing ladder logic for processes that
are only dependant on time. The basic
method is:
1. Understand the process.
2. Identify the outputs that are time dependant.
3. Draw a timing diagram for the outputs.
4. Assign a timer for each time when an output
turns on or off.
5. Write the ladder logic to examine the timer
values and turn outputs on or off.
TIMING DIAGRAMS
Description:
A handicap door opener has a
button that will open two doors.
When the button is pushed
(momentarily) the first door will
start to open immediately, the
second door will start to open 2
seconds later.
The first door power will stay
open for a total of10 seconds,
and the second door power will
stay on for 14 seconds.
Use a timing diagram to design
the ladder logic.
FLOWCHART BASED DESIGN


A flowchart is ideal for a process that has sequential
process steps.
The symbols used for flowcharts are:
FLOWCHART BASED DESIGN

The general method for constructing flowcharts is:
1. Understand the process.
2. Determine the major actions, these are drawn
as blocks.
3. Determine the sequences of operations, these
are drawn with arrows.
4. When the sequence may change use decision
blocks for branching.
A Flowchart for a Tank Filler
BLOCK LOGIC

STEP 1: Add labels to each block in the flowchart
BLOCK LOGIC
BLOCK LOGIC
BLOCK LOGIC
The ladder logic for
operation F2 is simple,
and when the start
button is pushed, it will
turn off F2 and turn on
F3.
The ladder logic for
operation F3 opens
the inlet valve and
moves to operation F4
BLOCK LOGIC
The ladder logic for operation
F4 turns off F4, and if the tank
is full it turns on F6, otherwise
F5 is turned on.
The ladder logic for operation
F5 is very similar.
The ladder logic for operation
F6 turns the outlet valve on
and turns off the inlet valve.
It then ends operation F6 and
returns to operation F2
STATE BASED DESIGN

A State based system can be described with
system states, and the transitions between those
states.
STATE BASED DESIGN
The most essential part of creating state diagrams is
identifying states. Some key questions to ask are:
1. Consider the system:
What does the system do normally?
Does the system behavior change?
Can something change how the system
behaves?
Is there a sequence to actions?
2. List modes of operation where the system is doing
one identifiable activity that will start and stop.
Keep in mind that some activities may just be to
wait.

STATE BASED DESIGN
Consider the design of a coffee vending machine.
The first step requires the identification of vending
machine states as shown in
STATE BASED DESIGN

STATES
idle - the machine has no coins and is doing
nothing,
inserting coins - coins have been entered and
the total is displayed,
user choose - enough money has been entered
and the user is making coffee selection,
make coffee - the selected type is being made,
service needed - the machine is out of coffee,
cups, or another error has occurred.
STATE BASED DESIGN
The states are then drawn in a state diagram as shown in
Basic PLC Function Categories




Combinatorial Logic
- relay contacts and coils
Events
- timer instructions
- counter instructions
Data Handling
- moves
- mathematics
- conversions
Numerical Logic
- boolean operations
- comparisons



Lists
- shift registers/stacks
- sequencers
Program Control
- branching/looping
- immediate inputs/outputs
- fault/interrupt detection
Input and Output
- PID
- communications
- high speed counters
- ASCII string functions
Move Functions


MOV(value, destination) - moves a value to a memory
location
MVM(value, mask, destination) - moves a value to a
memory location, but with a mask to select specific bits.
Mathematical Functions
Advanced Mathematical Functions
Conversions

The example function will retrieve a BCD
number from the D type (BCD) memory and
convert it to a floating point number that will be
stored in F8:2.
Statistic Functions

When A becomes true the average (AVE) conversion will
start at memory location F8:0 and average a total of 4
values. The control word R6:1 is used to keep track of
the progress of the operation, and to determine when the
operation is complete.
Block Operation Functions

A basic block function is shown in Figure 10.13. This
COP (copy) function will copy an array of 10 values
starting at N7:50 to N7:40.
Comparison Functions


Comparison functions are shown in Figure.
The example shows an EQU (equal) function that
compares two floating point numbers. If the numbers are
equal, the output bit B3:5/1 is true, otherwise it is false.
Boolean Functions

The function shown will obtain data words from bit
memory, perform and operation, and store the results in
a new location in bit memory. These functions are all
oriented to word level operations. The ability to perform
Boolean operations allows logical operations on more
than a single bit.
Boolean Function Example
Shift Register Functions
Shift Register Variations
Buffers and Stack Types
Stacks store integer words in a two ended buffer.
There are two basic types of stacks: first-on-first-out (FIFO)
and last-in-first-out (LIFO).
The Basic Sequencer Instruction

A PLC sequencer uses a list of words in memory. It
recalls the words one at a time and moves the words to
another memory location or to outputs. When the end of
the list is reached the sequencer will return to the first
word and the process begins again.
A JMP Instruction

These functions allow parts of ladder logic programs to
be included or excluded from each program scan
A Fault Recovery Program
A Timed Interrupt Program

A timed interrupt will run a program at regular intervals.
To set a timed interrupt the program in file number
should be put in S2:31. The program will be run every
S2:30times 1 milliseconds.
Immediate I/O Instructions

Input, Program and Output Scan
Immediate Inputs and Outputs
Design techniques
This state diagram shows three states with four transitions.
There is a potential conflict between transitions A and C.
The Main Program for the State Diagram
Subroutines for the States
A Modified State Diagram to Prevent Racing

Figure shows a technique that blocks race
conditions by blocking a transition out of a state
until the transition into a state is finished. The
solution may not always be appropriate.
Design cases. If-Then.

Problem: Convert the following C/Java program to ladder
logic.
void main(){
int A;
for(A = 1; A < 10 ; A++){
if (A >= 5) then A =
add(A);
}
}
int add(int x){
x = x + 1;
return x;
}
INSTRUCTION LIST PROGRAMMING

A simple example is shown in Figure using the
definitions found in the IEC standard
A Structured Text Example Program

This program counts from 0 to 10 with a loop.
PROGRAM main
VAR
i : INT;
END_VAR
i := 0;
REPEAT
i := i + 1;
UNTIL i >= 10;
END_REPEAT;
END_PROGRAM
FUNCTION BLOCK PROGRAMMING


A Simple Comparison Program.
In this program the inputs N7:0 and N7:1 are used to
calculate a value sin(N7:0) * ln(N7:1). The result of this
calculation is compared to N7:2. If the calculated value is
less than N7:2 then the output O:000/01 is turned on,
otherwise it is turned off.
Creating function blocks

Figure shows a divide function block created
using ST
The IEC 61499 Standard
A standardization project of IEC Technical
Committee 65 (TC65) to standardize the
use of function blocks in distributed
industrial-process measurement and
control systems (IPMCSs).
 Work item approved 1991; assigned to
Working Group 6 (WG6) 1993

 Experts
from USA, Germany, Japan, UK, Sweden,
France, Italy
 Also responsible for IEC 61131-3 (Programmable
Controller Languages) and 61131-8 (Programmable
Controller Language Guidelines)
Function Blocks: The Architectural Dialectic
Centralized
Programmable
Configurable
PLC
IEC 61131-3
Thesis
agility!
distributability
Function Blocks
IEC 61499
Synthesis
Antithesis
DCS
IEC 61804
Distributed
Configurable
programmability
agility!
dynamically
reconfigurable
= agile !
Common
Architecture
Reference
Model
distributed
configurable
programmable
Architectural Co-Evolution







IEC 61499
Parent organization: IEC
Working group: TC65/WG6
Goal: Standard model
(function blocks) for control
encapsulation
& distribution
Started: 10/90
Active development: 3/92
Trial period: 2001-03
Completion: 2005
Holonic Manufacturing Systems
(HMS)
 Parent organization: IMS
 Working group: HMS
Consortium
 Goal: Intelligent manufacturing
through holonic (autonomous,
cooperative) modules
 Feasibility study: 3/93-6/94
 First phase: 2/96 - 6/00
 Second phase: 6/00-6/03
Requirements
Controls architecture
Intelligent Automation architecture
Intelligent Systems: Requirements of
The IP Value-Add Chain
•Intellectual Property (IP)
•Development
•Deployment = Reuse +
Distribution + Integration
Design Patterns
+ Software Tools
Operational
Expertise
Industrial
Enterprises
Integration
Expertise
System
Intelligent
Software
Integrators
Enterprise
Components
Machine
Machine Expertise
Intelligent
Software
Vendors
Systems
Components
Intelligent
Software
Machines
Components
Device Device Intelligent
Vendors Expertise Devices
Runtime
Platforms
Software
Components
Hardware
Components
Architectural Requirements
Component-Based


Support encapsulation/protection of Intellectual Property (IP)
IP Portable across Software Tools and Runtime Platforms


Map IP modules into distributed devices
Integrate IP Modules into distributed applications





Control/Automation/Diagnostics components
Machine/Process Interface components
Communication Interface components
Human/Machine Interface (HMI) components
Software Agent ("Holonic") components


Encapsulate new types of IP
Create new IP through Functional Composition of existing IP modules
Distributed
Functionally Complete
Extendable
OPEN!
 Multiply the value of IP through widest possible deployment
 Benefits available to all market players
What is an Open Architecture?
An architecture whose functional units are capable of
exhibiting portability, interoperability and configurability:



portability: Software tools can accept and correctly interpret
library elements produced by other software tools.

interoperability: Devices can operate together to perform the
functions specified by one or more distributed applications.

configurability: Devices and their software components can be
configured (selected, assigned locations, interconnected and
parameterized) by multiple software tools.
architecture: The structure and relationship among
functional units in a system.
functional unit: An entity of hardware or software, or
both, capable of accomplishing a specified purpose.
Requirements for an Open Distributed Architecture
Project
Repository
PORTABILITY
CONFIGURABILITY
INTEROPERABILITY
Distributed intelligent devices & machines
Software
Libraries
IEC 61131-3 Function Blocks:
Component-Based Encapsulation and Reuse
BOOL
DEBOUNCE
IN
OUT
TIME
DB_TIME
BOOL
External Interface Specification
Control Algorithm Specification
ON_TMR
OFF_TMR
TON
IN
IN
IN
Q
|/|
DB_FF
PT ET
DB_TIME
SR
OFF_TMR
TON
IN
DB_TIME
Q
PT ET
S1 Q1
OUT
TON
IN
Q
(R)
PT ET
OUT
ON_TMR
R
IN
||
DB_TIME
TON
IN
Q
PT ET
OUT
(S)
IEC 61499 Basic Function Block Types:
Encapsulation and Reuse
Event inputs
Event outputs
Execution
Control
Chart
Type identifier
Algorithms
(IEC 1131-3)
Internal
variables
Input variables
Output variables
The Execution Control Chart (ECC):
An Event-Driven State Machine
EC initial state
START
1
INIT
EX
1
EC action
INIT
INIT
INITO
MAIN
EX
EXO
EC state
algorithm
event
Functional Composition and Reuse:
IEC 61499 Composite Function Block Types
Event inputs
Event outputs
Execution
Control
Type identifier
Input variables
Output variables
IEC 61499 Service Interface Function Blocks


Access to Resource functionality, e.g., I/O, HMI, comms
Modeled as sequences of service primitives per ISO TR 8509
INITO
INIT
REQ
EVENT
EVENT
CNF
EVENT
EVENT
EVENT
EVENT
BOOL
ANY
BOOL
ANY
QI
PARAMS
SD_1
:
SD_m
ANY
:
ANY
QO
STATUS
PARAMS
ANY
:
ANY
:
SD_1
:
RD_n
ANY
ANY
SD_m
resource
application
startService
PARAMS
INITO(+)
STATUS
STATUS
REQ(+)
CNF(+)
RD_1
:
RD_n
resource
INIT(+)
INITO(+)
SD_1,...,SD_m
QO
STATUS
IND(+)
writeOutputs
readInputs
startService
readInputs
RD_1,...,RD_n
STATUS
RSP(+)
RD_1,...,RD_n
SD_1,...,SD_m
writeOutputs
STATUS
INIT(-)
INIT(-)
endService
BOOL
ANY
ANY
:
ANY
(resource-initiated transactions)
INIT(+)
PARAMS
QI
RD_1
:
(application-initiated transactions)
application
EVENT
EVENT
RESPONDER
INITIATOR
BOOL
ANY
INITO
IND
INIT
RSP
t
endService
IEC 61499 Communication Service Interfaces:
Publish/Subscribe Model
EVENT
EVENT
BOOL
ANY
ANY
:
ANY
INIT
REQ
INITO
CNF
PUBLISH_m
QI
QO
PARAMS
STATUS
SD_1
EVENT
EVENT
EVENT
EVENT
BOOL
ANY
BOOL
ANY
:
SD_m
INIT
RSP
INITO
IND
SUBSCRIBE_m
QI
QO
PARAMS
STATUS
RD_1
:
RD_m
INIT(+)
PARAMS
INITO(+)
~
INIT(+)
PARAMS
INITO(+)
REQ(+)
SD_1, ..., SD_m
IND(+)
RD_1, ..., RD_m
CNF(+)
RSP(+)
EVENT
EVENT
BOOL
ANY
ANY
:
ANY
IEC 61499 Communication Service Interfaces:
Client/Server Model
EVENT
EVENT
BOOL
ANY
ANY
:
ANY
INIT
REQ
INITO
CNF
CLIENT_m_n
QO
QI
PARAMS STATUS
RD_1
SD_1
:
:
RD_n
SD_m
EVENT
EVENT
EVENT
EVENT
BOOL
ANY
ANY
:
ANY
BOOL
ANY
ANY
:
ANY
INIT(+)
PARAMS
INITO(+)
INIT(+)
PARAMS
INITO(+)
REQ(+)
SD_1, ..., SD_m
IND(+)
RD_1, ..., RD_m
CNF(+)
RSP(+)
SD_1, ..., SD_n
RD_1, ..., RD_n
Example: m=2, n=1
INIT
RSP
INITO
IND
SERVER_n_m
QI
QO
PARAMS STATUS
SD_1
RD_1
:
:
SD_n
RD_m
EVENT
EVENT
BOOL
ANY
ANY
:
ANY
IEC 61499 Distributed System Architecture
Event flow
Application
=
Function Block
Network
Data flow
Communication network
Device 1
Device 2
Device 3
Device 4
Application A
Appl. C
Application B
Controlled process/machines
System
=
Communication
Network
+
Devices
+
Process/Machines
IEC 61499 Device Architecture
Communication link(s)
Device boundary
Communication interface(s)
Resource x
Resource y
Resource z
Application A
Application C
Application B
Process interface(s)
Controlled process/machine
IEC 61499 Resource Architecture


Resource schedules & executes FB algorithms
Resource maps Communications & Process I/O Functions
to Service Interface Function Blocks
Communication functions
Local application
(or local part of distributed application)
Communication mapping
Events
Data
Service
Interface
Function
Block
Algorithms
Service
Interface
Function
Block
Process mapping
Process I/O functions
Scheduling Function
Standard Event Processing Function Blocks













E_SPLIT/E_MERGE/E_REND - Event split, merge, rendezvous
E_PERMIT - Permissive event propagation
E_SELECT - 1 of 2 (boolean) event selection
E_SWITCH - 1 of 2 (boolean) event demultiplexing
E_DELAY - Event delay (timer)
E_CYCLE - Periodic event generation
E_RESTART - Generation of COLD/WARM restart, STOP events
E_TRAIN/E_TABLE/E_N_TABLE - Finite trains of events
E_SR/E_RS/E_D_FF - Event-driven bistables
E_R_TRIG/E_F_TRIG - Event-driven rising/falling edge detection
E_SR/E_RS/E_D_FF - Event-driven bistables
E_CTU - Event-driven up-counter
See IEC 61499-1, Annex A
Conversion of IEC 61311-3 Function Blocks to 61499
Without error detection
With error detection
IEC 61499 Device Management Architecture

Separation of Concerns
 Software Tools vs. Runtime Device
 Communication Services vs. Management Services
Device Management Proxy
(in Software Toolset)
Device Management Kernel
(in Device)
Dynamic Configuration in IEC 61499:
The Device Management Service Interface
<Request ID="3" Action="CREATE" >
<FB Name="DIAG" Type="SUBL_2" />
</Request>
<Request ID="4" Action="CREATE" >
<FB Name="LOG" Type="DIAG_LOG" />
</Request>
?!
<Request ID="7" Action="CREATE" >
<Connection Source="DIAG.IND" Destination="LOG.REQ" />
</Request>
<Request ID="10" Action="WRITE" >
<Connection Source="700" Destination="LOG.W" />
</Request>
<Request ID="8" Action="CREATE" >
<Connection Source="DIAG.RD_1" Destination="LOG.SRC" />
</Request>
The IEC 61499 System Management Model
IEC 61499 Software Tool Models
IEC 61499-2: Software Tool Requirements
 Exchange
of library elements
 Information to be provided by the supplier
of library elements
 Display of declarations
 Modification of declarations
 Validation of declarations
 Implementation of declarations
 System operation, testing and maintenance
Open Distributed Systems: The IEC 61499 Solution
KEY:
Existing & Normative in IEC 61499
Existing but non-Normative in IEC 61499
Defined in Compliance Profiles
Software
Tools
Project
Repository
import
DeviceNet EDSs
Fieldbus DDs
IEC 61915
ISO 15745
ISO 10303
etc.
Libraries:
IEC 61499
PORTABILITY IEC 61131-3
XML
Standard management protocols (XML) ==>CONFIGURABILITY
Standard data transfer protocols (ASN.1)==>INTEROPERABILITY
Distributed intelligent devices & controllers
Methodology for Distributed Applications
Libraries





1.
Application
Mapping
Configuration
Obtain or develop a library of function block,
resource and device types.
2. Define and develop the application.
3. Map function block instances from the
application to distributed resources.
4. Configure devices and resources.
5. Configure communication connections, using
communication service interface function
blocks to implement the event connections and
data connections of the application across
resource boundaries
Application Example: Orange Sorter
Pneumatically
actuated
diverter
Presence/Color Sensor
Accepted product
Feed conveyor
Rejected product
Distributed Orange Sorter Application
Communication Connection
Pneumatically actuated diverter
Presence/Color Sensor
Accepted product
Feed conveyor
Rejected product
Using Libraries
Libraries
Application
Mapping
Example: process/PIDD_TANK
Configuration
A Centralized Application
Libraries
Application
Mapping
Configuration
Mapping to Distributed Devices
Libraries
Application
Mapping
Configuration
Configuring Devices (1) - Setting Parameters
Libraries
Application
Mapping
Configuration
Configuring Devices (2) - Editing Resources
Libraries
Application
Mapping
Configuration
Running the Distributed Configuration
Pattern: Local Multicast
Distributed Multicast
Local Multicast
encode
copy
decode
Local
Group
encode
decode
copy
Example: process/PIDD_TANKL
Pattern: Layered MVC (Model/View/Controller)
HMI Layer
HMI
HMI
HMI
HMI
Inter- Layer
Communication
Controller
Control Layer
Controller
actuator outputs
sensor inputs
Model
Model
Model
rendering data
Model Layer
user input
View
View
View
Inter- Layer
Communication
Inter- Layer
Communication
View Layer
Realization: Simulation => Physical Interface
HMI Layer
HMI
parameters
HMI
HMI
HMI
HMI
Inter- Layer
Communication
control
parameters
Controller
Controller
actuator outputs
sensor inputs
interface
parameters
Interface
Interface
Interface
Control Layer
Inter- Layer
Communication
Interface Layer
Physical
Connections
actuature/sensor
signals + power
Mechanism
Mechanism
Mechanism
Machine/Process Layer
Elements of the Engineering Architecture
Engineering Methodology
Sketch
Views
Animation
Models
Controllers
Diagnostics
Distribution
Physical
1. Sketch & describe the problem to be solved.
2. Develop & test Views.
3. Animate the desired operational sequences.
4. Develop & test Models.
5. Develop & test Controllers.
6. Develop & test Diagnostic & fault recovery elements.
7. Perform distribution design.
8. Integrate to physical components and systems.
An Example
Sketch
Views
Animation
Models
Controllers
Diagnostics
Distribution
Physical
View Development Framework
Sketch
Views
Models
Animation
Controllers
HMI
parameters
...
HMIElement
user
input
display
parameters
Diagnostics
Physical
HMI Layer
HMIElement
rendering
data
ViewElement
Distribution
user
input
...
rendering
data
Inter- Layer
Communication
View Layer
ViewElement
Model Development Framework
Sketch
Views
Animation
HMI
parameters
Models
Controllers
...
HMIElement
sensor
inputs
actuator
outputs
Diagnostics
HMIElement
sensor
inputs
actuator
outputs
Distribution
HMI Layer
Inter- Layer
Communication
inter-model
interactions
Model
parameters
ModelElement
user
input
display
parameters
...
rendering
data
ViewElement
Model Layer
ModelElement
user
input
...
rendering
data
ViewElement
Inter- Layer
Communication
View Layer
Physical
Controller Development Framework
Sketch
Views
Animation
HMI
parameters
Models
Controllers
...
HMIElement
Diagnostics
HMIElement
Distribution
HMI Layer
Inter- Layer
Communication
Control
parameters
control
interactions
sensor
inputs
Model
parameters
actuator
outputs
ControllerElement
sensor
inputs
actuator
outputs
Inter- Layer
Communication
inter-model
interactions
ModelElement
user
input
display
parameters
...
ControllerElement
Control Layer
...
rendering
data
ViewElement
ModelElement
user
input
...
rendering
data
ViewElement
Model Layer
Inter- Layer
Communication
View Layer
Physical
Low-Level Diagnostics
Sketch
HMI
parameters
Views
Animation
Models
...
HMIElement
Controllers
HMIElement
Diagnostics
...
Distribution
HMIElement
Physical
HMI Layer
Inter- Layer
Communication
Control
parameters
control
interactions
ControllerElement
sensor
inputs
Model
parameters
actuator
outputs
ControllerElement
sensor
inputs
actuator
outputs
inter-model
interactions
ModelElement
user
input
display
parameters
...
...
rendering
data
ViewElement
ModelElement
user
input
...
rendering
data
ViewElement
Control
Layer
Diagnostic
parameters
Inter- Layer
Communication
Model Layer
Inter- Layer
Communication
View Layer
DiagnosticElement
...
Distribution Design
Sketch
Views
Animation
...
HMIElement
Models
HMIElement
Controllers
Diagnostics
...
Physical
Distribution
HMIElement
HMI Layer
Inter- Layer
Communication
control
interactions
ControllerElement
sensor
inputs
actuator
sensor
outputs
inputs
inter-model
interactions
ModelElement
user
input
...
ControllerElement
...
rendering
data
ViewElement
ModelElement
user
input
...
actuator
outputs
rendering
data
ViewElement
Control
Layer
Diagnostic
parameters
DiagnosticElement
...
Inter- Layer
Communication
Model Layer
Inter- Layer
Communication
View Layer
Convert from local
to distributed
communications
Physical Design
Sketch
Views
HMI
parameters
Animation
Models
...
HMIElement
Controllers
HMIElement
Diagnostics
Distribution
...
HMIElement
Physical
HMI Layer
Inter- Layer
Communication
Control
parameters
control
interactions
ControllerElement
sensor
inputs
Interface
parameters
...
actuator
outputs
InterfaceElement
ControllerElement
sensor
inputs
...
actuator
outputs
InterfaceElement
Diagnostic
parameters
...
Mechanism
DiagnosticElement
...
Inter- Layer
Communication
Interface Layer
Physical
Connections
signals + power
Mechanism
Control
Layer
Substitute physical
interfaces for Models
Machine/Process Layer
Pattern: Mechatronic
HMI
parameters
HMI
HL control
parameters
HLController
HMI
HMI
HL commands
LLC
LLC
LLC
Interface
Interface
Interface
physical inputs
physical
behaviors
Partition control/diagnostic functions to:
 Use existing mechatronic devices
 Design new mechatronic devices
HLController
HL status
device
parameters
HMI
Mechanism
physical outputs
Mechanism
Mechanism
HL = High Level
LL = Low Level
Mechatronic
Element
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