EE 5324 – VLSI Design II
Part I: Introduction
Kia Bazargan
University of Minnesota
Spring 2006
EE 5324 - VLSI Design II - © Kia Bazargan
1
Section Outline
• Administrative Issues
• Semiconductor industry trends
• Chip implementation methodologies
• Design methodologies
Spring 2006
EE 5324 - VLSI Design II - © Kia Bazargan
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Section Outline
• Administrative Issues
• Semiconductor industry trends
• Chip implementation methodologies
• Design methodologies
Spring 2006
EE 5324 - VLSI Design II - © Kia Bazargan
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Administrative Issues
• Class
 Time and venue:______________________________
 Web page:
http://www.ece.umn.edu/users/kia/Courses/EE5324
 Textbook:
J. M. Rabaey, "Digital Integrated Circuits: A Design
Perspective", Prentice Hall, 2nd Ed., 2002
 CAD software:
o Cadence / HSpice / Magic?
• Grades
 40% homework and quizzes
 25% midterm – open book. Date: ______________
 35% Final exam – open book. Date: ______________
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Administrative Issues
• Personnel
 Instructor: Kia Bazargan
o Email: [email protected]
o Phone: (612) 625-4588
Office: EE/CSci 4-159
o Office hours: __________________________
 TA: ______________
o Email: ______________________________
o Phone: ___________
Office: _____________
o Office hours: ___________________
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Administrative (cont.)
• Policies
 Homework must be received before class
o 1min – 24 hours late: 50% of the grade
o > 24 hours late: 0%





Spring 2006
Zero tolerance for cheating
Collaboration OK, copying NOT OK
Include ID on all homework, exams, etc.
No extra work for extra credit
Check the class web pages regularly, the students are
responsible for checking the discussion threads and
announcements regularly
EE 5324 - VLSI Design II - © Kia Bazargan
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Online Slides
• Slides are posted on the web
 Handouts as .pdf file
 Powerpoint files provided too
o NOTE: some slides are animated (like this one)
o Click on the slide to see the animation
o Click once more.
o Note: some slides have notes! (like this one)
o Some slides contain text that is not printed in the handouts,
but animated. These are left for you to fill out in the handouts.
An example is shown below (animated: click to see)
This is a sample text, not printed, but animated
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References and Copyright
• Textbooks (only [Rab02] required)
 [WE92] N. H. E. Weste, K. Eshraghian
“Principles of CMOS VLSI Design: A System Perspective”
Addison-Wesley, 2nd Ed., 1992.
 [Rab02] J. M. Rabaey
“Digital Integrated Circuits: A Design Perspective”
Prentice Hall, 2nd Ed., 2002.
 [Par00] B. Parhami
“Computer Arithmetic: Algorithms and Hardware Designs”
Oxford University Press, 2000.
 [KL99] S. Kang, Y. Levlebici
“CMOS Digital Integrated Circuits: Analysis and Design”
McGraw-Hill, 2nd Ed., 1999.
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References and Copyright (cont.)
• Slides used:
 [©Hauck] © Scott A. Hauck, 1996-2000;
G. Borriello, C. Ebeling, S. Burns, 1995,
University of Washington
(Modified by Kia when necessary)
 [©Prentice Hall] © Prentice Hall 1995, © UCB 1996
Slides for [Rab96]
http://bwrc.eecs.berkeley.edu/Classes/IcBook/instructors.html
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What is This Course All About?
• Prerequisite
 Basic CMOS design
 Static/dynamic circuit design
 Layout / Simulation
• What is different from “VLSI Design I”?
 Higher-level of design (closer to architecture)
 Emphasis on performance, processor cores, fault
tolerance
• What is covered?




Spring 2006
Mostly arithmetic circuits
Memories
Test and testability
New issues and design techniques
EE 5324 - VLSI Design II - © Kia Bazargan
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Course Outline
• CMOS Designs
 Arithmetic & logic unit (ALU)
o Bitwise operations
o Datapath layout
 Adders
o Basic adders: carry propagation, Carry Look-ahead,
Manchester Carry Chain
o More complex adders: Carry Save Adder, Brent-Kung
o Fast adders: Carry-Select adder, Wallace tree
 Multipliers
o
o
o
o
Spring 2006
Shift/Add multiplication
Booth encoding
Multiplication by constants
Floating point multiplication
EE 5324 - VLSI Design II - © Kia Bazargan
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Course Outline (cont)
• CMOS Designs (cont)
 Shift/Rotate operations
 Memories
o Memory cells: static and dynamic
o Memory arrays: address decoders, sensors and amplifiers
• Test and testability
 Fault models
 Design techniques: scan design, built-in self-test
• New design techniques/platforms
 CORDIC algorithms
 Bit-serial computations
 [Recent circuit examples]
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Section Outline
• Administrative Issues
• Semiconductor industry trends
• Chip implementation methodologies
• Design methodologies
Spring 2006
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IC Products
• Processors
 CPU, DSP, Controllers
• Memory chips
 RAM, ROM, EEPROM
• Analog
 Mobile communication,
audio/video processing
• Programmable
 PLA, FPGA
• Embedded systems
 Used in cars, factories
 Network cards
• System-on-chip (SoC)
Spring 2006
EE 5324 - VLSI Design II - © Kia Bazargan
Images: amazon.com
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IC Product Market Shares
Source: Electronic Business
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Semiconductor Industry Growth Rates
Source: http://www.icinsight.com/ (McClean Report)
Spring 2006
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More Demand for EDA
CAE = Computer Aided Engineering
Source: http://www.edat.com/edac
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Growth in System Size
CAGR = Compound Annual Growth Rate
Source: http://www.edat.com/edac
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Example: Intel Processor Sizes
Silicon Process 1.5m
Technology
1.0m
0.8m
0.6m
0.35m 0.25m
Intel386TM DX
Processor
Intel486TM DX
Processor
Pentium® Processor
Pentium® Pro &
Pentium® II Processors
Source: http://www.intel.com/
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Section Outline
• Administrative Issues
• Semiconductor industry trends
• Chip implementation
methodologies
• Design methodologies
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Implementation Methodologies
D igital
C ircu
it Im p lem en tation AApproaches
p p roach es
Digital
Ckt
Implementation
C u stom
Custom
S em i-cu
stom
Semi
custom
C ell-B ased
S tandard C ells
C om piled C ells
M acro C ells
A rray-B ased
P re-diffused
P re-w ired
(G ate A rrays)
(F P G A )
[© Prentice Hall]
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Custom Design
• Using Magic we can
get exactly what we
want.
• However:
 Complex to design
 Takes weeks to
fabricate
 High design costs
 High overhead (nonrecurring – NRE) costs
 How do we automate
the mapping?
[© Hauck]
Spring 2006
EE 5324 - VLSI Design II - © Kia Bazargan
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Standard Cells
• Develop predefined implementations of basic gates with
standard form-factor
Spring 2006
EE 5324 - VLSI Design II - © Kia Bazargan
[© Hauck]
23
Standard Cells
• Use regular layout
• Can automate the mapping process, but
 Takes weeks to fabricate
 No economies of scale
PWR
CELL CELLCELL
1
2
3
CELL
4
CELL CELL
5
6
GND
ROUTING
Cells
PWR
CELL
7
ROUTING
CELL
8
CELL CELL
9
10
GND
Cells
ROUTING
Cells
ROUTING
PWR
CELL CELL CELL CELL CELL CELL
11
12
13
14
15
16
Cells
ROUTING
GND
[© Hauck]
Spring 2006
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Combined Standard Cell and Full Custom
Use full custom for
regular structures &
critical paths
Standard cells handle
complex logic &
non-critical logic
[© Hauck]
Spring 2006
EE 5324 - VLSI Design II - © Kia Bazargan
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Mask-Programmable Gate Array (MPGA)
• Prefabricate all but the metal layers
[© Hauck]
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Sea-of-Gates (SOG)
• Prefabricate all but the metal layers and the
contacts
[© Hauck]
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Discrete Components
• Prefabricate lots of small, simple parts. Wire
them together.
Q
D
Q
D
Q
D
D
Q
D
Q
D
Q
[© Hauck]
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Programmable Logic Devices
• Categories of prewired arrays (or fieldprogrammable devices):
 Fuse-based (program-once)
 Non-volatile EPROM based
 RAM based
• Recently:
 VPGA (Via-Programmable Gate Array)
 Structured ASIC
[© Prentice-Hall]
Spring 2006
EE 5324 - VLSI Design II - © Kia Bazargan
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Programmable Logic Devices
PLA
PROM
PAL
[© Prentice-Hall]
Spring 2006
EE 5324 - VLSI Design II - © Kia Bazargan
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Fabrication Process Revisited
• Speed up fabrication & get economies of scale by
prefabricating some layers
(a) field oxide etching
(b) p-well diffusion
n-SUBSTRATE
(d) gate oxidation
(c) field oxide etching
n-SUBSTRATE
p-WELL
n-SUBSTRATE
p-WELL
p-WELL
n-SUBSTRATE
(e) polysilicon definition
(f) p-plus diffusion
p+
n-SUBSTRATE
p-WELL
p+
n-SUBSTRATE
n+
n+
p-WELL
p-WELL
p+
n+
n+
p-WELL
(j) metalization
p+
n-SUBSTRATE
Spring 2006
p+
n-SUBSTRATE
(i) contact cuts
p+
n-SUBSTRATE
(h) oxide growth
(g) n-plus diffusion
p+
p+
n+
n+
p-WELL
p+
p+
n-SUBSTRATE
EE 5324 - VLSI Design II - © Kia Bazargan
n+
n+
p-WELL
[© Hauck]
31
Programming Technologies
• Mask-programmed
• Antifuse
Polysilicon
Field
Oxide
N+ diffusion
ONO
Dielectric
access gate
• EPROM
• EEPROM
floating gate
n+ source
n+ drain
P-Type Silicon
Write
~Q
• SRAM
Q
[© Hauck]
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RAMs, ROMs
• Given a RAM/ROM with 8k memory locations, in
1k*8bit organization
 10 address lines
 Can implement 8 arbitrary 10-input functions (but
inefficiently)
I1
I2
I3
ROM
000
001
010
011
100
101
110
111
A B C D E F G H
[© Hauck]
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Field Programmable Gate Arrays (FPGAs)
• Logic cells embedded in a
general routing structure
• Logic cells usually contain:
 5-input function calculator
 Flip-flops
• All features electronically
(re)programmable
RAM RAM
RAM RAM
RAM RAM
M RAM RAM
AM RAM RAM
[© Hauck]
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Multi-Mode Systems
Tektronix PhaserCard printer controllers
Different configurations for different printers
Andromeda Systems disk controller
Field upgrades performed by modem
Radius pivoting monitor
Different configurations for
landscape & portrait
ROM
FPGA
Honeywell tape drive
Different configurations for
read & write operations
Config1
Config2
Config3
Config4
[© Hauck]
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Microprocessors & Microcontrollers
• Microcontrollers are simple 1-chip computers
optimized for embedded control
• Cheap, ubiquitous, can handle complex control
flow (relatively slowly)
CPU
RAM
I/O
ROM
Sensor
Actuator
[© Hauck]
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Digital Signal Processors (DSPs)
• Fast multiply-accumulate for signal filtering, etc.
REGISTER
MUX
MULTIPLIER
REGISTER
PC
PROGRAM
CONTROLLER
Address
REGISTER
MUX
Address
MUX
PROGRAM
ROM
SHIFTER
DATA
RAM
ALU
Program
Bus
ACCUMULATOR
I/O
CONTROLLER
SHIFTER
Data Bus
[© Hauck]
Spring 2006
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Digital Logic Implementation Alternatives
Full Custom
PWR
CELL CELL CELL
1
2
3
CELL
4
CELL CELL
5
6
GND
Standard Cells
PWR
CELL
7
CELL
8
CELL
9
CELL
10
GND
Gate Arrays
Field-Programmable Gate Arrays (FPGAs)
i1 i2 i3 i4 i5 i6
Programmable Logic Devices
o1
Discrete Components
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To Probe Further...
• D. G. Chinnery and K. Keutzer,
“Closing the Gap Between ASIC and Custom: An
ASIC Perspective”, Design Automation Conference
(DAC), pp. 637-642, 2000.
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EE 5324 - VLSI Design II - © Kia Bazargan
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Section Outline
• Administrative Issues
• Semiconductor industry trends
• Chip implementation methodologies
• Design methodologies
Spring 2006
EE 5324 - VLSI Design II - © Kia Bazargan
40
IC Design Steps (cont.)
Specifications
Spring 2006
High-level
Description
Structural
Description
Behavioral
VHDL, C
Structural
VHDL
EE 5324 - VLSI Design II - © Kia Bazargan
Figs. [©Sherwani]
41
IC Design Steps (cont.)
High-level
Description
Specifications
Physical
Design
Placed
& Routed
Design
Packaging
Spring 2006
Structural
Description
Synthesis
Technology
Mapping
Gate-level
Design
Fabrication
EE 5324 - VLSI Design II - © Kia Bazargan
Logic
Description
X=(AB*CD)+
(A+D)+(A(B+C))
Y = (A(B+C)+AC+
D+A(BC+D))
Figs. [©Sherwani]
42
IC Design Steps (cont.)
High-level
Description
Specifications
Physical
Design
Placed
& Routed
Design
Packaging
Spring 2006
Structural
Description
Synthesis
Technology
Mapping
Gate-level
Design
Logic
Description
Fabrication
EE 5324 - VLSI Design II - © Kia Bazargan
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The Big Picture: IC Design Methods
Design
Methods
Cost /
Development
Time
Quality
% Companies
involved
Full Custom
Standard Cell
Library Design
ASIC – Standard
Cell Design
RTL-Level Design
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Optimization: Levels of Abstraction
• Gate-level
 Reduce fan-out, capacitance
 Gate duplication, buffer insertion
• Layout
 Move transistors driven by late
inputs closer to the output
Spring 2006
EE 5324 - VLSI Design II - © Kia Bazargan
Level of detail
 Encoding data, computation
scheduling, balancing delays of
components, etc.
Effectiveness
• Algorithmic
45
Where Is This Course in the Big Picture?
• VLSI related courses:
VLSI CAD
EE 5301
VLSI Design
EE 5323
VLSI Design
Automation I
VLSI Design I
EE 5302
EE 5324
VLSI Design
Automation II
VLSI Design II
EE 5333
Analog
Integrated Circuit
Design
Spring 2006
EE 5324 - VLSI Design II - © Kia Bazargan
Others
EE 4301
Digital Design
With Programmable
Logic
EE 5329
VLSI Digital
Signal Processing
Systems
EE 5549
Digital
Signal Processing
Structures for VLSI
46
Full Custom Design
Structural/RTL Description
Component Design
Ctrl
Mem
Reg
File
Comp.
Unit
Place & Route
I/O
...
PLA
comp
RAM
A/D
Floorplan [©Sherwani]
Layouts [© Prentice Hall]
Spring 2006
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ASIC Design
HDL Programming
Structural/
RTL Description
P_Inp: process (Reset, Clock)
begin
if (Reset = '1') then
sum <= ( others => '0' );
input_nums_read <= '0';
sum_ready <= '0';
Ctrl
Mem
Reg
File
Comp.
Unit
add82 : kadd8 port map (
a => add_i1, b => add_i2,
ci => carry, s => sum_o);
Mult_i1 <= sum_o(7 downto 0);
D
C
Spring 2006
B
C
A
D
C
C
C
C
C
D
C
B
B
Cell library
A
C
B
D
EE 5324 - VLSI Design II - © Kia Bazargan
Floorplan [©Sherwani]
48
More Issues to Consider
• Area/speed trade-off
• Power consumption a new factor
static
mirror
look-ahead
manchester
bypass
60
select
Area (mm2)
80
tp(sec)
0.4
40
select
look-ahead
20
0 0
static
bypass
mirror
0.2
manchester
10
20
0
0
N
10
20
N
[© Prentice Hall]
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More Issues to Consider (cont.)
• Aspect ratio, area budgets, datapath layout
• Power and clock grid
Wires (M1)
Signal wires (M2)
GND
Well
VDD
Signal wires (M2)
Control wires (M1)
Well
GND
Figures:
[© Prentice
Hall]
GND
Approach I —
Signal and power lines parallel
Spring 2006
GND
VDD
Approach II —
Signal and power lines perpendicular
EE 5324 - VLSI Design II - © Kia Bazargan
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Datapath Layout Example: Adder
Standard cell layout
Bit-slice cell layout
[WE92] p.521
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Architecture of a CPU
Flags:
overflow,
zero, etc.
Control
Read/write
Mem
Spring 2006
Register
File
Data path
EE 5324 - VLSI Design II - © Kia Bazargan
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Arithmetic and Logic Unit (ALU)
• Functions
 Arithmetic (add, sub, inc, dec)
 Logic (and, or, not, xor)
 Comparison (<, >, <=, >=, !=)
• Control signals
 Function selection
 Operation mode (signed, unsigned)
• Output
 Operation result (data)
 Flags (overflow, zero, negative)
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Simple ALU Example
Bit 3
Bit 2
Bit 1
Data Out
Multiplexer
Shifter
Adder
Register
Data in
Control
Bit 0
Tile identical processing elements
[© Prentice Hall]
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EE 5324 – VLSI Design II
Part I, Appendix: FPGA Architectures
Kia Bazargan
University of Minnesota
Spring 2006
EE 5324 - VLSI Design II - © Kia Bazargan
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FPGA Architecture - Layout
• Island FPGAs
 Array of functional units
 Horizontal and vertical routing
channels connecting the
functional units
 Versatile switch boxes
 Example: Xilinx, Altera
• Row-based FPGAs
 Like standard cell design
 Rows of logic blocks
 Routing channels (fixed width)
between rows of logic
 Example: Actel FPGAs
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FPGA Architecture: Functional Units
• Functional units
 RAM blocks (Xilinx):
implement function truth table
Address
lines
(input)
output
 Multiplexers (Actel):
build Boolean functions using
muxes
 Logic gates, flip-flops:
Such as carry chains. Used for
high-performance
computations
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Programmable Switch Elements
• Used in connecting:
 The I/O of functional units
to the wires
 A horizontal wire to a
vertical wire
 Two wire segments to
form a longer wire
segment
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Programmable Switch Elements: Implementation
• SRAM connected to the
gate of a transistor
(Xilinx)
symbol
implementation
symbol
implementation
• Fuse / Anti Fuse (Actel)
Note: Switches degrade the
signals  slow down
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Routing Channels
• Note: fixed channel widths (tracks)
• Should “predict” all possible connectivity
requirements when designing the FPGA chip
• Channel -> track -> segment
track
segment
channel
• Segment length?
 Long: carry the signal longer,
less “concatenation” switches, but might waste track
 Short: local connections, slow for longer connections
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Routing Channels (cont.)
• Segment offset?
• Hierarchy?
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Switch Boxes
• Ideally, provide switches
for all possible connections
• Trade-off:
 Too many switches:
o Large area
o Complex to program
 Too few switches:
o Cannot route signals
One possible
solution
Spring 2006
EE 5324 - VLSI Design II - © Kia Bazargan
Xilinx 4000
62
Operation Example
• 4-bit ripplecarry adder
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Programming
• How to access all programmable elements?
 Pin limitation
- Chain all config bits in a shift register or
use pipelining
- Partition the elements into subsets,
treat each as a memory block
 Feasibility of access (Actel example)
- Consider the problem when designing the
FPGA architecture
- Carefully schedule the programming
• Are there “invalid” configurations?
- Yes! If two functional units drive same line
- Avoid at architectural design or when prog
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Programming (cont.)
• Too much detail!
(tens of bits for each cell/switch block)
 Automated placement, routing and programming
 Design a simple structure so that tools can handle
• Partially reconfigurable?
 Extra control circuitry, more flexibility
 Runtime reconfigurable? (avoid conflicts with running
components)
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Pros and Cons
• General architecture
 Slower than ASIC
 Less logic capacity
(solution: reuse silicon area through reconfiguration)
 Flexible
• Customization helps
 Instantiate many small processing elements
 parallel processing
 Some operations faster
(e.g., constant multiplication, bit-wise operations)
 More operations in parallel
 reduce clock speed
 reduce power consumption
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New Challenges
• Balance between elements




Data memory
Configuration memory
Special-purpose functional units
Fine- vs. coarse-grain functional units
• Communication bandwidth
• Fast automatic tools
• Versatile libraries
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