Enabling Technologies for
Reconfigurable Computing
July 8, 2002, ENST, Paris, France
Reiner Hartenstein
University of
Kaiserslautern
Enabling Technologies for
Reconfigurable Computing and
Software / Configware Co-Design
Part 3:
Resources for RC and
Data-Stream-based Computing
-
Schedule
X pu te r L a b
University of Kaiserslautern
time
slot
10.00 – 11.00
Reconfigurable Computing (RC)
11.00 – 11.30
coffee break
11.30 – 12.30
Data-Stream-based Computing
12.30 – 14.00
lunch break
14.00 – 15.00
15.00 – 15.30
Resources for RC and
Data-Stream-based Computing
Recent developments
15.30 – 16.00
Discussion
© 2002, reiner@hartenstein.de
2
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>> Configware Industry
X pu te r L a b
University of Kaiserslautern
• Configware Industry
• Terminology
• MoPL data-procedural language
• Anti architecture and circuitry
• Stream-based Memory Architecture
http://www.uni-kl.de
© 2002, reiner@hartenstein.de
3
http://kressaray.de
X pu te r L a b
Configware heading for mainstream
University of Kaiserslautern
• Configware market taking off for mainstream
• FPGA-based designs more complex, even SoC
• No design productivity and quality without
good configware libraries (soft IP cores)
from various application areas.
• FPGA vendors and a growing no.
of independent configware houses
(soft IP core vendors)
and design services .
© 2002, reiner@hartenstein.de
4
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OS for PLDs
X pu te r L a b
University of Kaiserslautern
• separate EDA software market, comparable
to the compiler / OS market in computers,
• Cadence, Mentor, Synopsys just jumped in.
• < 5% Xilinx / Altera income
from EDA software
• Alliances with hundreds of partners
providing hundreds of IP cores,
synthesizable (hopefully)
(WWW sites difficult to navigate)
© 2002, reiner@hartenstein.de
5
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>> Terminology
X pu te r L a b
University of Kaiserslautern
• Configware Industry
• Terminology
• MoPL data-procedural language
• Anti architecture and circuitry
• Stream-based Memory Architecture
http://www.uni-kl.de
© 2002, reiner@hartenstein.de
6
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Terminology
X pu te r L a b
University of Kaiserslautern
P latfo rm
P ro g ram m in g
so u rce
“vo n N eu m an n ”
H a rd w a re
S o ftw a re
S o ft M ach in e (w .
so ft d atap ath s)
C oarse grain
high level
F le x w a re
C o n fig w a re
P arad ig m
R L (F P G A etc.)
© 2002, reiner@hartenstein.de
fine grain F le x w a re
7
netlist level
C o n fig w a re
http://kressaray.de
Terminology & Acronyms
X pu te r L a b
• DPU: datapath unit
•RC: reconfigurable computing• DPA: datapath array
• rDPU: reconfigurable DPU
•RL: reconfigurable logic
•
rDPA:
reconfigurable
DPA
•RA: reconfigurable array
University of Kaiserslautern
•Software (SW): procedural sources*
•Configware (CW): structural sources
•Hardware (HW): hardwired platforms
•ASIC: customizable hardwired platforms
•Flexware (FW): reconfigurable platforms
•FPGA: field-programmable gate array
•FPL: field-programmable logic
*) note: firmware is SW !
© 2002, reiner@hartenstein.de
8
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Babylonial Confusion
X pu te r L a b
University of Kaiserslautern
Communication between areas, and between
abstraction levels – mainly because of nonintuitive, misleading or ambiguos terminology
© 2002, reiner@hartenstein.de
9
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>> MoPL data-procedural language
X pu te r L a b
University of Kaiserslautern
• Configware Industry
• Terminology
• MoPL data-procedural language
• Anti architecture and circuitry
• Stream-based Memory Architecture
http://www.uni-kl.de
© 2002, reiner@hartenstein.de
10
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Fundamental Ideas available (1)
X pu te r L a b
University of Kaiserslautern
• Data Sequencer Methodology
• Data-procedural Languages (Duality with v N)
• ... supporting memory bandwidth optimization
• Soft Data Path Synthesis Algorithms
• Parallelizing Loop Transformation Methods
• Compilers supporting Soft Machines
• SW / CW Partitioning Co-Compilers
© 2002, reiner@hartenstein.de
11
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X pu te r L a b
Fundamental Ideas available (2)
University of Kaiserslautern
• Programming Xputers
• Similarities to programming computers
• How not to get confused by similarities
• What benefits vs. Computers ?
© 2002, reiner@hartenstein.de
12
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Programming Language Paradigms
X pu te r L a b
University of Kaiserslautern
language category
C om puter Languages
X puter Languages
both determ inistic
procedural sequencing: traceable, checkpointable
read next instruction,
goto (instr. addr.),
jum p (to instr. addr.),
instr. loop, loop nesting
no parallel loops , escapes,
instruction stream branching
read next data item ,
goto (data addr.),
jum p (to data addr.),
data loop, loop nesting,
parallel loops, escapes,
data stream branching
state register
program counter
data counter(s)
address
com putation
m assive m em ory
cycle overhead
overhead avoided
Instruction fetch
m em ory cycle overhead
overhead avoided
parallel m em ory
bank access
interleaving only
no restrictions
operation
sequence
driven by:
© 2002, reiner@hartenstein.de
13
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Similar Programming Language Paradigms
X pu te r L a b
University of Kaiserslautern
lang u ag e catego ry
b o th d eterm inistic
seq u en cing
d riven b y:
© 2002, reiner@hartenstein.de
C o m pu ter L an gu ag es
X p u ter L an gu ag es
p ro cedu ral seq u encing : traceab le, ch eckp oin table
read n ext in stru ction ,
g o to (in stru ction add r.),
ju m p (to in stru ction ad dr.),
in stru ction loo p,
in stru ction loo p nestin g
n o p arallel loo p s ,
in stru ction loo p escap es ,
in stru ction stream b ran ch in g
14
read n ext d ata o bject,
g o to (d ata add r.),
ju m p (to d ata ad dr.),
d ata lo op ,
d ata lo op n estin g ,
p arallel d ata lo o ps ,
d ata lo op escap es ,
d ata stream b ran ch in g
http://kressaray.de
JPEG zigzag scan pattern
*> Declarations
goto PixMap[1,1]
4
X puis
te r L a b
EastScan
University of Kaiserslautern
step by [1,0]
end EastScan;
1
SouthScan is
step by [0,1]
endSouthScan;
HalfZigZag;
SouthWestScan
uturn (HalfZigZag)
NorthEastScan is
loop 8 times until [*,1]
step by [1,-1]
2 endloop
published
in 1993
x
y
dataHalfZigZag
counter
data counter
data counter
data counter
end NorthEastScan;
SouthWestScan is
loop 8 times until [1,*]
step by [-1,1]
3 endloop
end SouthWestScan;
endloop
end HalfZigZag;
© 2002, reiner@hartenstein.de
15
HalfZigZag
HalfZigZag is
EastScan
loop 3 times
SouthWestScan
SouthScan
NorthEastScan
EastScan
http://kressaray.de
>> Anti architecture and circuitry
X pu te r L a b
University of Kaiserslautern
• Configware Industry
• Terminology
• MoPL data-procedural language
• Anti architecture and circuitry
http://www.uni-kl.de
• Stream-based Memory Architecture
© 2002, reiner@hartenstein.de
16
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X pu te r L a b
University of Kaiserslautern
GAU generic address unit Scheme
GAG = Generic
Address
Generatorc
DA
B0
[|
L0
Limit
Slider
GAU
© 2002, reiner@hartenstein.de
DA
17
|
|
]
limit
B0
Address
Stepper
A
|
L
Base
Slider
all 3 are copies
of the same BSU
stepper circuit
http://kressaray.de
BSU: Basic Stepper Unit
X pu te r L a b
University of Kaiserslautern
]
[
Base
B0
Limit
DA
B0
[|
|
|
]
|
stepVector
maxStepCount
init
tag
L
|
|
L
DA
A
Step
Counter
limit
sequencing
GAG =
Generic
Address
Generator
BSU =
Basic
Stepper
Unit
© 2002, reiner@hartenstein.de
stepper
A
Address
18
+/–
=o
Escape
Clause
End
Detect
endExec
http://kressaray.de
GAG Complex Sequencer Implementation
X pu te r L a b
University of Kaiserslautern
GAU
GAU
L0 DA B0
Limit
Slider
Address
Stepper
A
VLIW
stack
L0 DA B0
Base
Slider
Limit
Slider
Address
Stepper
GAU
A
L0 DA B0
Limit
Slider
GAG
Address
Stepper
A
Base
Slider
GAU
GAG
SDS
Base
Slider
GAU
Generic Address Generator
© 2002, reiner@hartenstein.de
19
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Generic Sequence Examples
X pu te r L a b
L0 DA B0
University of Kaiserslautern
atomic scan
Limit
Slider
linear scan
a)
video scan
b)
Address
Stepper
A
Base
Slider
GAU
-90º rotated video scan
c)
-45º rotated (mirx (v scan))
until
sheared video scan
non-rectangular video scan
zigzag video scan
d)
e)
f)
g)
spiral scan
feed-back-driven scans
perfect
shuffle
© 2002, reiner@hartenstein.de
20
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Slider Demo
B0 DA L0
X pu te r L a b
University of Kaiserslautern
Address
Stepper
Base
Slider
Limit
Slider
GAU
A
address
floor
F
c eiling
B0
DA
DB
y
DB
x
© 2002, reiner@hartenstein.de
21
L0
C
DL
DL
http://kressaray.de
X pu te r L a b
XMDS Scan Pattern Editor GUI
University of Kaiserslautern
© 2002, reiner@hartenstein.de
22
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X pu te r L a b
>> Stream-based Memory Architecture
University of Kaiserslautern
• Configware Industry
• Terminology
• MoPL data-procedural language
• Anti architecture and circuitry
• Stream-based Memory Architecture
http://www.uni-kl.de
© 2002, reiner@hartenstein.de
23
http://kressaray.de
X pu te r L a b
MoM Xputer Architecture
University of Kaiserslautern
Smart memory interface
Scan
Window
„Cache“
© 2002, reiner@hartenstein.de
rDPA
24
Multiple
RAM banks
http://kressaray.de
X pu te r L a b
Antimachine: MoM architecture
University of Kaiserslautern
H a n d le P o sitio n G en era to r
i ntra sca n w ind ow a ccesse s
scan w ind ow
y
( low l eve l se qu en cin g)
exam ple
y- GA G
x-G A G
handle position
Sc an W in d o w G e n era to r
ba nk 0 1
scan pa tte rn
(h igh level se qu e ncin g)
• •• n
m em o ry a ccesse s
x
h a nd le p osi ti on s
© 2002, reiner@hartenstein.de
25
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Linear Filter Application 11 x 22: initial
X pu te r L a b
University of Kaiserslautern
[Dissertation Michael Herz]
b)
r/ w
r
r
r
r
r
r
r
r
9 x 20 = 180
1620
w /r
r
r
B an k a
w / r
r
r
r
r
r
B an k b
r
r
r
r
r
r
r
B an k a
r
r
r
r
w
r
sca n step
© 2002, reiner@hartenstein.de
26
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Linear Filter: scanline unrolling
X pu te r L a b
University of Kaiserslautern
3 x 20 = 60
r/ w
r
r
r/ w
r
r
r/ w
r
r
r
r
r
r
r
r
900
© 2002, reiner@hartenstein.de
27
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90o Rotation of Scan Pattern
X pu te r L a b
University of Kaiserslautern
r
r
r
r
r
B an k b
r
r
r
r
r
B an k a
w
r
w
r
w
r
r
B an k b
r
w
r
w
r
w
r
B an k a
r
r
r
r
r
r
r
r
r
r
r
r
B an k b
r
r
r
r
r
r
r
r
r
r
B an k a
r
r
r/ w
r/ w
r /w
w
w
w
B an k b
r
r
r/ w
r/ w
r /w
w
w
w
B an k a
3 x 10 = 30
sca n
w i nd ow
o ver lap
a re a
600
© 2002, reiner@hartenstein.de
28
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Linear Filter Application: final
X pu te r L a b
University of Kaiserslautern
Parallelized Merged Buffer Linear Filter Application
with example image of x=22 by y=11 pixel
final design
after inner scan
line loop unrolling
after scan
line unrolling
hardw. level
access optim.
initial design
Speed-up
factor:
11,2
© 2002, reiner@hartenstein.de
29
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X pu te r L a b
MoM Application Examples
University of Kaiserslautern
• Image Processing
• Grid-based design rule check [1983*]
–
–
–
–
4 by 4 word scan cache
Pattern-matching based
Our own nMOS „DPLA“ design
design rule violation pixel map automatically
generated from textual design rules
– 256 M&C nMOS, 800 single metal CMOS
– Speed-up > 10000 vs. Motorola 68000
*) „machine“ not yet discovered
© 2002, reiner@hartenstein.de
30
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X pu te r L a b
MoM Architecture Features
University of Kaiserslautern
• Scan Cache Size adjustable at run time
• Any other shape than square supported
• 2-dimensional memory space
• Supports generic „scan patterns“
– Subject of parallel access transformations
– compare Francky Cathoor et al .
• Supports visualization
© 2002, reiner@hartenstein.de
31
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Hot Research Topic: Memory Architectures
X pu te r L a b
University of Kaiserslautern
• High Performance Embedded Memory Architectures [Cathoor et al.]
• High Performance Memory Communication Architectures [Herz]
• Custom Memory Management Methodology [Cathoor et al]
• Data Reuse Transformations [Kougia et al.]
• Data Reuse Exploration [Soudris, Wuytak]
• Rapidly greowing market: IP cores, module generators ets.
© 2002, reiner@hartenstein.de
32
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X pu te r L a b
Processor Memory Performance Gap
University of Kaiserslautern
Performance
1000
µProc
60%/yr..
CPU
100
Processor-Memory
Performance Gap:
(grows 50% / year)
10
1
1980
© 2002, reiner@hartenstein.de
DRAM
1990
2000
33
DRAM
7%/yr..
http://kressaray.de
rDPAs: classical cache does not help
X pu te r L a b
University of Kaiserslautern
• Stream-based arrays
are a memory
bandwidth problem
• super pipe networks,
no parallel computers !
• the memory bandwidth
problem is often more
dramatic then for
microprocessors
• classical interleaving is
not practicable, since
based on sequential
instruction streams
• classical caches do not
help, since instruction
sequencing is not used
• the problem: throughput
of parallel data streams,
not instruction streams
© 2002, reiner@hartenstein.de
34
http://kressaray.de
Cache does not help ....
X pu te r L a b
University of Kaiserslautern
© 2002, reiner@hartenstein.de
35
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Data-Stream-based Soft Anti Machine
X pu te r L a b
University of Kaiserslautern
Memory
(data memory)
Compiler
“instructions”
Scheduler
rDPA
memory bank
memory bank
memory bank
...
memory bank
...
memory bank
Sequencers
(data stream
generator)
© 2002, reiner@hartenstein.de
36
http://kressaray.de
X pu te r L a b
University of Kaiserslautern
The Disk Farm? or
a System On a Card?
The 500GB disc card
LOTS of bandwidth
A few disks replaced by
>10s Gbytes RAM
and a processor
[Gordon Bell,
Jim Gray,
ISCA2000]
14"
MicroDrive:1.7” x 1.4” x 0.2”
2006: ?
1999: 340 MB, 5400 RPM,
5 MB/s, 15 ms seek
2006: 9 GB, 50 MB/s ?
(1.6X/yr capacity, 1.4X/yr BW)
Integrated IRAM processor
2x height
Connected via crossbar switch
growing like Moore’s law
16 Mbytes; ; 1.6 Gflops; 6.4 Gops
10,000+ nodes in one rack!
100/board = 1 TB; 0.16 Tflops
© 2002, reiner@hartenstein.de
37
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>>> Coarse Grain
X pu te r L a b
University of Kaiserslautern
- END © 2002, reiner@hartenstein.de
38
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Appendix
X pu te r L a b
University of Kaiserslautern
APPENDIX
© 2002, reiner@hartenstein.de
39
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Alliances
X pu te r L a b
University of Kaiserslautern
•Alliances
© 2002, reiner@hartenstein.de
40
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Xilinx Alliances
X pu te r L a b
University of Kaiserslautern
• The Software
AllianceEDA Program
• ... Xilinx Inc.'s
Foundation...
• free WebPACK
downloadable tool
palette
© 2002, reiner@hartenstein.de
• The Xilinx XtremeDSP
Initiative (with Mentor
Graphics)
• MathWorks / Xilinx
Alliance.
• The Wind River / Xilinx
alliance
41
•#
http://kressaray.de
The Software Alliance EDA Program
X pu te r L a b
University of Kaiserslautern
provides a wide
selection of EDA tools
helps leading EDA
vendors to integrate
Xilinx Alliance software
tightly into their tools
© 2002, reiner@hartenstein.de
Acugen Software,
Agilent
EEsof EDA,
Aldec,
Aptix,
Auspy Development,
Cadence,
Celoxica,
Dolphin Integration,
Elanix,
Exemplar,
Flynn Systems,
Hyperlynx,
42
IKOS Systems,
Innoveda,
Mentor
Graphics,
MiroTech,
Model Technoloy,
Protel International,
Simucad,
SynaptiCAD,
Synopsys,
Synplicity,
Translogic,
Virtual Computer Corporation.
http://kressaray.de
X pu te r L a b
University of Kaiserslautern
The Xilinx AllianceCORE program
a cooperation between Xilinx and third-party
core developers, to produce a broad selection
of industry-standard solutions for use in
Xilinx platforms. - Partners are:
Amphion Semiconductor, Ltd.
ARC Cores
CAST, Inc.
DELTATEC
Derivation Systems, Inc.
Dolphin Integration (Grenoble)
Eureka Technology Inc.
Frontier Design Inc.
GV & Associates, Inc.
inSilicon Corporation
iCODING Technology Inc.
Loarant Corporation
Mindspeed Technologies
- A Conexant Business
(formerly Applied Telecom) |
© 2002, reiner@hartenstein.de
MemecCore
Mentor Graphics
Inventra
NewLogic Technologies, Inc. (Europe)
NMI Electronics
Paxonet Communications, Inc.
Perigee, LLC
Rapid Prototypes Inc.
sci-worx GmbH (Hannover, Germany)
SysOnChip
TILAB (Telecom Italia Lab)
VAutomation
Virtual IP Group, Inc.
XYLON.
43
http://kressaray.de
The Xilinx Reference Design Alliance Program
X pu te r L a b
University of Kaiserslautern
The Xilinx Reference Design Alliance Program helps
the development of multi-component reference
designs that incorporate Xilinx devices and other
semiconductors.
The designs are fully functional, but no warranties,
no liability. Partners are:.
ADI Engineering
Innovative Integration
© 2002, reiner@hartenstein.de
JK microsystems, Inc.
LYR Technologies
NetLogic Microsystems
44
http://kressaray.de
X pu te r L a b
The Xilinx University Program
University of Kaiserslautern
The Xilinx University Program provides
•
•
•
•
•
•
•
Xilinx Student Edition Software,
Professor Workshops,
a Xilinx University User Group,
Presentation Materials and Lab Files,
Course Examples,
Research,
Books, etc.
© 2002, reiner@hartenstein.de
45
http://kressaray.de
X pu te r L a b
University of Kaiserslautern
Altera offers over a hundred IP
cores like, for example:
Altera offers over a
hundred IP cores (1)
• modulator,
• synchronizer,
• DDR SDRAM controller,
• Hadamar transform,
• interrupt controller,
• Real86 16 bit microprocessor,
• floating point,
• FIR filter,
• discrete cosine,
• ATM cell processor,
• and many others.
• controller,
• UART,
• microprocessor,
• decoder,
• bus control,
• USB controller,
• PCI bus interface,
• viterbi controller,
• fast Ethernet
• MAC receiver or transmitter,
© 2002, reiner@hartenstein.de
46
http://kressaray.de
Altera offers over a
hundred IP cores (2)
X pu te r L a b
University of Kaiserslautern
from Altera |
AMIRIX Systems, Inc.
Amphion Semiconductor, Ltd.
Arasan Chip Systems, Inc.
CAST, Inc.
Digital Core Design
Eureka Technology Inc.
HammerCores
Innocor
Ktech Telecommunications, Inc.
Lexra Computing Engines
Mentor Graphics - Inventra
© 2002, reiner@hartenstein.de
47
Modelware
Ncomm, Inc.
NewLogic Technologies
Northwest Logic
Nova Engineering, Inc.
Palmchip Corporation
Paxonet Communications
PLD Applications
Sciworx
Simple Silicon
Tensilica
TurboConcept.
http://kressaray.de
Altera IP core design services
X pu te r L a b
University of Kaiserslautern
Altera IP core design
services are available
from:
• Northwest Logic
© 2002, reiner@hartenstein.de
48
http://kressaray.de
Altera Certified Design Center
X pu te r L a b
(CDC) Program
University of Kaiserslautern
Certified Design Center (CDC) Program:
•
•
•
•
•
•
•
•
Barco Silex
El Camino GmbH
Excel Consultants
Plextek
Reflex Consulting
Sci-worx
Tality
Zaiq Technologies.
© 2002, reiner@hartenstein.de
49
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The Altera Consultants
Alliance Program (ACAP):
X pu te r L a b
University of Kaiserslautern
The Altera Consultants Alliance
Program (ACAP): lists
•41 offices in North America and
•29 in the rest of the world.
© 2002, reiner@hartenstein.de
50
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Devlopment boards
X pu te r L a b
University of Kaiserslautern
Devlopment boards are offered from:
• Altera
• El Camino GmbH
• Gid'el Limited
• Nova Engineering, Inc.
• PLD Applications
• Princeton Technology Group
• RPA Electronics Design, LLC
• Tensilica.
© 2002, reiner@hartenstein.de
51
http://kressaray.de
X pu te r L a b
University of Kaiserslautern
Consultants and services not listed
by Xilinx nor Altera (index)
Algotronix, Edinburgh,
Andraka Consulting Group
Arkham Technology, Pasadena, CA
Barco Silex, Louvain-la-Neuve, Belgium,
Bottom Line Technologies, Milford, NJ
Codelogic, Helderberg, South Africa,
Coelacanth Engineering, Norwell, MASS
Comit Systems, Inc., Santa Clara, CA
EDTNProgrammableLogicDesignCenter
© 2002, reiner@hartenstein.de
Flexibilis, Tampere, Finland,
Geoff Bostock Designs, Wiltshire, England,
Great River Technology, Alberquerque, NM,
New Horizons GB Ltd, United Kingdom,
North West Logic
Silicon System Solutions, Canterbury, Australia,
Smartech, Tampere, Finland,
Tekmosv, Austin, Texas,
The Rockland Group, Garden Valley, CA
Nick Tredennick, Los Gatos, California,
Vitesse,
52
http://kressaray.de
X pu te r L a b
University of Kaiserslautern
Consultants and services not
listed by Xilinx nor Altera (1)
Algotronix, Edinburgh, Reconfigurable Computing and FPL in
software radio, communications and computer security
Andraka Consulting Group high performance FPGA designs for
DSP applications
Arkham Technology, Pasadena, low cost IP cores for Xilinx and
Atmel, embedded processor, DSP, wireless communication,
COM / CORBA / DirectX, client-server database programming,
software internationalization, PCB design
Barco Silex, Louvain-la-Neuve, Belgium, IP integration boards
for ASIC and FPGA, consultancy, design, sub-contracting
© 2002, reiner@hartenstein.de
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X pu te r L a b
University of Kaiserslautern
Consultants and services not
listed by Xilinx nor Altera (2)
Bottom Line Technologies, Milford, New Jersey, FPGA design,
training, designing Xilinx parts since 1985
Codelogic, Helderberg, South Africa, consulting, FPGA design
services
Coelacanth Engineering, Norwell, Massachusetts, design services,
test development services, in wireless communication, DSP-based
instrumentation, mixed-signal ATE
Comit Systems, Inc., Santa Clara, California, DSP, ASIC,
networking, embedded control in avionics -- FPGA / ASIC design
and system software
EDTN Programmable Logic Design Center
© 2002, reiner@hartenstein.de
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X pu te r L a b
University of Kaiserslautern
Consultants and services not
listed by Xilinx nor Altera (3)
FirstPass, Castle Rock, Colorado
Vitesse, ASIC design
Flexibilis, Tampere, Finland, VHDL IP cores for Xilinx products
Geoff Bostock Designs, Wiltshire, England, FPGA design
services
Great River Technology, Alberquerque, New Mexico, FPGA
design services in digital video and point-to-point data
transmission for aerospace, military, and commercial
broadcasters
New Horizons GB Ltd, United Kingdom, FPGA design and
training, Xilinx specialist
North West Logic; FPGA and embedded processor design in
digital communications, digital video
© 2002, reiner@hartenstein.de
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X pu te r L a b
University of Kaiserslautern
Consultants and services not
listed by Xilinx nor Altera (4)
Silicon System Solutions, Canterbury, Australia, VHDL IP
cores for the ASIC and FPGA/CPLD/EPLD markets
Smartech, Tampere, Finland, ASIC and FPGA design
Tekmosv, Austin, Texas, Multiple Designs on a Single Gate
Array, HDL synthesis, design conversions, chip debug, test
generation
The Rockland Group, Garden Valley, California, a
TeleConsulting organization about logic design for FPGAs
Nick Tredennick, Los Gatos, California, investor and
consultant
© 2002, reiner@hartenstein.de
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Terms
X pu te r L a b
University of Kaiserslautern
•Terms
© 2002, reiner@hartenstein.de
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Confusing Terminology
X pu te r L a b
University of Kaiserslautern
Computer Science and EE as well as ist R&D and applicatgion areas
suffer from a babylonial confusion.
Communication not only between Computer Science and EE, but also
between ist special areas, even between ist different abstraction
levels is made difficult – mainly because of immature terminology in
relation to reconfigurable circuits and their applications.
Terms are rarely standardized and often used with drastically
different meanings – even within then same special area.
Often terms have been so badly coined, that they are not selfexplanatory, but misleading. A demonstratory example is the
comparizon of terms used used in VHDL and Verilog.
Ideal are "intuitive" terms. But often Intuition yields the wrong idea.
Whenever a new term appears in teaching, I often have to tell the
students, that the term does not mean, what he believes.
© 2002, reiner@hartenstein.de
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.
Terms (1)
[à la Ingo Kreuz]
X pu te r L a b
University of Kaiserslautern
Term
Hardware
Flexware
Meaning
hardwired
Reconfigurable
Example
Processor, ASIC
(structurally programmable)
FPLA, FPGA,
KressArray
Firmware
Microprogramme
IBM 360 Computer Family
Software
procedural programs
Word, C, OS,
Compiler, etc.
(rarely used
after introduction of RISC proc.)
(sequentially executable by a CPU)
Configware structural programs, soft
IP cores, personalizing CPLD,
FPGA, or other Flexware
© 2002, reiner@hartenstein.de
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for rDPA FPGA
configuration, e. g. as a logic
circuit, state machine,
datapath, function
http://kressaray.de
.
Terms (2)
[à la Ingo Kreuz]
X pu te r L a b
University of Kaiserslautern
Term
Meaning
Example
data
objects of computing
“data” property
depends on the moment
of watching
data stream ordered, also parallel
data word lists,
obtained by scheduling
programming personalisation by
loading programm code
program
source text or object
code for programming
© 2002, reiner@hartenstein.de
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Bits, numbers, operands,
results, any text (also
compiler input) lists,
graphs, tables, images, ...
I/O data streams for
systolic or other arrays
procedural code or
structural code: for
(re)configuration
procedural oder structural
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.
Terms (3)
[à la Ingo Kreuz]
X pu te r L a b
University of Kaiserslautern
Term
boot program
booting
Meaning
simple program to
enable programming
- usually saved in
non-volatile memory
load and execute a
boot program
© 2002, reiner@hartenstein.de
61
Example
comparable to the
starter of the
motor of a car
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Hardware Terms (1)
[à la Ingo Kreuz]
X pu te r L a b
University of Kaiserslautern
Term
machine
Meaning
execution unit, driven by
deterministic sequencer
Example
von Neumann
machine
„dataflow
machine“
not a machine, since without (sleeping
research
a deterministic sequencer
area)
(exotic concept)
CPU
Instruction Set Processor
ARM, Pentium
("von Neumann”): program
core,
counter (instruction
sequencer) and DPU - mode of
operation: deterministically
instruction-driven
© 2002, reiner@hartenstein.de
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Hardware Terms (2)
[à la Ingo Kreuz]
X pu te r L a b
University of Kaiserslautern
Term
DPU
Meaning
data path unit, processes
operands - no CPU since without
sequencer - no maschine
Computer
Parallel
Computer
CPU with RAM and interfaces
ensemble of several Computers
Xputer
deterministically data-driven
Machine, (transport-triggered) data counter(s) used instead of a
program counterm
indeterministically data-driven
dataflow
machine
(execution sequence unpredictable)
© 2002, reiner@hartenstein.de
63
Example
ALU with
registers,
multiplexers etc.
MoM
architectures
(Kaiserslautern)
(sleeping research
area)
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Terms on Parallelism (1)
[à la Ingo Kreuz]
X pu te r L a b
University of Kaiserslautern
Term
parallelism
Meaning
several levels of parallelism
distinguished
concurrent
parallel processes run on
different CPUs of a parallel
computer - may occasionally
exchange signals or data
ISP (instruction several CPUs run in parallel
set parallelism) by clocked synchronization
© 2002, reiner@hartenstein.de
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Example
parallel processes,
parallelism at
instruction set level,
pipelines,
weather prognisis,
complex simulations,
etc.
VLIW (very long
instruction word)
computer
http://kressaray.de
[à la Ingo Kreuz]
X pu te r L a b
Terms on Parallelism (2)
University of Kaiserslautern
Term
pipelining
chaining
Pipe network
Meaning
several uniform or different
DPUs running simultaneously
- connected to a pipeline by
buffer registers.
several uniform or different
DPUs running simultaneously
- connected to a pipeline
without buffer registers
Ensemble of DPUs, also
multiple pipelines, also with
irregular or wild structures
© 2002, reiner@hartenstein.de
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Example
pipelined CPUs, pipe
networks, systolic,
etc.
Schaltnetze,
komplexe
arithmetische
Operatoren
systolisc arrays,
stream-based
computing arrays
http://kressaray.de
[à la Ingo Kreuz]
X pu te r L a b
Terms on Parallelism (3)
University of Kaiserslautern
Term
Meaning
Example
Systolic Array
Pipe network with only
linear (straight-on, no
branching), uniform
pipelines (all DPUs
hardwired and with same
functionality) pipelines
pipe network, configured
before fabrication
Matrix computation,
DSP, DNA sequencing,
etc.
stream-based arrays,
configurable after
fabrication
KressArray
stream-based
computing arrays
(super-systolic arrays)
(coarse grain)
reconf. streambased arrays
© 2002, reiner@hartenstein.de
66
image processing, DSP,
complex functions and
algorithms
http://kressaray.de
Counterparts
[à la Ingo Kreuz]
X pu te r L a b
University of Kaiserslautern
category
programing
mode
property
procedural
(classical)
counterpart
machine:
principle of
operation
controlflow-driven
(instruction-driven): v.
Neumann
system:
principle of
operation
Set-up time
(datapaths
switched thru)
instruction-flow-driven Data-stream-based (systolisc
(parallel computer etc.) array, DPU array, KressArray)
during run time;
(instruction-driven)
© 2002, reiner@hartenstein.de
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structural (synthesis, design)
- „field-programmable“, PLA
„programming“, etc.
Data-driven: Xputer machine
before run time:
FPGA (at compile time)
Gate Array (at fabrication)
http://kressaray.de
-
X pu te r L a b
University of Kaiserslautern
•© 2002, reiner@hartenstein.de
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Synthesizable Memory Communication
X pu te r L a b
University of Kaiserslautern
An example by
Nageldinger’s
KressArray
Xplorer
Efficient Memory
Communication
should be directly
supported by the
Mapper Tools
Legend:
Optimized
Parallel
memory ports Memory
Controller
sequencers
application
not used
http://kressarray.de
© 2002, reiner@hartenstein.de
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X pu te r L a b
Opportunities by new patent laws ?
University of Kaiserslautern
• to clever guys being keen on patents:
• don‘t file for patent following details !
• everything shown in this presentation
has been published years ago
© 2002, reiner@hartenstein.de
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Coarse Grain Reconfigurable Architectures