Software
Development
© 2004 Xilinx, Inc. All Rights Reserved
Objectives
After completing this module, you will be able to:
•
•
•
•
Identify the functionality included in the GNU tools: GCC, AS, LD, GDB
Examine the IP driver’s functionality and design
Examine the Xilinx Libraries
Determine what is a BSP and what is included
Software Development - 8 - 3
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Outline
•
•
Introduction
Software Settings
–
–
•
•
GNU Tools: GCC, AS, LD, Binutils
Device Drivers
–
–
–
–
•
•
Level 0, Level 1
PowerPC Processor: Exceptions, Sleep, Time
MicroBlaze Processor: Interrupts
Integration in EDK
Libraries
BSP
–
Software Development - 8 - 4
Software Platform Settings
Compiler Settings
Boot Files and Sequence
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Embedded versus Desktop
•
•
•
Desktop development: written,
debugged, and run on the same
machine
OS loads the program into the
memory when the program
has been requested to run
Address resolution takes place
at the time of loading by a
program called the loader
–
The loader is included
in the OS
Software Development - 8 - 5
•
The programmer glues into one
executable file called ELF
–
•
Boot code, application code,
RTOS, and ISRs address
resolution takes place during
the “gluing” stage
The executable file is
downloaded into the target
system through different
methods
–
© 2004 Xilinx, Inc. All Rights Reserved
Ethernet, serial, JTAG, BDM,
ROM programmer
For A cadem ic U se O nly
Embedded versus Desktop
•
Development takes place on one
machine (host) and is downloaded
to the embedded system (target)
Host Computer
Target Computer
Off & On-Chip Memory
Core
ConnectTM
Firmware
#Include stdio.h
Main()
Other PPC405
Cores
PPC405 Dbg Facilities
Control
CPU Trace
Port
CPU JTAG
Port
SystemICE
Core
Post First
Release
CS ICON
Cores
OCM IF
I/O Selection
On-Chip
Memory
User
Ports
GB I/O
Port
Std JTAG
Port
A cross-compiler is run on the host
Software Development - 8 - 6
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Embedded Development
•
Different set of problems
–
–
–
Unique hardware for every design
Reliability
Real-time response requirement (sometimes)
•
–
–
RTOS versus OS
Code compactness
High-level languages and assembly
Software Development - 8 - 7
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
EDK
Processor IP
MPD Files
MHS File
system.mhs
Source Code
Source Code
PlatGen
Synthesis
Compile
MSS File
system.mss
LibGen
system.ucf
EDIF
IP Netlists
Object Files
ISE/Xflow
Link
system.bit
Data2MEM
Executable
Libraries
Focus Here
download.bit
Hardware
Software Development - 8 - 8
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Outline
•
•
Introduction
Software Settings
–
–
•
•
GNU Tools: GCC, AS, LD, Binutils
Device Drivers
–
–
–
–
•
•
Level 0, Level 1
PowerPC Processor: Exceptions, Sleep, Time
MicroBlaze Processor: Interrupts
Integration in EDK
Libraries
BSP
–
Software Development - 8 - 9
Software Platform Settings
Compiler Settings
Boot Files and Sequence
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Software Design
Environment
•
•
•
The Library Generator (LibGen) utility generates the necessary libraries
and drivers for the embedded soft processors
LibGen takes an MSS (Microprocessor Software Specification) file
created by the user as input. The MSS file defines the drivers associated
with peripherals, standard input/output devices, interrupt handler
routines, and other related software features
The MSS file is generated by XPS by using the software settings
specified
Software Development - 8 - 10
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
LibGen
LibGen Generated Directories
•
code directory
–
project_directory
•
Processor instance directory
include directory
–
code directory
include directory
A repository for EDK executables
–
C header files that are required by
drivers
xparameters.h
•
lib directory
libsrc directory
•
Note: The number of processor instance directories
generated is related to the number of
processor instances present in the system
Software Development - 8 - 11
© 2004 Xilinx, Inc. All Rights Reserved
•
Defines base and high
addresses of the peripherals in
the system
Defines the peripheral IDs
required by the drivers and user
programs
Defines the function prototypes
For A cadem ic U se O nly
LibGen
LibGen Generated Directories
•
lib directory
–
libc.a, libm.a and libxil.a libraries
project_directory
•
processor instance directory
code directory
•
include directory
libsrc directory
–
lib directory
–
libsrc directory
Note: The processor instance directories
content is overwritten every time LibGen
is run
Software Development - 8 - 12
The libxil library contains driver
functions that the particular
processor can access
Intermediate files and makefiles that
compile the libraries and drivers
Peripheral-specific driver files that
are copied from the EDK and user
driver directories
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Outline
•
•
Introduction
Software Settings
–
–
•
•
GNU Tools: GCC, AS, LD, Binutils
Device Drivers
–
–
–
–
•
•
Level 0, Level 1
PowerPC Processor: Exceptions, Sleep, Time
MicroBlaze Processor: Interrupts
Integration in EDK
Libraries
BSP
–
Software Development - 8 - 13
Software Platform Settings
Compiler Settings
Boot Files and Sequence
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Software Platform Settings
•
•
Software settings can be
assigned to individual processor
instance by double-clicking a
respective instance in System
BSP view under the System tab,
or
Software settings can also be
assigned clicking Project 
Software Platform Settings and
selecting a processor instance
Software Development - 8 - 14
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Software Platform Settings
1
Change driver
assignment
if needed
2
Select OS
3
Check desired
libraries
1
3
4
4
2
Set library version
Software Development - 8 - 15
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Software Platform Settings
1
Set compiler, archiver
core clock frequency,
and extra compiler
flags
2
Set interrupt handlers
for devices that have
the interrupt
mechanism
enabled
Software Development - 8 - 16
1
2
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Software Platform Settings
1
Select stdin and stdout
devices. Also, if your
application is using
memory allocation
function calls, then
select “true” in the
nee_xil_malloc field
Software Development - 8 - 17
1
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Outline
•
•
Introduction
Software Settings
–
–
•
•
GNU Tools: GCC, AS, LD, Binutils
Device Drivers
–
–
–
–
•
•
Level 0, Level 1
PowerPC Processor: Exceptions, Sleep, Time
MicroBlaze Processor: Interrupts
Integration in EDK
Libraries
BSP
–
Software Development - 8 - 18
Software Platform Settings
Compiler Settings
Boot Files and Sequence
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Compiler Settings
•
•
Compiler settings can be assigned
by double-clicking a processor
instance in the Application tab
Environment tab:
–
Compiler Tools
•
–
Mode
•
•
–
Displays compiler to be used
Executable
XmdStub (MicroBlaze only)
Memory Information
•
•
•
Program Start Address
Stack Size
Heap Size
Software Development - 8 - 19
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Compiler Settings
•
Optimization tab:
–
Optimization Parameters
•
•
•
–
Debug Options
•
•
•
*
Optimization Level: 0 to 3
Use Global Pointer Optimization*
Enable Profiling”
Do not generate debug symbols
Create symbol for debugging
(-g option)
Create symbols for assembly
(-gstabs option)
For profiling, xilprofile library must
be included
Software Development - 8 - 20
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Compiler Settings
•
Directories tab:
–
Search Paths
•
•
•
–
Linker Options
•
•
–
Compiler (-B)
Library (-L)
Include (-I)
Libs to link (-I)
Linker Script
Output Information
•
Output ELF File
Software Development - 8 - 21
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Compiler Settings
•
Advanced tab:
–
Additional Compiler Options
•
–
Add additional options
–
For example: -g
Pass Space Separated Options to
•
•
•
Preprocessor (-Wp)
Assembler (-Wa)
Linker (-Wl)
Software Development - 8 - 22
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Outline
•
•
Introduction
Software Settings
–
–
•
•
GNU Tools: GCC, AS, LD, Binutils
Device Drivers
–
–
–
–
•
•
Level 0, Level 1
PowerPC Processor: Exceptions, Sleep, Time
MicroBlaze Processor: Interrupts
Integration in EDK
Libraries
BSP
–
Software Development - 8 - 23
Software Platform Settings
Compiler Settings
Boot Files and Sequence
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
GNU Tools: GCC
•
•
•
GCC translates C source code into
assembly language
GCC also functions as the user interface
to the GNU assembler and to the GNU linker,
calling the assembler and the linker with
the appropriate parameters
Supported cross-compilers:
–
•
GNU GCC (powerpc-eabi-gcc)
Wind River Diab compiler (dcc)
Assembly
files
MicroBlaze processor compiler
•
•
Cross-compiler
PowerPC processor compiler
•
–
C files
GNU GCC (mb-gcc)
Command line only; uses the settings set through the GUI
Software Development - 8 - 24
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
GNU Tools
•
Calls four different executables
–
–
Preprocessor (cpp0)
Language specific c-compiler
•
•
–
Assembler
•
•
–
cc1 C-programming language
cc1plus C++ language
mb-as (MicroBlaze processor)
powerpc-eabi-as (PowerPC
processor)
Linker and loader
•
•
mb-ld (MicroBlaze processor)
powerpc-eabi-ld (PowerPC
processor)
Software Development - 8 - 25
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
GNU Tools: AS
•
Input: Assembly language files
–
•
Output: Object code
–
–
File extension: .o
Contains
•
•
•
•
•
•
Assembly files
File extension: .s
Assembled piece of code
Constant data
External references
Debugging information
Typically, the compiler automatically
calls the assembler
Use –Wa switch if the source files are
assembly only and use gcc
Software Development - 8 - 26
© 2004 Xilinx, Inc. All Rights Reserved
Cross-assembler
Object files
For A cadem ic U se O nly
GNU Tools: LD
•
•
Linker
Inputs:
–
–
–
•
Several object files
Archived object files (library)
Linker script (mapfile)
Outputs:
–
–
Object
files
Linker
script
Linker/Locator
Executable image (.ELF)
Mapfile (different from linker script)
Executable
Software Development - 8 - 27
© 2004 Xilinx, Inc. All Rights Reserved
Map
For A cadem ic U se O nly
Binutils: Binary Utilities
•
AR Archiver
–
–
–
•
Create, modify, and extract from libraries
Used in EDK to combine the object files of the Board Support Package
(BSP) in a library
Used in EDK to extract object files from different libraries
OBJDUMP
–
Display information from object files and executables
•
•
•
–
Header information, memory map
Data
Disassemble code
GNU executables
•
•
powerpc-eabi-objdump
mb-objdump
Software Development - 8 - 28
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Powerpc-eabi-objdump
Text section
Memory
location
Machine
code
Assembly
instructions
Software Development - 8 - 29
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Outline
•
•
Introduction
Software Settings
–
–
•
•
GNU Tools: GCC, AS, LD, Binutils
Device Drivers
–
–
–
–
•
•
Level 0, Level 1
PowerPC Processor: Exceptions, Sleep, Time
MicroBlaze Processor: Interrupts
Integration in EDK
Libraries
BSP
–
Software Development - 8 - 30
Software Platform Settings
Compiler Settings
Boot Files and Sequence
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Device Drivers
•
The Xilinx device drivers are designed to meet the following objectives:
–
Provide maximum portability
•
–
Support FPGA configurability
•
–
Supports multiple instances of the device without code duplication for each
instance, while at the same time managing unique characteristics on a perinstance basis
Support simple and complex use cases
•
–
The device drivers are provided as ANSI C source code
A layered device driver architecture provides both
–
Simple device drivers with minimal memory footprints
–
Full-featured device drivers with larger memory footprints
Ease of use and maintenance
•
Xilinx uses coding standards and provides well-documented source code for
developers
Software Development - 8 - 31
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Outline
•
•
Introduction
Software Settings
–
–
•
•
GNU Tools: GCC, AS, LD, Binutils
Device Drivers
–
–
–
–
•
•
Level 0, Level 1
PowerPC Processor: Exceptions, Sleep, Time
MicroBlaze Processor: Interrupts
Integration in EDK
Libraries
BSP
–
Software Development - 8 - 32
Software Platform Settings
Compiler Settings
Boot Files and Sequence
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Drivers: Level 0 / Level 1
•
The layered architecture provides seamless integration with…
–
–
–
(Layer 2) RTOS application layer
(Layer 1) High-level device drivers that are full-featured and portable
across operating systems and processors
(Layer 0) Low-level drivers for simple use cases
Layer 2, RTOS Adaptation
Layer 1, High-level Drivers
Layer 0, Low-level Drivers
Software Development - 8 - 33
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Drivers: Level 0
•
•
•
Consists of low-level device drivers
Implemented as macros and functions that are designed to allow a
developer to create a small system
Characteristics:
–
–
–
–
–
–
–
–
Small memory footprint
Little to no error checking is performed
Supports primary device features only
No support of device configuration parameters
Supports multiple instances of a device with base address input to the API
Polled I/O only
Blocking function calls
Header files have “_l” in their names (e.g. xuartlite_l.h)
Software Development - 8 - 34
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Drivers: Level 1
•
•
•
Consists of high-level device drivers
Implemented as macros and functions and designed to allow a developer
to utilize all of the features of a device
Characteristics:
–
–
–
–
–
–
–
–
Abstract API that isolates the API from hardware device changes
Supports device configuration parameters
Supports multiple instances of a device
Polled and interrupt driven I/O
Non-blocking function calls to aid complex applications
May have a large memory footprint
Typically, provides buffer interfaces for data transfers as opposed to byte
interfaces
Header files do not have “_l” in their names (e.g. xuartlite.h)
Software Development - 8 - 35
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Comparison Example
•
Uartlite Level 1
–
–
–
–
–
–
–
–
–
–
–
–
–
•
XStatus XUartLite_Initialize (XUartLite *InstancePtr, Xuint16 DeviceId)
void XUartLite_ResetFifos (XUartLite *InstancePtr)
unsigned int XUartLite_Send (XUartLite *InstancePtr, Xuint8 *DataBufferPtr, unsigned int NumBytes)
unsigned int XUartLite_Recv (XUartLite *InstancePtr, Xuint8 *DataBufferPtr, unsigned int NumBytes)
Xboolean XUartLite_IsSending (XUartLite *InstancePtr)
void XUartLite_GetStats (XUartLite *InstancePtr, XUartLite_Stats *StatsPtr)
void XUartLite_ClearStats (XUartLite *InstancePtr)
XStatus XUartLite_SelfTest (XUartLite *InstancePtr)
void XUartLite_EnableInterrupt (XUartLite *InstancePtr)
void XUartLite_DisableInterrupt (XUartLite *InstancePtr)
void XUartLite_SetRecvHandler (XUartLite *InstancePtr, XUartLite_Handler FuncPtr, void *CallBackRef)
void XUartLite_SetSendHandler (XUartLite *InstancePtr, XUartLite_Handler FuncPtr, void *CallBackRef)
void XUartLite_InterruptHandler (XUartLite *InstancePtr)
Uartlite Level 0
–
–
void XUartLite_SendByte (Xuint32 BaseAddress, Xuint8 Data)
Xuint8 XUartLite_RecvByte (Xuint32 BaseAddress)
Software Development - 8 - 36
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Outline
•
•
Introduction
Software Settings
–
–
•
•
GNU Tools: GCC, AS, LD, Binutils
Device Drivers
–
–
–
–
•
•
Level 0, Level 1
PowerPC Processor: Exceptions, Sleep, Time
MicroBlaze Processor: Interrupts
Integration in EDK
Libraries
BSP
–
Software Development - 8 - 37
Software Platform Settings
Compiler Settings
Boot Files and Sequence
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Exceptions and Interrupts
•
Exceptions are events detected by the processor that require action by
the system software
–
–
–
•
Typically, the result of unexpected error conditions (e.g., bus error)
Some exceptions can be programmed to occur (e.g., FIT, PIT)
Some exceptions are generated by external devices (e.g., CritInt)
Interrupts are automatic control transfers as a result of an exception
–
–
–
–
–
Execution of the current program is suspended after the current instruction
Some context info is saved so execution can return to the current program
Execution is transferred to the interrupt handler to service the interrupt
The interrupt handler must be registered
The interrupt must be enabled
Software Development - 8 - 38
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Hardware Interrupt Inputs
•
Two external inputs to the IBM PowerPC 405 processor core:
–
–
•
Enabled and disabled through the Machine State Register (MSR)
–
–
•
Critical interrupt
External interrupt
MSR(CE) and MSR(EE)
Default @RESET is disabled
FPGA design adds an interrupt controller for application-specific
requirements
–
Supports 32 interrupts
Software Development - 8 - 39
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Exceptions and Interrupts
Exception Code
Entry Point
Save State
Call Handler
Restore State
HANDLER
Return to Program
Registered Handler
Software Development - 8 - 40
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Exceptions and Interrupts
•
Exception library function calls support:
–
void XExc_Init(void);
•
–
void XExc_RegisterHandler (Xuint8 ExceptionId, XExceptionHandler
Handler, void *DataPtr);
•
–
Replaces the current handler with a default handler
void XExc_mEnableExceptions (EnableMask);
•
–
Allows the registration of a handler
void XExc_RemoveHandler (Xuint8 ExceptionId)
•
–
Initializes vector table, default handlers
Enables Crit, NonCrit interrupts
void XExc_mDisableExceptions (DisableMask);
•
Disables Crit, NonCrit interrupts
Software Development - 8 - 41
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Timer Facilities
•
Features:
–
–
–
–
–
•
Time base
Fixed Interval Timer (FIT)
Programmable Interval Timer (PIT)
Watchdog timer
These timers share the same time-base clock frequency
Uses:
–
–
–
–
Time-of-day
Data logging
Peripherals requiring periodic service
Recover from faulty hardware or firmware
Software Development - 8 - 42
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Internal Hardware Interrupt
Handling Example
•
When the source of the interrupt or exception is internal to the PPC, you should
explicitly perform the following tasks (using PIT Timer as an example) in the
main() routine
–
–
–
–
–
•
Initialize exception in the handler’s vector space
•
XExc_Init();
Register the interrupt handler
•
XExc_RegisterHandler(XEXC_ID_PIT_INT, (XExceptionHandler) pit_timer_int_handler,
(void *) 0);
Initialize and enable the device
•
XTime_PITSetInterval( 0xffffff00 );
•
XTime_PITEnableAutoReload();
Arm the device
•
XTime_PITEnableInterrupt() ;
Enable PPC noncritical interrupts
•
XExc_mEnableExceptions(XEXC_NON_CRITICAL);
Develop an interrupt handler that will acknowledge the source of the interrupt
(resetting flag) and perform a task it is supposed to do
Software Development - 8 - 43
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
PowerPC: Sleep
•
Sleep BSP library function calls:
–
–
•
•
unsigned int usleep(unsigned int __useconds);
unsigned int sleep(unsigned int __seconds);
The sleep() or usleep() function in sleep.c delays the execution of a
program by __seconds or __useconds seconds
Set CORE_CLOCK_FREQUENCY as sleep() and usleep() functions use
it compute the delay
Software Development - 8 - 44
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
PowerPC: Time
•
•
•
The xtime_l.c file and corresponding xtime_l.h include file provide access
to the 64-bit time-base counter inside the PowerPC processor core
The counter increases by one every processor cycle
Declarations:
–
void XTime_SetTime(XTime xtime);
•
–
void XTime_GetTime(XTime *xtime);
•
–
Sets the time-base register to the value in xtime
Writes the current value of the time-base register to variable xtime
void XTime_TSRClearStatusBits(unsigned long Bitmask);
•
Used to clear bits in the Timer Status Register (TSR). The parameter Bitmask
designates the bits to be cleared. A one in any position of the Bitmask
parameter clears the corresponding bit in the TSR
Software Development - 8 - 45
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Outline
•
•
Introduction
Software Settings
–
–
•
•
GNU Tools: GCC, AS, LD, Binutils
Device Drivers
–
–
–
–
•
•
Level 0, Level 1
PowerPC Processor: Exceptions, Sleep, Time
MicroBlaze Processor: Interrupts
Integration in EDK
Libraries
BSP
–
Software Development - 8 - 46
Software Platform Settings
Compiler Settings
Boot Files and Sequence
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Interrupt Management With
Interrupt Controller Present
•
The interrupt controller is required if more than one interrupting device is
present or the only interrupting signal is not level sensitive
–
Connect peripheral’s interrupt requesting signals to the Intr port of the interrupt
controller in the MHS file
e.g. PORT Intr = RS232_Interrupt & interrupt_push & interrupt_timer
–
–
Connect interrupt controller output intc to a processor interrupt pin
e.g. PORT Irq = interrupt_req
Define an external requesting signal in the global ports section of the MHS file
e.g. PORT interrupt_in1 = interrupt_in1, DIR = IN, LEVEL = low, SIGIS = Interrupt
–
–
Define signals in MSS file to associate them to peripherals
e.g. PARAMETER int_handler = uart_int_handler, int_port = Interrupt
Write interrupt handler functions for each interrupting requesting input
Software Development - 8 - 47
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Interrupt Management Without
Interrupt Controller
•
The interrupt controller is not required when only one interrupting device
is present and the interrupting pin and signal are level sensitive
–
–
–
–
The interrupt signal of the peripheral (or the external interrupt signal) must
be connected to the interrupt input of the MicroBlaze processor in the MHS
file
Define the signal in MSS file to associate them to peripherals
e.g. PARAMETER int_handler = uart_int_handler, int_port = Interrupt
Write an interrupt handler routine to service the request
The base address of the peripheral instance can be accessed as
XPAR_INSTANCE_NAME_BASEADDR
Software Development - 8 - 48
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
MicroBlaze Interrupts
•
MicroBlaze processor functions
–
void microblaze_enable_interrupts(void)
•
•
–
This function enables interrupts on the MicroBlaze processor
When the MicroBlaze processor starts up, interrupts are disabled. Interrupts
must be explicitly turned on by using this function
void microblaze_disable_interrupts(void)
•
This function disables interrupts on the MicroBlaze processor. This function
may be called when entering a critical section of code where a context switch
is undesirable
Software Development - 8 - 49
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Outline
•
•
Introduction
Software Settings
–
–
•
•
GNU Tools: GCC, AS, LD, Binutils
Device Drivers
–
–
–
–
•
•
Level 0, Level 1
PowerPC Processor: Exceptions, Sleep, and Time
MicroBlaze Processor: Interrupts
Integration in EDK
Libraries
BSP
–
Software Development - 8 - 50
Software Platform Settings
Compiler Settings
Boot Files and Sequence
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Integration in EDK
•
•
•
When the interrupt generating device is
connected to the processor interrupt pin,
either through an opb interrupt controller
or directly, only the interrupt handler
function must be developed (i.e., you do
not need to explicitly write code to set up
the interrupt mechanism)
Double-click the peripheral to open the
Software Platform Settings dialog
The Interrupt Handler Function section
in Processor and Device Parameters tab
provides an entry for the Interrupt
function name associated with that
peripheral
Software Development - 8 - 51
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Outline
•
•
Introduction
Software Settings
–
–
•
•
GNU Tools: GCC, AS, LD, Binutils
Device Drivers
–
–
–
–
•
•
Level 0, Level 1
PowerPC Processor: Exceptions, Sleep, Time
MicroBlaze Processor: Interrupts
Integration in EDK
Libraries
BSP
–
Software Development - 8 - 52
Software Platform Settings
Compiler Settings
Boot Files and Sequence
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Libraries
•
Xilinx provides three libraries
–
–
Math library (libm)
•
The math library is an improvement over the newlib math library
•
The –lm option is used for libm functions
Standard C language support (libc)
•
–
The functions of this library are automatically available
Xilinx C drivers and libraries (libxil)
•
•
•
Xilinx file support functions LibXil File
Xilinx memory file system LibXil Mfs
Xilinx networking support LibXil Net
Software Development - 8 - 53
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Outline
•
•
Introduction
Software Settings
–
–
•
•
GNU Tools: GCC, AS, LD, Binutils
Device Drivers
–
–
–
–
•
•
Level 0, Level 1
PowerPC Processor: Exceptions, Sleep, Time
MicroBlaze Processor: Interrupts
Integration in EDK
Libraries
BSP
–
Software Development - 8 - 57
Software Platform Settings
Compiler Settings
Boot Files and Sequence
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
What is a BSP?
•
Board Support Package (BSP):
–
–
–
A set of software modules combined into the libxil.a library
Allows you to use the low-level PowerPC processor core functions
•
Enable, disable, and flush caches
•
Read/write time-base registers
Allows you to use IP peripheral-device drivers
•
–
GPIO, IIC controller, PCI controller, UART
Offers glue functionality to link code against standard libraries
•
•
•
Time, sleep
Files
Memory
Software Development - 8 - 58
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Hardware IP Device Drivers
•
Driver
–
–
•
Provides an interface for the software to communicate with the hardware
Designed to be portable across processor architectures and operating
systems
Delivery format
–
–
–
Delivered as source code, allowing it to be built and optimized
Minimized assembly language
C programming language
Software Development - 8 - 59
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Outline
•
•
Introduction
Software Settings
–
–
•
•
GNU Tools: GCC, AS, LD, Binutils
Device Drivers
–
–
–
–
•
•
Level 0, Level 1
PowerPC Processor: Exceptions, Sleep, Time
MicroBlaze Processor: Interrupts
Integration in EDK
Libraries
BSP
–
Software Development - 8 - 60
Software Platform Settings
Compiler Settings
Boot Files and Sequence
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
PowerPC Processor
Boot Files
•
Files: boot.S, boot0.S, crt0.S, eabi.S
–
–
–
–
Application entry point at label _boot in boot.S
_boot is single jump instruction to _boot0 in boot0.S
_boot0 is a few instructions that do a jump to _start in crt0.S
_start
•
•
•
•
Clears .bss and .sbss sections
Sets up stack on an eight byte alignment
Initializes time-base registers to zero
Calls main()
–
Calls _eabi to set R13 and R2 registers to point to .sdata and .sdata2
sections respectively
–
Performs user tasks
Software Development - 8 - 61
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
MicroBlaze Processor
Boot File
•
File: crt0.S
–
–
Application entry point at label _start
_start
•
•
•
•
Clears .bss and .sbss sections
Sets up stack on an eight byte alignment
Initializes exception and interrupt handler
Calls main()
Software Development - 8 - 62
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Review Questions
•
•
•
What GNU GCC option is used to specify that debugging information
should be placed in the executable?
What is included in a BSP?
What are some of the differences between a Level 0 and a Level 1
driver?
Software Development - 8 - 63
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Answers
•
What GNU GCC option is used to specify that debugging information
should be placed in the executable?
–
•
What is included in a BSP?
–
–
–
•
-g
IP drivers
Processor functions
Library functions
What are some of the differences between a Level 0 and a Level 1
driver?
–
–
–
Size
Functionality
Ease of use
Software Development - 8 - 64
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Where Can I Learn More?
•
Tool documentation
–
–
–
–
–
–
•
Processor documentation
–
–
–
•
Embedded System Tools Guide  Microprocessor Software Specifications
Embedded System Tools Guide  Microprocessor Driver Definition
Embedded System Tools Guide  Microprocessor Library Definition
EDK OS and Libraries Reference Guide  LibXil File, Net, and Kernel
Processor IP Reference Guide
Xilinx Drivers
PowerPC Processor Reference Guide
PowerPC 405 Processor Block Reference Guide
MicroBlaze Processor Reference Guide
Support website
–
EDK Home Page: support.xilinx.com/edk
Software Development - 8 - 65
© 2004 Xilinx, Inc. All Rights Reserved
For A cadem ic U se O nly
Descargar

[Sample Course Title Slide Insert Presentation Title]