System Verilog
Testbench Language
David W. Smith
Synopsys Scientist
Synopsys, Inc.
Sample SOC and Testbench
DUT
10/100M
Ethernet
1Gb
Ethernet
10Gb
Ethernet
Ethernet
MAC
Ethernet
MAC
APB
AHB
Memory
Controller
CPU
Core
Ethernet
MAC
USB
USB model
Proprietary
model
Testbench
Proprietary
Bus Controller
Synchronous
Interface Boundaries
5 December 2003
Control
Logic
PCI
Controller
External
Memory
Serial
Ports
RS232 model
Parallel
Ports
1284
model
Bluetooth
controller
Bluetooth
model
Infrared
controller
IR device
model
PCI Model
David W. Smith
Protocol Checkers
for Interface
System with Multiple SOC’s
Packet Switched Bus
Cache
Cache
AMBA
CPU
Mem
AMBA
CPU
FPU
SOC 1
Mem
DUT
Cache
AMBA
CPU
FPU
SOC 2
Mem
FPU
SOC 3
• At System Level Problem is Exacerbated
• Abstractions and Re-use are Necessary!
5 December 2003
David W. Smith
3
Testbench Requirements
• Stimulus Generation
• Directed, Random, ATPG, ...
• Checkers
• Data
• Protocols
• Structured Connection to Multiple Independent Interfaces
• Interconnect
• Clocking Domain
• Protocol
• Abstract Modeling
• High-level data structures
• Dynamic Memory
>
Memory Management
• Re-entrant Processes
>
Inter-process Synchronization, Control, and Communication
• Re-usability
• Single language for design (HDL) and verification (HVL)  HDVL
5 December 2003
David W. Smith
4
Basic Types
• Strings
• arbitrary and dynamic length
• methods to manipulate and convert strings
• operators for comparison, concatenation and replication
• Associative arrays
• Indexed by integer, string, or class
• first(index), last(index), next(index), prev(index), delete(index), and
exist(index) methods
• Dynamic arrays
• integer mem[*];
• mem.size();
• Linked Lists
• doubly linked list of any data type
• iterator, modification, access methods
• Classes, Objects and Methods
• Object Oriented
>
Encapsulation, Inheritance, and Polymorphism
• Objects referenced with handles (Safe Pointers)
5 December 2003
David W. Smith
5
Random Variables and Constraints
Test Scenarios
Constraints
Constraints
• Valid Inputs Specified as Constraints
• Declarative
Input Space
Design
Constraint Solver
• Find solutions
Valid
5 December 2003
David W. Smith
6
Random Variables and Constraints
• rand, randc, and constraint added to class definition
class Bus;
rand bit[15:0] addr;
rand bit[31:0] data;
constraint word_align { addr[1:0] == 2’b0; }
endclass
• Generate 50 data and quad-aligned addresses
Bus bus = new;
repeat(50)
begin
integer result = bus.randomize();
end
5 December 2003
David W. Smith
7
Basic Additions
• Wild card operators (=?= and !?=)
• Pass by reference
Declaration: task tk( var int[1000:1] ar );
Use:
tk( my_array );
// no & needed
• Argument default values and pass by name
Declaration: task foo( int j = 5, int k = 8 );
Use: foo(); foo( 6 ); foo( ,9 ); foo( 6, 9 ); foo(.k(9));
• Alias for nets
• Short nets in a module
• Dynamic Memory
• Objects, threads, strings, dynamic and associative arrays
• Automatically Managed
5 December 2003
David W. Smith
8
Process Control/Synchronization
• Verilog thread support from fork…join with continuation
when all threads complete
• SV threads use fork…join with continuation control
• all
• any
• none
all
any
priority
none
3.0 process
• Threads execute until a blocking statement
• wait for event, mailbox, semaphore, variable change, ...
• Enhanced events (value and duration, passed as arguments)
• Threads are controlled by
•
•
•
•
$terminate
$wait_child
$suspend_thread
$exit
5 December 2003
David W. Smith
9
Clocking Domain
• A clocking domain defines a synchronous interface
for testbench and properties
• Every clocking domain has only one clock event
• Sample and drive timing specified with respect to
clock
• A signal may appear in multiple clocking domains
• Input - multiple samples
• Output – default bus resolution
• Clocking domain creates a scope
5 December 2003
David W. Smith
10
Synchronous Interfaces: Clocking
Race-free cycle and transaction level abstraction
device
clk
enable
full
data[7:0]
empty
bus
clocking bus @(posedge clk);
Clocking Event “clock”
default input #1ns output #2ns;
input
inout
output
output #6ns
endclocking
enable, full;
data;
empty;
reset = top.u1.reset;
Override Output skew
5 December 2003
Synchronous
Interface
David W. Smith
Default I/O skew
Hierarchical signal
Testbench Uses:
bus.enable
bus.data
...
11
Testbench Program Block
• Purpose: contains testbench verification code
• program is similar to a module
• Only one implicit initial block
• Special semantics
Execute in verification phase


design  clocking  verification  read_only
program name ( port_list );
declarations (class, type, function, clocking...)
statements
endprogram
5 December 2003
David W. Smith
12
System Verilog Testbench
Testbench
Verification Extensions
Aliases
Testbench Specific
Basic Types
Clocking Domains
Random Constraints
Program Block
Process Control/Synchronization
References
5 December 2003
David W. Smith
13
Descargar

SystemVerilog Testbench Language