IBM Mainframes
Assembler
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Presentation
Thanks for using this presentation. You are free to use it.
I appreciate if you refer to the author when using it.
I’m sorry about the language errors; my english isn’t so good; I’ll
appreciate if you send me any corrections and suggestions to
optimize the comprehension to the reader.
The same is valid for any technical error; please help me to make
this an error-free text.
Alberto Romano Schiesari – São Paulo - Brazil
www.profars.com
[email protected]
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Summary
Architecture
IBM Mainframes architecture
Data format
Instruction format
Assembler language
Assembly flow
Assembler program structure
Statement
Assembler elements
Statement types
Assembler commands
Machine Instructions
Hints and tips Instructions by group Instructions
Macro Instructions
Appendix - Links
Appendix - Instructions summary (by op code) (by mnemonic)
Appendix - Some EBCDIC characters Some ASCII characters
Appendix - Questions Answers
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Summary
Assembler commands (alphabetically)
AMODE
DROP
ISEQ
RMODE
CCW
DS
LOCTR
SPACE
CCW0
DSECT
LTORG
START
CCW1
DXD
OPSYN
TITLE
CNOP
EJECT
ORG
USING
COM
END
POP
WXTRN
COPY
ENTRY
PRINT
CSECT
EQU
PUNCH
CXD
EXTRN
PUSH
DC
ICTL
REPRO
These aren’t in the scope of this course: AREAD, MACRO, MEXIT, MEND
ACTR, AGO, AIF, ANOP, GBLA, GBLB, GBLC, LCLA, LCLB, LCLC, MHELP,
MNOTE, SETA, SETB, SETC
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Summary
Machine instructions (alphabetically)
A
BCR
CLI
EDMK
LR
MVO
SH
SRDL
TRT
AH
BCT
CLM
EX
LTR
MVZ
SL
SRL
TS
AL
BCTR
CLR
IC
M
N
SLA
SRP
UNPK
ALR
BSM
CP
ICM
MC
NC
SLDA
ST
X
AP
BXH
CR
IPM
MH
NI
SLDL
STC
XC
AR
BXLE
CS
L
MP
NR
SLL
STCK
XI
BAL
C
CVB
LA
MR
O
SLR
STCM
XR
BALR
CDS
CVD
LCR
MVC
OC
SP
STH
ZAP
BAS
CH
D
LH
MVCIN
OI
SPM
STM
BASR
CL
DP
LM
MVCL
OR
SR
SVC
BASSM
CLC
DR
LNR
MVI
PACK
SRA
TM
BC
CLCL
ED
LPR
MVN
S
SRDA
TR
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Architecture
SYSTEM ARCHITECTURE
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Architecture – some components
 System CPU (CISC, RISC, hybrid)
CISC = Complex Instruction Set Computer
Variable length instructions
In each instruction, explicitly or implicitly, one must specify:
- The operation to be done
- The operands used (places with data to process and places to store
results): their address!
- Operands’ length
- Data format
RISC = Reduced Instruction Set Computer
Fixed length instructions; e.g. 4 bytes; the execution (average) is faster
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Architecture – some components
Note that...
Mainframes and PC’s = CISC
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Architecture – some components
 Storage byte addressing (access)
Real storage? Virtual Storage?
In virtual storage systems, hardware must talk with software to
achieve the use of virtual storage
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Architecture – some components
In symbolic languages, the reference to a field is made:
 Using its name (variable or constant) or
 Using its contents (literal)
MOVE 1 TO NPAGE.
NPAGE = 1
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Architecture – some components
In machine language, referencing a field is made using its address,
one must specify a number (hexadecimal / binary) which is the field’s
address. There is NO reference to names.
This is called ADDRESSING.
The hexadecimal number must have 6 or 8 digits.
With 6 digits, if we have to store the address in a storage field, at
least 3 bytes are needed.
With 8 digits, if we have to store the address in a storage field, 4
bytes are needed.
(in many of our examples we use smaller numbers, with 2 or 3 digits, just to simplify the visual and
the computing)
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Architecture – some components
 Storage bytes addressing (access)
Program
Instructions
Areas
F830B004C82F
1C
MOVE instruction in machine language, indicating :
(a) it is MOVE [F8];
(b) Sender [literal 1] length 0 (meaning = 1 byte)
(c) Receiver [NPAGE] length 3 (meaning 4 bytes)
(d) Sender [literal1] address C82F
(e) Receiver [NPAGE] address B004
For now forget why and how, but believe me: x’B004’ is
the NPAGE address and x’C82F’ is the literal address.
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00
00
Sender field
[literal with
contents 1]
It has an address !
00
1C
Receiver field
[NPAGE variable]
It has an address !
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Architecture – some components
 Storage bytes addressing (access)
Real storage X Virtual Storage
Add 1 to the contents of field at address x’2B40’
If the contents of the field at address x’2B40’ is not in the real
storage, then we (operating system + hardware) must:
- Convert address from real to virtual storage
- Fetch the contents from the virtual storage to the real storage
- Execute the instruction
(Remember also that it can happen with the instruction, and with
any or all of the operands, too...)
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Architecture – some components
 Storage bytes addressing (access)
Direct addressing? Indirect addressing?
Direct addressing example  Add 1 to the field at address x’00002B40’
Indirect addressing example  Add 1 to the field at address x’2000’ + x’0B40’
Notes:
(a) in fact, the field address is x’2B40’; it is expressed in a different way (x’2000’ +
x’0B40’)
(b) the number x’2000’ may be in a place, the number x’0B40’ in another place...
Indirect addressing example 
Add 1 to the field at the address x’2000’ + x’0B00’ + x’0040’
Notes:
(a) in fact, the field address is x’2B40’; it is expressed in a different way (x’2000’ +
x’0B00’ + x’0040’)
(b) the number x’2000’ may be in a place, the number x’0B00’ in another place,
and x’0040’ elsewhere...
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Architecture – some components
 Storage bytes addressing capacity
Storage length; how many “bits” does the mainframe’s CPU have?
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Architecture – some components
 Storage bytes addressing capacity
Address Bus = to refer to the addresses
To address storage up to 64K, address bus must be 16-bit wide.
To address storage up to 16MB, address bus must be 24-bit. etc...
Data Bus = to transfer data between components
To transfer (simoutaneously) a half-word, data bus must be 16-bit wide.
To transfer (simoutaneously) a full-word the data bus must be 32-bit. Eetc...
Data transfer
Data Bus
CPU
Storage
Address Bus
Storage address refer
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Architecture – some components
 CPU Instruction Set – types and characteristics
How many, what are the instructions of a CPU Instruction Set?
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Architecture – some components
 CPU instruction execution
How is the instruction execution process?
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Architecture – some components
 CPU instruction execution – generic process
 FETCH (CPU fetchs the instruction from RAM storage to a CPU
internal area; “problem”: variable length instructions
 Decode = Analysis : what is the instruction length? (not needed in
RISC Cpu), what is the operation to be done (wrong code? We could
dubb this situation with the name 0C1...), what are the operands, etc
Error? Pass control to the operating system, to solve it
 OK? Operand(s) data FETCH
 If they are in real store, good! (Else, lots of things to do...)
 Operand contents Validation
Error? How about dubb it as 0C7?...
 Execution : in some cases (math operations mostly), results must be
stored temporarily in CPU areas
OK? If needed, STORE results back in RAM storage
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Architecture – some components
Other architectural components
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Architecture – some components
OTHER architectural components
 Interruption system
What are the interruptions? E.g. Time, program error (0Cx...)
 I/O sub-systems
How does the comm work between controller, storage, CPU and software?
Which information does software receive after I/O operations?
 Storage protection system
How does the storage protection work?
Is it possible to a program to invade another?
 Virtual storage system
Which is the process?
What are the page-in & page-out algorithms?
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IBM Mainframes Architecture
IBM Mainframes Architecture
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IBM Mainframes Architecture
Tribute
We own our jobs to him! Gene Myron Amdahl (1922-)
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IBM Mainframes Architecture
IBM Mainframes : architectural main components
CPU
ALU
GR0
GR1
GR2
GR3
GR4
GR5
GR6
GR7
GR8
GR9
GR10
GR11
GR12
GR13
GR14
GR15
16 General Registers
(fixed point registers)
FPR0
FPR2
FPR4
FPR6
4 Floating Point registers (8 bytes each)
PSW
1 Special 8 byte Register named
PSW (Program Status Word)
etc... (cache...)
4 bytes each
Storage (RAM)
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IBM Mainframes Architecture
IBM Mainframes : architectural main components
CPU
PSW
cc
nia
etc
PSW : special 8 bytes length register. 2 important “fields" :
 CONDITION CODE (*) : 2 BITS. They indicate, after some instructions execution,
some condition inherent to the executiosn., e.g., comparison result.
(*) Remember that this is NOT the operating system RETURN CODE (program-finish status
indicator ; may be tested using JCL tool)
 next instruction address (to be executed – 3 or 4 bytes, depending on the type
of addressing mode/PSW)
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IBM Mainframes Architecture
BC mode PSW
BYTE 0 BITS 0-5
= channel masks
BIT 6
= channel 6 and above masks
BIT 7
= external mask
BYTE 1 BITS 8-11 = protection key
BIT 12
= 0 = Basic Control Mode
BIT 13
= machine-check mask
BIT 14
= 1 = wait state
BIT 15
= 1 = problem program state
BYTES 2-3 (BITS 16-31) = Interruption code
BYTE 4 BITS 32-33 = ILC = Instruction length code
BITS 34-35 = CC = Condition code
BITS 36-39 = program mask
BYTES 5-7 (BITS 40-63) = Instruction address
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IBM Mainframes Architecture
EC mode PSW
BYTE 0 BIT 0
= 0
BIT 1
= PER mask
BIT 2
= 0
BIT 3
= 0
BIT 4
= 0
BIT 5
= translation mode
BIT 6
= I/O mask
BIT 7
= external mask
BYTE 1 BITS 8-11 = protection key
BIT 12
= 1 = Extended Control Mode
BIT 13
= machine check mask
BIT 14
= 1 = wait state
BIT 15
= 1 = problem program state
BYTE 2 BIT 16
= 0
BIT 17
= 0
BITS 18-19 = CC = condition code
BITS 20-23 = program mask
BIT 20 = fixed-point overflow mask
BIT 21 = decimal-overflow mask
BIT 22 = exponent underflow mask
BIT 23 = significance mask
BYTE 3 (BITS 24-31) = 00000000
BYTE 4 (BITS 32-39) = 00000000
BYTES 5-7 (BITS 40-63) = Instruction address
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IBM Mainframes Architecture
XA mode PSW
BYTE 0 BIT 0
= 0
BIT 1
= PER mask recording
BIT 2-4
= 000
BIT 5
= translation mode
BIT 6
= I/O mask
BIT 7
= external mask
BYTE 1 BITS 8-11 = protection key
BIT 12
= 1
BIT 13
= machine-check mask
BIT 14
= 1 = wait state
BIT 15
= 1 = program problem state
BYTE 2 BIT 16
= address space mode (together with bit 5)
BIT 17
= 0
BITS 18-19 = CC = condition code
BITS 20-23 = program mask
BIT 20 = fixed-point overflow mask
BIT 21 = decimal-overflow mask
BIT 22 = exponent underflow mask
BIT 23 = significance mask
BYTE 3 (BITS 24-31) = 00000000
BYTE 4 BIT 32
= 0 = 24 bit addressing
= 1 = 31 bit addressing
BYTE 4/5/6/7 (BITS 33-63) = Instruction address
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IBM Mainframes Architecture
ESA mode PSW
BYTE 0 BIT
BIT
BIT
BIT
BIT
BIT
BYTE 1 BITS
BIT
BIT
BIT
BIT
BYTE 2 BIT
= 0
= PER mask
= 000
= translation mode
= I/O mask
= external mask
= protection key
= 1
= machine-check mask
= 1 = wait state
= 1 = program problem state
= address space control
= 00 = Primary space mode (bit 5 = 1)
= 01 = Access-register mode (bit 5 = 1)
= 10 = Secondary space mode (bit 5 = 1)
= 11 = Home space mode (bit 5 = 1)
BITS 18-19 = CC = condition code
BITS 20-23 = program mask
BIT 20 = fixed-point overflow mask
BIT 21 = decimal-overflow mask
BIT 22 = exponent underflow mask
BIT 23 = significance mask
BYTE 3 (BITS 24-31) = 00000000
BYTE 4 BIT 32
= 0 = 24 bit addressing
= 1 = 31 bit addressing
BYTE 4/5/6/7 (BITS 33-63) = Instruction address
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0
1
2-4
5
6
7
8-11
12
13
14
15
16-17
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IBM Mainframes Architecture
IBM Mainframes : special areas
HALFWORD = area with 2 bytes and address multiple of 2
WORD ou FULLWORD = area with 4 bytes and address multiple of 4
DOUBLEWORD = area with 8 bytes and address multiple of 8
QUADWORD = area with 16 bytes and address multiple of 16
•
•
•
•
QW
QW
DW
•
•
•
DW
FW
HW
•
•
•
•
•
•
FW
•
HW
Summary
HW
Prev.Page
DW
FW
•
HW
HW
•
•
FW
•
HW
HW
etc.
FW
•
HW
HW
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IBM Mainframes Architecture
IBM Mainframes : program error interruptions (0Cx)
Code
0001
0002
0003
0004
0005
0006
0007
Reason
OPERATION = the operation code is invalid (it
doesn’t refer to any executable instruction)
PRIVILEGED OPERATION = the program tried to
execute a privileged instruction.
EXECUTE = Execute of another Execute instruction
PROTECTION = A program instruction tried to store
data outside its authorized range
ADDRESSING = A program instruction referenced a
non-existent address
SPECIFICATION = The instruction specified
something with error; e.g., an odd floating-point
register
DATA = The fields an instruction refers to aren’t in
the correct format; e.g., adding 2 packed fields, and
one of them (or both) does not meet the packed
format rules.
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Code
0008
0009
000A
000B
000C
000D
000E
000F
Reason
FIXED POINT OVERFLOW = The instruction uses a
general register as result operand, but it isn’t large
enough to fit the result
FIXED POINT DIVIDE = Binary fixed-point division
with zero divisor.
DECIMAL OVERFLOW = In an operation with packed
fields, the receiver field isn’t large enough to fit the
result
DECIMAL DIVISION = Packed decimal division with
zero divisor.
EXPONENT OVERFLOW = Binary floating-point
operations.
EXPONENT UNDERFLOW = Binary floating-point
operations.
SIGNIFICANCE = Binary floating-point operations.
FLOATING`POINT DIVISION = Binary floating-point
division with zero divisor.
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IBM Mainframes Architecture
IBM Mainframes IBM : addressing
 It is needed to address : registers and storage bytes
(Remember that a storage field address is the address of its
leftmost byte)
 DIRECT addressing : only for registers:
General Registers = 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
Floating Point Registers = 0,2,4,6
 There is NO DIRECT addressing to storage
The INDIRECT addressing may be:
 Base + Displacement
 Index + Base + Displacement
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IBM Mainframes Architecture
IBM Mainframes IBM : addressing
Note that, in reality, ALL addresses specified are “real
storage” addresses, as if they were in a mirror refleting the
address space.
But remember that the things in real life aren’t so nice...
Try this way: was once a kingdom where for each address
space there was a real storage exactly equal...
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IBM Mainframes Architecture
Base + Displacement
Instructions to Main Avenue Postman :
Go to the “Caliente” Restaurant
Walk 850 meters, you arrived at the house where the
envelope must be delivered!
This is the
BASE, an
initial
reference to
start
identifying the
deliver
address
Walk 850 meters =
Displacement
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IBM Mainframes Architecture
Base + Displacement
Hex number in a General
Register (by this time
dubbed base register)
=
+
Hex number (from
x’000’ up to x’FFF’) in
the instruction,
dubbed displacement
Hex number : this is the
Address
Note: the interrupted line box means that the number (address)
IS NOT in a general register, but in an internal CPU area !!!
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IBM Mainframes Architecture
Base + Displacement : specification (2 bytes)
x
x
x
y
Base register
3
x
5
0
A
Summary
8
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y
Displacement
x
x
D
y
C
x
D
Base Register = 3
Displacement = 5AC
Address = Register 3 contents + x’5AC’
Base register = 13 (D)
Displacement = 08D
Address = Register D contents + x’08D’
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IBM Mainframes Architecture
Base + Displacement
x
x
Base register
y
y
x
y
Displacement
Then:
Maximum displacement = x’FFF’ = 4095
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IBM Mainframes Architecture
Base + Displacement : examples
Base
Register
Base register
Contents
Displacement
“Direct” address
(it would be
necessary 4 bytes
to specify it)
“Indirect” Address
(Base +
displacement : 2
bytes are enough
to specify it)
4
00002000
B40
00002B40
4B40
4
00B2F02C
1A2
00B2F1CE
41A2
15
00000000
DB4
00000DB4
FDB4
0
0046B28C
114
00000114
0114
The contents of register zero is NOT CONSIDERED
computing an address !!!
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IBM Mainframes Architecture
Base + Displacement : Hints and tips
You must use it to address “normal” addresses.
What are “normal” addresses?
Give me a break!
(Those we can express using an ... Expression)
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IBM Mainframes Architecture
Base + Displacement : Hints and tips
What is an expression?
Again!?
(see in the “Assembler elements” chapter)
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IBM Mainframes Architecture
Index + Base + Shift
Instructions to Main Avenue Postman :
Go to the “Caliente” Restaurant.
Walk 850 meters, you’ll arrive at the condo.
In the condo, walk 50 meters then you’ll arrive at the
house where the envelope must be delivered!
Walk 850 =
Displacement
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This is the
BASE, an
initial
reference to
start
identifying the
deliver
address
Walk 50 = Index
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IBM Mainframes Architecture
Index + Base + Shift
Binary number in a General
Register (by this time
dubbed index register)
=
+
Binary number in a
General Register (by this
time dubbed base
register)
+
Hex number (from
x’000’ up to x’FFF’) in
the instruction, dubbed
displacement
Hex number : this is the
Address
Note: the interrupted line box means that the number (address)
IS NOT in a general register, but in an internal CPU area !!!
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IBM Mainframes Architecture
Index + Base + Displacement : specification (21/2 bytes)
x
x
x
z
x
y
Index register Base register
x
x
7
x
B
3
5
Summary
x
5
x
A
C
y
y
Displacement
Index register = 7
Base Register = 3
Displacement = 5AC
Address = register 7 contents +
register 3 contents + x’5AC’
x
F
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A
C
Index Register = 11 (B)
Base Register = 5
Displacement = FAC
Address = register B contents +
register 5 contents + x’FAC’
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IBM Mainframes Architecture
Index + Base + Displacement : specification (21/2 bytes)
x
z
x
x
Index register Base register
y
y
x
y
Displacement
Then:
Maximum displacement = x’FFF’ = 4095
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IBM Mainframes Architecture
Index + Base + Displacement : examples
Index
Register
Index register
Contents
Base
Register
Base Register
Contents
Displace
ment
“Direct”
address
(it would be
necessary 4
bytes to
specify it)
“Indirect”
Address
(Base +
displacement
: 2 ½ bytes
are enough to
specify it)
12
00100000
4
00002000
B40
00102B40
C4B40
0
00F4CAFE
10
000C8B00
1F0
000C8CF0
0A1F0
4
00007000
4
00007000
1A2
0000E1A2
441A2
15
00000000
12
00C42B06
002
00C42B08
FC002
The contents of register zero is NOT CONSIDERED
computing an address !!!
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IBM Mainframes Architecture
Index + Base + Displacement : hints and tips
In general, one uses to address “abnormal” addresses.
What is an abnormal address?
(I’m kidding...)
A good example: the elements of a table.
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IBM Mainframes Architecture
Index + Base + Displacement : hints and tips
Example: addressing elements of a table
BR
US
UK
Initial table
address :
Symbol =
TBSTATS
(converted by
assembler to
base +
displacement)
IT
FR
ES
AR
CA
BE
AU
GE
DE
PT
GR
IR
Target element address (8th element) =
Initial table address + [element length * (number of elements – 1) ] =
TBSTATS + [ 2 * (8 – 1) ] = TABSTATS + 2 * 7 = TBSTATS + 14
Target element address (8th element) =
Base+Displacement of TBSTATS + Index Register
(e.g. 17C0A = Index reg=1, Base reg = 7, displacement = C0A)
TBSTATS address : in the instruction, with format
Base + Displacement = X’7C0A’ (assembler finds out base register and
displacement; let’s suppose Base reg = 7, displacement = X’C0A’)
Contents of Index register : e.g. Reg 1 (it’s our program’s responsibility to
prepare) with contents = X’0000000E’
TBSTATS address in Index+base+displacement format = X’17C0A’
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IBM Mainframes Architecture
IBM Mainframes IBM : addressing
X’00000000’
Suppose
this 256
bytes
storage
X’00000010’
X’00000020’
X’00000030’
X’00000040’
X’00000050’
X’00000060’
X’00000070’
X’00000080’
X’00000090’
X’000000A0’
X’000000B0’
X’000000C0’
X’000000D0’
X’000000E0’
X’000000F0’
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IBM Mainframes Architecture
IBM Mainframes IBM : addressing
X’00000000’
X’00000010’
*
X’00000020’
X’00000030’
X’00000040’
X’00000050’
X’00000060’
X’00000070’
X’00000080’
The number in the base register indicates byte
X’00000090’
*.
X’000000A0’
If the desired
target address is x’00000048’:
X’000000B0’
Q: Using register 12 as base register and with its contents being x’00000000’,
X’000000C0’
how many
bytes one has to “walk” (shift) to, leaving the byte pointed by base
X’000000D0’
register,
arrive at the target byte?
X’000000E0’
A: x’048’ = displacement (blue dotted line)
X’000000F0’
Summary
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49
IBM Mainframes Architecture
IBM Mainframes IBM : addressing
X’00000000’
X’00000010’
The number in the base register indicates byte
X’00000020’
*.
X’00000030’
If the desired
target address is x’000000E8’:
X’00000040’
Q: Using register 12 as base register and with its contents being x’000000A0’,
X’00000050’
how many
bytes one has to “walk” (shift) to, leaving the byte pointed by base
X’00000060’
register,
arrive at the target byte?
X’00000070’
A: x’048’ = displacement (blue dotted line)
X’00000080’
X’00000090’
X’000000A0’
X’000000B0’
*
X’000000C0’
X’000000D0’
X’000000E0’
X’000000F0’
Summary
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50
IBM Mainframes Architecture
IBM Mainframes IBM : addressing
See this case:
Target byte = x’00000048’ ; Base register = C (contents =
x’00000000’) + (Displacement) x’048’
Remember that
Maximum displacement allowed = x’FFF’
In other words: general register C, while used as base
register (in this example), with x’00000000’ as contents,
can only be used as base register to refer to addresses
from x’00000000’ to x’00000FFF’.
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51
IBM Mainframes Architecture
IBM Mainframes IBM : addressing
Maximum displacement allowed = x’FFF’
If an instruction needs to address 2 fields:
The first with address x’00000048’, and the second with
address x’00001CB0’, at the time of its execution, IT’S
NEEDED MORE THAN 1 BASE REGISTER correctly
prepared.
We can set, for example, register C (12) with x’00000000’ and
register D (13) with x’00001000’ .
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52
IBM Mainframes Architecture
IBM Mainframes IBM : addressing
Maximum displacement allowed = x’FFF’
The first field is addressed by base register 12:
C048  Base register C (contents = x’00000000’) +
Displacement x’048’
The second field is addressed by base register 13:
DCB0  Base register D (contents x’00001000’) +
Displacement x’CB0’
THERE’S NO WAY in a single instruction (and, by
extension, in a program range) to use only 1 base
register addressing fields with addresses far from each
other longer than x’FFF’.
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53
IBM Mainframes Architecture
IBM Mainframes IBM : addressing
Summary:
At the same time, one can use a maximum of
15 base registers (remember that the contents
of register zero is not considered when
computing an address).
This means that the biggest program size
addressable simultaneously is
(4K * 15) = 60K
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54
IBM Mainframes Architecture
IBM Mainframes IBM : addressing
Summary:
Using (almost) all registers as base registers:
YOU WILL HAVE PRACTICALLY NO
WORK REGISTER (only R0) !
Be careful!
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55
IBM Mainframes Architecture
Mainframes IBM : endereçamento
WOW !
What if the program is bigger
(than 20K)?
Summary
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56
IBM Mainframes Architecture
IBM Mainframes IBM : addressing
One (there are lots of them) alternative:
Think about what general registers you’ll use as base registers in
your program. For example: R3, R4, R5, R6 and R7
They are 5 registers. This is enough to address (5 x 4K) = up to 20K
In a 20K “piece” of the program, you (must) set the registers up with
the right contents, and use only things (areas and instructions)
belonging to this piece.
In another 20K piece, set the registers up with the other contents
and use only things of the new piece.
And so on...
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57
IBM Mainframes Architecture
IBM Mainframes IBM : addressing
60K
storage
Program
0K
Summary
4K
8K
12K
16K
20K
24K
28K
32K
36K
40K
44K
48K
52K
R3 = x’00000000’
R3 = x’00005000’
R3 = x’0000A000’
R4 = x’00001000’
R4 = x’00006000’
R4 = x’0000B000’
R5 = x’00002000’
R5 = x’00007000’
R5 = x’0000C000’
R6 = x’00003000’
R6 = x’00008000’
R6 = x’0000D000’
R7 = x’00004000’
R7 = x’00009000’
R7 = x’0000E000’
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56K
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58
IBM Mainframes Architecture
Register usage: idea, hints
Summary
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59
IBM Mainframes Architecture
Register usage: idea, hints
Reg
Summary
Use
0
Avoid using; used by the access methods
and operating system routines
1
Avoid using; used by the access methods
and operating system routines; used by TRT
and EDMK instructions.
2
Avoid using; use for work; used by TRT
instruction
3
Use as base register
4
Use as base register
5
Use as base register
6
Use as base register
7
Use as base register
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60
IBM Mainframes Architecture
Register usage: idea, hints
Reg
Use
8
Use as work register
9
Use as work register
10
Use as work register
11
Use as work register
12
Use as work register
13
Avoid using; used as save area by the interface
routines between softwares
14
Avoid using; used to save the return address
when calling a routine by the caller
15
Avoid using; used as initial base register for
called routines, mainly in the access methods
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61
Data format
Data format
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62
Data format
Data format
 Alphanumeric data
EBCDIC standard
 Numeric data
Fixed point binary
(arithmetic operations : registers or storage)
Floating point binary
(arithmetic operations : registers or storage)
Packed decimal
(arithmetic operations : storage)
Zoned decimal
(arithmetic operations : NOT ALLOWED)
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63
Data format - Alphanumeric data
Alphanumeric Data
EBCDIC standard
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64
Data format - Alphanumeric data
1 byte each character
example: to represent the word “ALBERTO”
A
L
B
E
R
T
O
C1
D3
C2
C5
D9
E4
D6
1100
0001
1101
0011
1100
0010
1100
0101
1101
1001
1110
0100
1101
0110
Curiosity: in ASCII
A
L
B
E
R
T
O
41
4C
42
45
52
54
4F
0100
0001
0100
1100
0100
0010
0100
0101
0101
0010
0101
0100
0100
1111
Summary
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65
Data format - Alphanumeric data
1 byte each character
example: to represent the word “Alberto”
A
l
b
e
r
t
o
C1
93
82
85
99
A4
96
1100
0001
1001
0011
1000
0010
1000
0101
1001
1001
1010
0100
1001
0110
Curiosity: in ASCII
A
1
b
e
r
t
o
41
6C
62
65
72
74
6F
0100
0001
0110
1100
0110
0010
0110
0101
0111
0010
0111
0100
0110
1111
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66
Data format - Numeric data
Numeric data
Formats:
- Zoned decimal or
- Packed decimal or
- Fixed point binary or
- Floating point binary
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67
Data format - Numeric data
ZONED DECIMAL
1 byte each algarism, up to 16 bytes = up to 16 algarisms
Each byte : left half = x’F’
right half = algarism
Rightmost byte : left half = sign
positive number or zero : x’F’ or x’C’
negative number : x’D’
IMPORTANT !!!
1  With this format, it’s NOT allowed to do arithmetic operations,
it’s just to receive data (e.g. terminal data entry)
or to format output data (e.g. terminal, printer).
2  Numbers: only INTEGERS.
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68
Data format - Numeric data
ZONED DECIMAL
F1
F2
F3
Number 123 : 3 bytes needed
1111 0001
1111 0010
F1
Number –123 : 3 bytes needed
1111 0001
1111 0010
1111 0011
F2
D3
1101 0011
Atention !!! : if printed (or seen), in character mode this configurations corresponds to the letter “L”
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69
Data format - Numeric data
ZONED DECIMAL
Number 123 in a 5 bytes length field
F0
F0
F1
F2
F3
1111 0000
1111 0000
1111 0001
1111 0010
1111 0011
Number -123 in a 5 bytes length field
F0
F0
F1
F2
D3
1111 0000
1111 0000
1111 0001
1111 0010
1101 0011
Atention !!! : if printed (or seen), in character mode this configurations corresponds to the letter “L”
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70
Data format - Numeric data
PACKED DECIMAL
½ byte each algarism, ½ byte for the sign
Up to 8 bytes = up to 15 algarisms
Rightmost byte : right half : sign
positive number or zero : x’F’ or x’C’
negative number : x’D’
IMPORTANT !!!
1  In this format arithmetic operations are only allowed with
storage fields (there is NO instructions to manipulate packed decimal
data in registers)
2  Numbers: only INTEGERS.
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71
Data format - Numeric data
PACKED DECIMAL
02
0000 0010
3F
0011 1111
Number 23 : 2 bytes needed
02
0000 0010
Number - 23 : 2 bytes needed
02
0000 0010
3C
0011 1100
3D
0011 1101
Atention !!! : if printed (or seen), in character mode these configurations corresponds to “other” characters
Summary
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72
Data format - Numeric data
PACKED DECIMAL
12
0001 0010
3F
0011 1111
Number 123 : 2 bytes needed
12
0001 0010
Number -123 : 2 bytes needed
12
0001 0010
3C
0011 1100
3D
0011 1101
Atention !!! : if printed (or seen), in character mode these configurations corresponds to “other” characters
Summary
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73
Data format - Numeric data
PACKED DECIMAL
Number 123 in a 5 bytes length field
00
00
00
12
3C
0000 0000
0000 0000
0000 0000
0001 0010
0011 1100
Number -123 in a 5 bytes length field
00
00
00
12
3D
0000 0000
0000 0000
0000 0000
0001 0010
0011 1101
Atention !!! : if printed (or seen), in character mode these configurations corresponds to “other” characters
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74
Data format - Numeric data
FIXED POINT BINARY
Only fixed length fields:
2 bytes (1 bit for sign + 15 bits for the number)
or 4 bytes (1 bit for sign + 31 bits for the number)
or 8 bytes (1 bit for sign + 63 bits for the number)
The quantity of algarisms (in the equivalent decimal numbers)
depends on the number being represented (see next slide table)
Leftmost bit = sign
positive number or zero : 0 ; negative number : 1
BUT...
If positive, it’s the number’s representation
If negative, the contents is the complement to the next 2 power
IMPORTANT !!!
1  In this format arithmetic operations are only allowed with
data in registers or in registers and storage fields
(there is NO instructions to manipulate fixed point binary numbers
only in storage; one of the operands must be in register)
2  Numbers: only INTEGERS.
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75
Data format - Numeric data
FIXED POINT BINARY
Bytes
Magnitude
Sample use
2
Thousands
(32K)
Person’s age,
line counter
(US Bilions)
(2G)
Employee salary,
Part code,
Customer code
4
8
(US
Quintillions)
(9Exa)
Summary
Company
revenues,
World
population,
astronomical
distances
Prev.Page
Numbers that may be represented
From –32,768
to 32,767
From –2,147,483,648
to 2,147,483,647
From –9,223,372,036,854,775,808
to 9,223,372,036,854,775,807
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76
Data format - Numeric data
FIXED POINT BINARY
Why complement?
+123 in binary = 1111011
–123 in binary = ...1111111111111111111111110000101
Subtracting 1 step by step... See (0 – 1) subtraction
000000100
- 000000001
----------000000011
4
- 1
----3
000000011
- 000000001
----------000000010
3
-1
----2
000000010
- 000000001
--------000000001
2
1
----1
000000001
- 000000001
----------000000000
1
- 1
----0
000000000
- 000000001
----------111111111
0
- 1
-----1
111111111
- 000000001
----------111111110
-1
- 1
-----2
111111110
- 000000001
----------111111101
-2
- 1
-----3
110000110
- 000000001
----------110000101
-122
- 1
-----123
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Etc...
Etc...
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77
Data format - Numeric data
FIXED POINT BINARY
How to convert a decimal negative number to binary?
 Convert the correspondent positive number to binary (consider only the significant digits)
 Invert them: 1 becomes 0 and 0 becomes 1
 Add 1
 Fill to the left with 1’s to complete a half-word, a full-word or a double-word
Example: let’s suppose decimal –123;
+123 is 1111011
 Convert the correspondent positive number to binary
 Invert them: 1 becomes 0 and 0 becomes 1
 Add 1
1111011
0000100
0000100
+
1
------0000101
 Fill to the left with 1’s to complete a half-word, a full-word or a double-word
1111111110000101
F
F
8
1111.1111.1111.1111 1111.1111.1000.0101
F
F
8
5
1111.1111.1111.1111.1111.1111.1111.1111.1111.1111 1111.1111.1000.0101
F
F
F
F
F
F
F
F
F
F
F
F
8
5
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78
Data format - Numeric data
FIXED POINT BINARY
How to convert a binary negative number to decimal?
 Subtract it from X’....FFFFFF’ (the 1st X’...F’ number greater than the number to be converted)
 Add 1; result is the POSITIVE desired number. Convert it to negative
Example: let’s suppose X’FFE8’
 Subtract
FFFF
- FF85
---007A
 Add 1
007A
1
---007B
 X’7B’ is the hexadecimal equivalent to decimal 123.
 Desired number is decimal -123
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79
Data format - Numeric data
FIXED POINT BINARY
Number 123
In a half-word
00000000 01111011
X’007B’
In a full-word
00000000 00000000 00000000 01111011
X’0000007B’
In a double-word
00000000 00000000 00000000 00000000 00000000 00000000 00000000 01111011
X’000000000000007B’
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80
Data format - Numeric data
FIXED POINT BINARY
Number - 123
In a half-word
11111111 10000101
X’FF85’
In a full-word
11111111 11111111 11111111 10000101
X’FFFFFF85’
In a double-word
11111111 11111111 11111111 11111111 11111111 11111111 11111111 10000101
X’FFFFFFFFFFFFFF85
’
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81
Data format - Numeric data
FLOATING POINT BINARY
Sorry... It isn’t in the scope of this course
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82
Instruction format
INSTRUCTION FORMAT
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83
Instruction formats
Instructions : main formats
 RR = 2 bytes
 RX = 4 bytes
 RS = 4 bytes
 SI = 4 bytes
 SS = 6 bytes
2 bytes : operation codes between x’00’ and x’3F’
(b’0000 0000’ a
b‘0011 1111’)
4 bytes : operation codes between x’40’ and x’BF’
(b’0100 0000’ a
b‘1011 1111’’)
6 bytes : operation codes between x’C0’ and x’FF’
(b’1100 0000’ a
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b‘1111 1111’)
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Instruction formats
Instructions : main formats
 RR – generally 2 operands, both in general registers
 RX – 2 operands:
1 general register
1 storage field : address specification : Index + [ Base + Displacement ]
 RS – 3 operands, 2 registers and 1 storage field
2 registers (they may indicate a range)
1 storage field : address specification: [ Base + Displacement ]
 SI – 2 operands, both in storage
1 immediate storage (only 1 byte, within the instruction; no need to address it)
1 storage field : address specification : [ Base + Displacement ]
 SS – 2 operands, both storage fields
Both addresses specified as [ Base + Displacement ]
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85
Instruction formats
Instructions : main formats
 RR – (normally) 2 operands, both registers
Operation code
CO
0
5
E
x
F
1st.
Operand
registerx
R1
2nd.
Operand
register
x
R2
Operation code = X’05’
1st operand register = X’E’ (register 14)
2nd operand register = X’F’ (register 15)
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86
Instruction formats
Instructions : main formats
 RX – 2 operands:
1 of them: register
The other one : storage (address specified via
Index register + [ Base register + Displacement ]
Operation code
CO
4
1st.
Operand
registerx
R1
5
E
2nd.
Operand
Index
Register
x
x
X2
0
2o. Operand Base + Displacement
B2
3
D2
C
D2
2
x
x
D2
8
Operation code = X’45’ ; 1st operand register = X’E’ (register 14) ; 2nd operand index register = X’0’
(register 0); 2nd operand base register = X’3’ (register 3); 2nd operand displacement = X’C28’
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87
Instruction formats
Instructions : main formats
 RS – 3 operands, 2 of them are registers, the other one in storage (address
specified via [ Base register + Displacement ] )
Operation code
CO
9
1st.
Operand
Register
R1
8
E
3rd.
Operand
Register
x
x
R3
C
2o. Operand Base + Displacement
B2
D
D2
0
D2
0
x
x
D2
0
Operation code = X’98’ ; 1st operand register = X’E’ (register 14) ; 3rd operand register = X’C’ (register
12); 2nd operand base register = X’D’ (register 13); 2nd operand displacement = X’000’
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88
Instruction formats
Instructions : main formats
 SI – 2 operands, both in storage
1 of them is immediate operand = 1 single byte (it is the instruction 2nd byte)
The other one in storage: address specified via [ Base register + Displacement ]
Operation code
Immediate Operand
1st. Operand Base + Displacement
(2nd. Operand)
x
CO
9
B1
I2
2
5
x
C
5
D1
6
D1
D
x
x
D1
2
Operation code = X’92’ ; 2nd operand (immediate operand) = X’5C’ ; 1st operand base register = X’5’
(register 5); 1st operand displacement = X’6D2’
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89
Instruction formats
Instructions : main formats
 SS-L – 2 operands, both in storage; 1 length specified (valid for both operands).
Both addresses are specified as [ Base register + Displacement ]
Operation code
1st. Operand
Base + Displacement
1st and 2nd
operands length
2o. Operand
Base + Displacement
-1
CO
L
x
x
B1
D1
D1
D1
x
B2
D2
D2
D2
x
D 2 4 F 3 B 9 4 6 F 2 A
Operation code = X’D2’ ; Both operands length = X’4F’ (80 bytes);
1st operand base register = X’3’ (register 3); 1st operand displacement = X’B94’;
2nd operand base register = X’6’ (register 6); 2nd operand displacement = X’F2A’
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90
Instruction formats
Instructions : main formats
 SS-L1/L2 – 2 operands, both of them in storage; 2 lengths specified (1 for each
operand). Both addresses are specified as [ Base register + Displacement ]
Operation code
1st.
Operand
length - 1
CO
L1
2nd.
Operand
length - 1
L2
1st. Operand
Base + Displacement
x
x
B1
D1
D1
2o. Operand
Base + Displacement
D1
x
B2
D2
D2
D2
x
F 8 4 0 3 7 7 E 4 D 6 2
Operation code = X’F8’ ; 1st operand length = X’4’ (5 bytes) ; 2nd operand length = X’0’ (1 byte);
1st operand base register = X’3’ (register 3); 1st operand displacement = X’77E’;
2nd operand base register = X’4’ (register 4); 2nd operand displacement = X’D62’
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91
Instruction formats
Exercise
Solve Exercise 301
See the result here ONLY after trying hard to solve it
Summary
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92
Assembler Language
ASSEMBLER LANGUAGE
Summary
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93
Assembly / linkedit / execution flow
SYSLIB
SYSIN
Macros/Copys
Source prog
SYSUT1
LOADER
IEV90
Work
SYSPUNCH
SYSGO
SYSPRINT
Object prog
Object prog
List
SYSIN
SYSLIN
SYSLIB
Control stmts
Object prog
Other inputs
SYSUT1
IEWL
Work
SYSPRINT
List
Summary
Storage
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LINKLIB
SYSLMOD
Executable
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Assembler program structure
Assembler program structure
Summary
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95
Assembler program structure
It can be this way...
Program
I (Instructions)
A (Areas)
LOAD POINT =
ENTRY POINT
Summary
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96
Assembler program structure
Or this way...
Program
A (Areas)
I (Instructions)
LOAD POINT
Summary
ENTRY POINT
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97
Assembler program structure
This way too...
Program
I
A
I
A
I
A
I
LOAD POINT =
ENTRY POINT
Summary
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98
Assembler program structure
Even like this ...
Program
I
A
I
A
I
A
I
A
I
A
I
A
I
A
I
LOAD POINT =
ENTRY POINT
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99
Assembler program structure
Or like this...
Program
A
I
A
I
A
I
A
I
A
I
A
I
A
I
A
ENTRY POINT
LOAD POINT
Summary
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100
Assembler program structure
Remember that a reentrant program may be like this...
P1 Program
P1 instructions
( manipulating A1, and, concurrently or in parallel,
manipulating A2, manipulating A3, etc... manipulating An)
+
A1
A2
A3
....
An
P1 is in fact:
P1 instructions
Summary
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P1 areas (A1 or A2 or etc)
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101
Assembler program structure
In fact, an Assembler program’ structure may be ...
Anyway !
If you do not branch (GO TO / Jump ) ,
CPU will try to “execute” areas as they were
instructions...
It is the von Newman architecture...
See the blue stripe and the branch just before...
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102
Statement
Assembler STATEMENT
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103
Statement
Positon
Position
Position
Position
1 : With an *, the whole statement is a comment
1 to 8 : Symbol
9 to 14 : Instruction Mnemonic Code
16 to 71: Operands and comments; continuation must begin
from position 16
Position
72 : If filled with any character, indicates that
this statement continues in the next one
Positions 73 a 80: Identification & sequence
123456789012345678901234567890123456789012345678901234567890123456789012
Continuation
*
THIS WHOLE STATEMENT IS A COMMENT
FILLING MVC
PRAREA,=CL133‘ '
COMMENT = CLEARS PRAREA
XI
*+5,X’F0’
COMMENT = FORCE BRANCH
BC
0,TOGGLE
COMMENT = SOMETIMES NOP
*
SOMETIMES BRANCH
HERE
EQU
*
WMESSAGE DC
C’AJK001A – FILE BEING OPENED HAS NO DD STATEMENT IN THE–
JCL. WAKE UP AND INCLUDE IT!.’
HERE WE HAVE A COMMEN
Symbol
Instruction
Summary
Operands & Comments
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104
Statement
Start smelling Assembler way of life...
INIT
TITLE ‘INITIALIZATION ROUTINE'
SEGINIT
DFHEIENT CODEREG=7,DATAREG=(10,11),EIBREG=9
BEGIN
B
BEGIN
SKIP CONSTANTS
DC
C‘HI! COPYRIGHT ARS 2001'
DC
CL17'***VERSION 1.0***'
DC
CL28'***LAST UPDATE 10/23/2001***'
EXEC
CICS ADDRESS CWA(R13)
L
R12,DFHEICAP
LOAD COMMAREA ADDRESS
ST
R13,TWSVCWA
SAVE CWA ADDRESS
LA
R2,TWAREA
LOAD R2 WITH TWAREA ADDRESS
LA
R3,JREND
R3 = JREND ADDRESS
SR
R3,R2
COMPUTE LENGTH
STH
R3,TWLENGTH
STORE LENGTH
SPACE 2
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105
Statement
“Smell” #2
(yellow = Instructions, blue = areas, white = commands to the assembler)
...
COPY COVER
CWA
DSECT
USING *,R13
COPY CWAREA
COPY TADSECT
COMMAREA DSECT
USING *,R12
COPY TWAREA
DFHEISTG DSECT
DFHEISTG
DFHEIEND
EJECT
T131
TITLE ‘SAMPLE PROGRAM‘
SPACE 2
ENTRYPT DFHEIENT CODEREG=(7,9),DATAREG=(10,11),EIBREG=5
B
BEGIN
SKIP CONSTANTS
DC
C‘HI! COPYRIGHT ARS 2001'
DC
CL17'***VERSION 1.0***'
DC
CL28'***LAST UPDATE 10/23/2001***'
BEGIN
L
R12,DFHEICAP
L
R8,TWSVTERM
L
R13,TWSVCWA
... back to program structure ...
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106
Statement
“Smell” #3
(yellow = Instructions, blue = areas, white = commands to the assembler)
...
* ================================================================== *
* SEQUENCE OF INSTRUCTIONS TO BE EXECUTED
*
* ================================================================== *
LA
R2,TRLT
TRLTLOOK CLI
0(R2),X'FF'
TABLE END ?
BE
ERROR
TRLT NOT IN TABLE
CLC
TWDBL(6),0(R2)
IS TRANSACTION CODE IN THE TABLE?
BE
TRL0100
YES
SR
R15,R15
CLEAR REGISTER 15
IC
R15,40(R2)
LOAD R15 WITH INPUT LENGTH
N
R15,=F'127'
ZERO LEFTMOST BIT OF REGISTER 15
AR
R2,R15
POINT TO NEXT ITEM IN THE TABLE
B
TRLTLOOK
BACK TO THE SEARCH
TRL0100 MVC
TWTRLT,0(R2)
MOVE TRLT TO TWA
EXIT
EXEC CICS RETURN
RETURN
ERROR
LA
R2,25
WRONG CODE
OI
TWSW,X'01'
TURN ON CANCEL SWITCH
LA
R3,7
R3 = MESSAGE LENGTH
LA
R1,TWMSG
R1 = MESSAGE WORKAREA ADDRESS
STC
R2,0(R1)
STORE SG NUMBER TO WORKAREA
B
EXIT
RETURN
LTORG
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00000360
00000370
00000410
00000420
00000430
00000440
00000450
00000460
00000470
00000480
00000490
00000500
00000510
00000520
00000530
00000540
00000550
00000560
00000570
00000580
00000590
00000600
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107
Statement
“Smell” #4
(yellow = Instructions, blue = areas, white = commands to the assembler)
...
* ================================================================== * 00000620
* MY MACROS USED TO DEFINE MY CONVERSION DATA
* 00000630
* ================================================================== * 00000640
TRLT
TRLT CODE=000301,
X00001540
TIT=‘NORMAL CREDIT
',
X00001550
MAPN='NOT',
X00001560
PTCM=01,
X00001570
SPEC=14,
X00001580
MNEM=‘NCR'
00001590
TRLT CODE=000302,
X00001600
TIT=‘NORMAL DEBIT
',
X00001610
MAPN=‘YES',
X00001620
PTCM=02,
X00001630
SPEC=14,
X00001640
MNEM=‘NDB'
00001650
END ENTRYPOI
00009330
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108
Assembly program
Assembler elements
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109
Assembly program
Element 1 = Location Counter
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110
Assembly program
Location Counter
There’s 1 for each Section (Control and Dummy)
It is a counter beggining at x’00000000’ and it is
- Incremented each time storage is allocated (e.g. by declaring areas or by
specifying instructions)
- Changed when explicitly demanded by the use of any Assembler
command that affects it (e.g. ORG)
00000
000000
001000
000000
000400
000410
000420
000422
000424
00042C
000434
00043A
000440
000446
00044C
Summary
00000
3400
3410
400040165000502C
6000604270007058
D20F
D215
D22B
D241
D257
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3400
4000
5000
6000
7000
3410
4016
502C
6042
7058
00400
01000
02000
03000
04000
00410
01016
0202C
03042
04058
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
BLOCO1
A
B
*
*
EQU
DS
ORG
DS
DS
DS
.
DC
DC
DC
DC
.
MVC
MVC
MVC
MVC
MVC
*
CL4096
BLOCO1
CL1024
CL16
CL16
.
S(A)
S(B)
S(C,D,E,F)
S(G,H,I,J)
.
A,B
C,D
E,F
G,H
I,J
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111
Assembly program
Element 2 = Output List
(some of the things listed
are also present in the object program)
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112
Assembly program
External Symbol Dictionary :
List of elements that must be treated by the Linkage Editor
and Loader
EXTERNAL SYMBOL DICTIONARY
SYMBOL
TYPE ID ADDR LENGTH LD ID FLAGS
PROGDEMO SD 0001 000000 000AF3
00
FORA
ER 0002
Z
LD
000844
0001
SUBROT
ER 0003
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113
Assembly program
Program List
LOC
00003B
000042
00004A
000052
OBJECT CODE
ADDR1 ADDR2
C1D3C2C5D9E3D6
C1D3C2C5D9E3D65C
C1D3C2C5D9E3C9D5
C8D6
000054 C1D3C2C5D9E3D6
00005B C1D3C2C5D9E3D65C
000063 C1D3C2C5D9E3C9D5
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STMT
SOURCE STATEMENT
49 * VOU MUDAR PARA PRINT DATA
50
PRINT DATA
51
DC
CL7'ALBERTO'
52
DC
CL8'ALBERTO*'
53
DC
CL10'ALBERTINHO'
54 * VOU RESTAURAR O DEFAULT
55
PRINT NODATA
56
DC
CL7'ALBERTO'
57
DC
CL8'ALBERTO*'
58
DC
CL10'ALBERTINHO'
59 *----------------------------------60 * PRINT ON/OFF
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114
Assembly program
Relocation Dictionary : more work to the Linkage Editor and
Loader
RELOCATION DICTIONARY
POS.ID
REL.ID
FLAGS
0001
0001
0C
0001
0001
08
0001
0001
0C
0001
0001
0C
0001
0001
0C
0001
0001
0C
0001
0001
0C
0001
0001
0C
0001
0001
0C
0001
0001
04
Summary
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ADDRESS
000070
0001B9
000860
000864
000868
00086C
000874
0008A4
0008A8
000A46
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115
Assembly program
Cross Reference / Symbol Table
It is being built each time a statement with its own symbol is
encountered.
CROSS REFERENCE
Symbols (labels)
Summary
SYMBOL
AAALIN
ANO
ARIMP
A1
A11
A12
A13
A2
A3
A4
A5
BYTE
BYTEON
CAMPO
CAMPO
COCIENTE
DATA
.
.
LEN
VALUE DEFN
00001
000A68 0272
00002
000AE6 0319
00133
0001C0 0130
00004
000848 0220
00001
000878 0231
00001
000879 0232
00001
000881 0233
00004
00084C 0221
00004
000854 0222
00004
000858 0223
00004
00085C 0224
****UNDEFINED****
00001 000000FF 0085
00001
00008A 0091
00001 00000000 0321
00012 00000074 0082
00006
000AE2 0316
REFERENCES
0297
0129
0229
0231
0232
0233
0230
0225 0226 0227 0261 0262 0263
0285
0092
****DUPLICATE****
0256
Addresses
Length attribute
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116
Assembly program
Remember forever and ever:
If you use a symbol that will be
converted to a
BASE + DISPLACEMENT address
and the conversion isn’t possible
(the assembler is not able to do it):
ADDRESSABILITY ERROR =
There is no base register to “serve” this address.
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117
Assembly program
Diagnostics
DIAGNOSTIC CROSS REFERENCE AND ASSEMBLER S
THE FOLLOWING STATEMENTS WERE FLAGGED
000028 000119 000120 000122 000123 000125 000134 000142 000149 000156 000
000205 000212 000256 000261 000262 000263 000264 000265 000266 000267 000
30 STATEMENTS FLAGGED IN THIS ASSEMBLY
12 WAS HIGHEST SEVERITY CO
OVERRIDING PARAMETERS- LINECOUNT(50),XREF(FULL)
OPTIONS FOR THIS ASSEMBLY
DECK, NOOBJECT, LIST, XREF(FULL), NORENT, NOTEST, NOBATCH, ALIGN, ESD, R
FLAG(0), SYSPARM()
NO OVERRIDING DD NAMES
312 CARDS FROM SYSIN
216 CARDS FROM SYSLIB
572 LINES OUTPUT
73 CARDS OUTPUT
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118
Assembly program
Element 3 = Expressions
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119
Assembly program
EXPRESSIONS
Set of terms with a value and maybe will
be used as an address.
If it’s an address, it may be converted to
base + displacement
format.
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120
Assembly program
EXPRESSIONS
May contain:
- Symbols
- Self-defining terms
(decimal, binary, character or hexadecimal)
- Length attributes
- Location Counter reference
- Arithmetic operators ( + - * / )
- Paired parenthesis
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121
Assembly program
EXPRESSIONS
Examples
Expression
The resulting value corresponds to the
LPOUP
leftmost byte of LPOUP
(Suppose LPOUP address = x’000A000C’; the value of expression LPOUP is x’000A000C’)
This expression : only 1 term: a symbol [LPOUP]
LPOUP+0
leftmost byte of LPOUP
(Suppose LPOUP address = x’000A000C’; the value of expression LPOUP+0 is x’000A000C’)
This expression : 2 terms: 1 symbol [LPOUP] and
1 decimal self-defining term [0]
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122
Assembly program
EXPRESSIONS
Expression
The resulting value corresponds to the
LPOUP+3
4th byte of LPOUP
(Suppose LPOUP address = x’000A000C’; the value of expression LPOUP+3 is x’000A000F’)
This expression : 2 terms: 1 symbol [LPOUP] and
1 decimal self-defining term [3]
LPOUP+15
16th. byte of LPOUP
(Suppose LPOUP address = x’000A000C’; the value of expression LPOUP+15 is x’000A001B’)
This expression : 2 terms: 1 symbol [LPOUP] and
1 decimal self-defining term [15]
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123
Assembly program
EXPRESSIONS
Expression
The resulting value corresponds to the
LPOUP+B’1111’
16th. byte of LPOUP
(Suppose LPOUP address = x’000A000C’; the value of expression LPOUP+B’1111’’ is x’000A001B’)
This expression : 2 terms: 1 symbol [LPOUP] and
1 binary self-defining term [B’1111’]
LPOUP+C’F’
199th. byte of LPOUP
(Suppose LPOUP address = x’000A000C’; the value of expression LPOUP+C’F’’ is x’000A00D2’)
This expression : 2 terms: 1 symbol [LPOUP] and
1 character self-defining term [C’F’]
Note that C’F’ = X’C6’
X’000A000C’ + X’C6’ = X’000A00D2’
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124
Assembly program
EXPRESSIONS
Expression
The resulting value corresponds to the
WAREA+50+X’100’+B’1100’+C’ ’
383th. byte de WAREA
(Suppose WAREA address= x’000A000C’; the value of expression WAREA+50+X’100’+B’1100’+C’ ‘ is
x’000A018A’)
This expression : 5 terms: 1 symbol [WAREA]
1 decimal self-defining term [50]
1 hexadecimal self-defining term [X’100’]
1 binary self-defining term [B’1100’]
1 character self-defining term [C’ ‘]
Note that : Decimal 50 = X’32’; B’1100’ = X’C’ ; C’ ‘ (space) = X’40’
X’32’ + X’100’ + X’C’ + X’40‘ = X’17E’ = decimal 382
X’000A000C’ + X’32’ + X’100’ + X’C’ + X’40’ = X’000A018A’
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125
Assembly program
EXPRESSIONS
Expression
The resulting value corresponds to the
WAREA+L’WAREA
1st byte after (whole) WAREA
This expression : 2 terms: 1 symbol (WAREA) and
1 length attribute [L’WAREA]
WAREA+1
1st byte after the beginning of WAREA
(2nd byte of WAREA)
This expression : 2 terms: 1 symbol (WAREA) and
1 decimal self-defining term [1]
WAREA+L’WAREA-1
last byte of (whole) WAREA
This expression : 3 terms: 1 symbol (WAREA) and
1 length attribute [L’WAREA]
1 decimal self-defining term [1]
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126
Assembly program
EXPRESSIONS
Expression
The resulting value corresponds to the
WAREA+L’FIXDLEN+1000
This expression : 3 terms: 1 symbol (WAREA) +
1 length attribute [L’FIXDLEN] +
1 decimal self-defining term [1000]
Suppose WAREA is composed by
 an area named FIXDLEN +
 an area with 1000 bytes
The value of this expression WAREA+L’FIXDLEN+1000 corresponds to the
first byte after whole WAREA (WAREA + FIXDLEN length + 1000)
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127
Assembly program
EXPRESSIONS
Expression
The resulting value corresponds to the
L’WATERM1+L’WATERM2+L’WATERM3
This expression : 3 terms: 3 length attributes
[L’WATERM1, L’WATERM2, L’WATERM3]
length of WATERM1 area +
length of WATERM2 area +
length of WATERM3 area
Suppose length of WATERM1 is 1000 bytes, length of WATERM2 is 2000
bytes, length of WATERM3 is 3000 bytes (Total length is 6000 bytes [decimal])
The value of the expression L’WATERM1+ L’WATERM2+ L’WATERM3 is
X’1770’
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128
Assembly program
EXPRESSIONS
Expression
The resulting value corresponds to the
*+1
address in the location counter + 1
This expression : 2 terms: 1 Location Counter reference (*) +
1 decimal self-defining term [1]
*+L’WAREA
address in the location counter +
x bytes (x = WAREA length)
This expression : 2 terms: 1 Location Counter reference (*) +
1 length attribute [L’WAREA]
L’COMM+L’REGTYP1 COMM length + REGTYP1 length
This expression : 2 terms: 2 length attributes [L’COMM, L’REGTYP1]
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129
Assembly program
Element 4 = Explicit and Implicit Operand reference
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130
Assembly program
Explicit and implicit operand reference
Registers: allways referenced explicitly
AR
LR
LR
LR
1,6
R5,R14
5,14
R5,14
LR
5,R14
*
*
*
*
Summary
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Syntax OK if there is R5 EQU 5 , but...
Don’t do that! Why reg 5 with symbol
and reg 15 don’t?
Syntax OK if there is R14 EQU 14 , but...
Don’t do that! Why reg 14 with symbol
and reg 5 don’t?
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131
Assembly program
Explicit and implicit operand reference
Storage: explicitly or implicitly referenced
RX instructions :
Explicit reference:
L
L
ST
ST
op reg1st,disp2nd(index2nd,base2nd)
14,12(13)
R14,12(R13) IF EQUATES PROVIDED
7,96(8)
7,96(R8)
IF R8 EQU 8
PROVIDED
Implicit reference:
or
L
L
ST
ST
op reg1st,expression
(assumed index register = 0)
op reg1st,expression(index2nd)
14,SAVE14
14,SAVEAREA+12
7,WSAVEA(7)
7,WSAVAREA+(7*4)
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132
Assembly program
Explicit and implicit operand reference
Storage: explicitly or implicitly referenced
RS Instructions :
Explicit reference :
op reg1st,reg3rd,disp2nd(base2nd)
LM 14,12,12(13)
STM 7,11,0(R12)
Implicit reference :
op reg1st,expression
LM 14,12,SAVEAREA+12
STM 14,12,THERE
Summary
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133
Assembly program
Explicit and implicit operand reference
Storage: explicitly or implicitly referenced
SI Instructions :
Explicit reference :
MVI
XI
OI
op disp1st(base1st),immed2nd
10(R12),C’*’
0(15),X’FF’
15(R8),X’80’
Implicit reference :
MVI
XI
OI
op expression1st,immed2nd
FLAGS+77,C’*’
TOGGLE,X’FF’
PRINTED,X’80’
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134
Assembly program
Explicit and implicit operand reference
Storage: explicitly or implicitly referenced
SS/L Instructions :
Implicit reference :
op
expression1st,expression2nd
(assumed length = length of 1st operand)
*
*
*
MVC
ARIMP+77,C’*’ T-A-K-E C-A-R-E!!!
I THINK THIS IS NOT YOU WANNA DO !!!
MVC
ARIMP+77,=C’*’
I THIS THIS IS NOT ALSO ... !!!
MVC
ARIMP+77(1),=C’*’
WOW ! PROBABLY IT’S THE RIGHT OPTION !!!
CLC
AGENTCOD,CODWANT
(length implicit = length of AGENTCOD)
CLC
IVSAM(3),CODWANT
(length = 3 = explicitly indicated)
CLC
IVSAM+68(3),CODWANT (length = 3 = explicitly indicated)
CLC
IVSAM+68,CODWANT
(length implicit = length of IVSAM)
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135
Assembly program
Explicit and implicit operand reference
Storage: explicitly or implicitly referenced
SS/L Instructions :
Explicit reference : op disp1st(lengthboth,base1st), disp2nd(base2nd)
MVC
CLC
CLC
CLC
CLC
Summary
0(18,7),=C’ERROR’
AGENTCOD,25(14)
AGENTCOD+33,25(14)
AGENTCOD+33(2),25(14)
3(22,8),7(15)
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(length = 18 = explicitly indicated)
(length assumed = length of AGENTCOD)
(length assumed = length of AGENTCOD)
(length = 2= explicitly indicated)
(length = 22 = explicitly indicated)
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136
Assembly program
Explicit and implicit operand reference
Storage: explicitly or implicitly referenced
SS/L1-L2 Instructions :
Implicit reference :
op
expression1st,expression2nd
(1st operand assumed length = length of 1st operand;
2nd operand assumed length = length of 2nd operand)
AP
ZAP
AP
MP
MP
Summary
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COUNTLIN,=P’1’
TOTVAL,=P’0’
BIGTOT,SUBTOT
WNUM,=P’12’
WNUM+44(3),=P’12’
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137
Assembly program
Explicit and implicit operand reference
Storage: explicitly or implicitly referenced
SS/L1-L2 Instructions :
Explicit reference :
op disp1st(length1st,base1st), disp2nd(length2nd,base2nd)
AP
ZAP
AP
MP
Summary
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0(4,3),=P’1’
17(16,12),=P’0’
BIGTOT,127(2,5)
WNUM+44(8),222(3,R6)
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138
Assembly program
Statement types
- Assembler commands
- Machine instructions
- Macro-instructions
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139
Assembly program
Assembler commands
- Area definition: DC, DS, CCW, CCW0, CCW1
- Program sectioning and linking : START, CSECT, DSECT, DXD, CXD,
COM, ENTRY, EXTRN, WXTRN
- Base register control: USING, DROP
-Listing control: TITLE, EJECT, SPACE, PRINT
- Misc control: ICTL, ISEQ, PUNCH, REPRO, ORG, EQU, OPSYN,
PUSH, POP, LTORG, CNOP, COPY, END, LOCTR, AMODE,
RMODE
- Macro instruction definition: AREAD, MACRO, MEXIT, MEND
- Conditional assembly (normally used to do macro instructions): ACTR, AGO,
AIF, ANOP, GBLA, GBLB, GBLC, LCLA, LCLB, LCLC, MHELP,
MNOTE, SETA, SETB, SETC
Summary
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140
Assembly program
(Some) Machine instructions
- Storage to Storage move : MVC, MVZ, MVN, MVI, MVO, ZAP, MVCL, PACK, UNPK, MVCI
- Register to Storage move : ST, STH, STM, STC, STCM, CVD
- Storage to Register move : L, LH, LM, IC, ICM, CVB
- Register to Register move : LR, LPR, LNR, LCR, LTR
- Arithmetic with Storage fields in the packed format : AP, SP, MP, DP, SRP
- Arithmetic with Registers (fixed point binary) : AR, SR, MR, DR, ALR, SLR
- Arithmetic with Register and Storage (fixed point binary) : A, S, M, D, AH, SH, MH, AL, SL
- Compare : CP, CLC, CLI, CLCL, C, CH, CL, CLM, CR, CLR
- Branch : BC, BCR
- Loop Control : BCT, BCTR, BXH, BXLE
- Edition : ED, EDMK
- Byte Translation and test: TR, TRT
- Register Shift : SLL, SRL, SLDL, SRDL, SLA, SRA, SLDA, SRDA
- Boolean Algebra : N, O, X, NR, OR, XR, NI, OI, XI, NC, OC, XC
- Load and branch : BALR, BAL, BAS, BASR, BASSM, BSM
- Misc : LA, TM, EX, SVC, MC, SPM, IPM, STCK, TS, CS, CDS
Summary
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141
Assembly program
Macro-instructions
Installation’s
e.g. ASCEBC, etc...
IBM’s (from operating system, access methods)
DCB (to declare datasets)
OPEN, CLOSE, GET, PUT, READ, WRITE
GETMAIN, FREEMAIN, ATTACH, DETACH
etc...
IBM’s (specific for CICS, DB2, etc...)
DFHMSD, DFHMDF, etc...
Summary
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142
Assembler commands
Assembler commands
Summary
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143
Instructions to the assembler - commands
Assembler commands (alfabetically)
AMODE
DROP
ISEQ
RMODE
CCW
DS
LOCTR
SPACE
CCW0
DSECT
LTORG
START
CCW1
DXD
OPSYN
TITLE
CNOP
EJECT
ORG
USING
COM
END
POP
WXTRN
COPY
ENTRY
PRINT
CSECT
EQU
PUNCH
CXD
EXTRN
PUSH
DC
ICTL
REPRO
These aren’t in the scope of this course): AREAD, MACRO, MEXIT, MEND
ACTR, AGO, AIF, ANOP, GBLA, GBLB, GBLC, LCLA, LCLB, LCLC, MHELP,
MNOTE, SETA, SETB, SETC
Summary
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144
Instructions to the assembler - commands
Assembler commands (by group)
-Source statement and listing control: TITLE, EJECT, SPACE, PRINT,
PUNCH, REPRO, ICTL, ISEQ
- Program sectioning and linking : START, END, CSECT, DSECT, COM,
- Base register control: USING, DROP, POP, PUSH
- Direct Location Counter manipulation: ORG, EQU, CNOP, LOCTR
- Use of external objects or external use of internal objects: ENTRY, EXTRN,
WXTRN, DXD, CXD
- Misc: AMODE, RMODE, COPY, OPSYN
- Declare literals: LTORG
- Area definition: DC, DS, CCW, CCW0, CCW1
- Macro instruction definition: AREAD, MACRO, MEXIT, MEND
- Conditional assembly (normally used to do macro instructions): ACTR, AGO,
AIF, ANOP, GBLA, GBLB, GBLC, LCLA, LCLB, LCLC, MHELP,
MNOTE, SETA, SETB, SETC
Summary
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145
Assembler commands - AMODE
AMODE (Adressing Mode)
This command is used to indicate to the assembler the addressing mode associated to a Control Section.
[symbol]
AMODE
n
n may be 24 or 31 or ANY.
Symbol is optional.
If omitted, the addressing mode will be associated to the blank (no name) Control Section that must exist in the program.
If specified, the addressing mode will be associated to the Contro,l Section with the same name as indicated in the
symbol.
The operand indicates the addressing mode that must be associated with the Control Section. One must specify 24 (24bit addressing), 31 (31-bit addressing) or ANY (the Control Section isn’t sensitive to the addressing mode).
There must be only one AMODE for each Control Section.
The AMODE command may be specified at any point in the program.
AMODE 24 is not compatible with RMODE ANY.
Summary
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Commands
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146
Assembler commands - AMODE
AMODE (Adressing Mode)
If only AMODE or RMODE is specified (or even none of them) the defaults are:
Specified
Assumed
None
AMODE
AMODE
AMODE
RMODE
RMODE
AMODE
RMODE
RMODE
RMODE
AMODE
AMODE
24
31
ANY
24
ANY
Summary
24
24
24
24
24
31
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and
RMODE 24
Commands
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147
Assembler commands – CCW / CCW0 / CCW1
CCW / CCW0 / CCW1 (Channel Command Word)
Sorry. It’s not in the scope of this course.
Summary
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Commands
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148
Assembler commands - CNOP
CNOP (Conditional Nop)
CNOP command aligns the Location Counter to a Half-word boundary.
The skipped bytes are filled with X'0700' (NOPR instruction). Syntax:
CNOP
a,b
Where:
a - 0, 2, 4 or 6. Indicates to what byte positition in a Full-Word or Double-Word the Location Counter must be
advanced.
b - 4 (full-word) or 8 (double-word).
Example:
CNOP
•
•
0,8
0,4
Summary
2,4
•
•
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2,8
2,4
Commands
•
•
4,8
0,4
•
•
6,8
2,4
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149
Assembler commands - COM
COM (Blank Common Control Section)
This command identifies and allocates a commom storage area. It can be referred to by independent modules
linkedited and loaded as a unique program.
No symbols nor operands are allowed.
Only one COM is allowed in each program, although many COM commands may be issued, the first one
indicating the COM beginning, and the others indicating the continuation(s). Sintax:
COM
Example:
CSPRG
START
.
.
COM
DS
DS
.
.
END
A
B
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0
CL3
CL4
Commands
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150
Assembler commands - COPY
COPY
COPY command copies source statements from a source library. Syntax:
COPY
symbol
The symbol refers to the name of the library member to be copied.
Among the copied commands, the commands ICTL or ISEQ are not allowerd.
Example:
COPY
EQUREG
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Commands
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151
Assembler commands - CSECT
CSECT (Control Section)
CSECT command identifies the beginning or the continuation of a Control Section.
[symbol]
CSECT
CSECT command have no operands.
If symbol is specified, it names the CSECT.
Commands and instructions specified after CSECT command will be part of it, up to another CSECT or DSECT
command.
Many CSECT commands with the same symbol may appear in a program. The first one names the CSECT (and is
the range of its first “piece”). The others identify their continuations (the other “pieces”).
To “interrupt” a DSECT, use another DSECT command or a CSECT command.
Summary
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Commands
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152
Assembler commands - CSECT
CSECT (Control Section)
PROG1
CSECT
.
.
.
END
Is the same as
PROG1
START
.
.
.
END
(In both cases) there is a Location Counter (for PROG1 section).
Summary
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Commands
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153
Assembler commands - CSECT
CSECT (Control Section)
PROG1A
PROG1B
PROG1B
START
.
.
CSECT
.
.
CSECT
.
.
END
There is a Location Counter for PROG1A section, another for PROG1B section, and a 3rd to PROG1C section.
Is the same as
PROG1A
PROG1B
PROG1B
CSECT
.
.
CSECT
.
.
CSECT
.
.
END
There is a Location Counter for PROG1A section, another for PROG1B section, and a 3rd to PROG1C section.
Summary
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Commands
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154
Assembler commands - CSECT
CSECT (Control Section)
A
B
C
A
C
CSECT
.
.
CSECT
.
.
CSECT
.
.
CSECT
.
.
CSECT
.
CSECT
CSECT
CSECT
1
A
B
C
=
=
=
1
2
3
+
4
+
5
2
3
4
5
END
There is a Location Counter for A section, another for B section, and a 3rd for C section.
Summary
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Commands
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155
Assembler commands - CSECT
CSECT (Control Section)
CSECTs of last slide is the same as this set of CSECTs:
A
B
C
A
C
START
.
.
CSECT
.
.
CSECT
.
.
CSECT
.
.
CSECT
.
CSECT A = 1
CSECT B = 2
CSECT C = 3
1
+
4
+
5
2
3
4
5
END
There is a Location Counter for A section, another for B section, and a 3rd for C section.
Summary
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Commands
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156
Assembler commands - CXD
CXD (Control Section)
CXD command defines a Full-Word. Linkage Editor (ou o Loader) will put in this full-word the length of all external
DSECTs specified in the source programs (being linkedited or loaded) using this DSECTs. Syntax:
symbol
CXD
No operands are allowed. Example:
TOTALLEN
Summary
CXD
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Commands
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157
Assembler commands - DC
DC (Define Constant)
See detailed description
Summary
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Commands
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158
Assembler commands - DROP
DROP (Por de lado, Deixar)
DROP command indicates to the assembler that one (or more) register(s) previously assigned as base registers
(via USING command) is (are) no longer base register(s) (teh assembler must drop them from the base register
table). Syntax is:
DROP
[R1[,R2,R3 ..........R16]]
Where R1 .........R16 is the list of registers not to be used as base registers anymore. Example:
DROP
3,8
If no operand is specified, all base registers will be unassigned.
Summary
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Commands
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Assembler commands - DS
DS (Define Storage)
See detailed description
Summary
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Commands
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160
Assembler commands - DSECT
DSECT (Dummy Section)
DSECT command defines a section used to do address convertions to Base+Shift format; it doesn’t allocate
areas, it’s just used by the assembler to build the symbol table and determine the displacements of the fields it
contains. It’s often used to describe an area ‘ structure., without phisically allocating storage for it. Syntax is:
symbol
DSECT
DSECT command have no operands.
The symbol names the DSECT.
Many DSECT commands with the same symbol may appear in a program. The first one names the DSECT (and is
the range of its first “piece”). The others identify their continuations (the other “pieces”).
To “interrupt” a DSECT, use another DSECT command or a CSECT command.
Example:
Summary
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Commands
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161
Assembler commands - DSECT
DSECT (Dummy Section)
CSN1
START
.
.
DSECT
DS
DS
DS
DS
CSECT
.
.
END
DSN1
A
B
C
D
CSN1
CL2
CL20
CL10
To use the DSECT fields as instruction’s operands, it’s the programmer’s responsibility to set the base(s)
register(s) up with the correct value(s), and, at codeing time, provide the assembler with the information about
what is the base register(s) for the DSECT (USING command).
Summary
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Commands
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162
Assembler commands - DXD
DXD (Define Dummy External)
DXD command defines an external DSECT. Syntax:
symbol
DXD
operand
Symbol must be referenced as operand ina Q-type constant. It is the external DSECT’ first byte address, and its
length attribute is 1.
The operand has the same syntax as in the DS command. Assembler computes the amount of storage and the
alignment required by the external DSECT, based on the area specified as operand. Example:
CONST
DISPLAC
Summary
DXD
.
.
DC
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5F
Q(CONST)
Commands
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163
Assembler commands - EJECT
EJECT
EJECT command causes a page skip in the sorce listing. No operands allowed.
EJECT
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Assembler commands - END
END
END command must be the last source statement. Syntax:
END
[Symbol]
If symbol is omitted, the first byte of the program is assumed as the ENTRY POINT.
If symbol is specified, the ENTRY POINT is the address indicated by te expression specified as ioperand.
END
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INICIO
Commands
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Assembler commands - ENTRY
ENTRY
This command identifies the symbols defined in the program, abd used externally (in another program). Syntax:
ENTRY
symbol[,symbol...]
In the external program that uses the symbol, it must be defined with an EXTRN command.
* ROUTINE IS DEFINED HERE IN PROG1
PROG1
START
0
.
.
ROUTINE
EQU
*
.
.
ENTRY
ROUTINE
END
Summary
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Commands
* ROUTINE IS REFERENCED HERE IN PROG2
PROG2
START
0
.
.
CONST
DC
A(ROUTINE)
.
.
EXTRN
ROUTINE
END
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Assembler commands - EQU
EQU (Equate - Igualar)
EQU command associates an expression (value / address) to a symbol, adding them (symbol + value) to the
symbol table. Syntax:
Symbol
EQU
a
Symbol
EQU
a,b
Symbol
EQU
a,b,c
Symbol
EQU
a,,c
Where:
a – expression whose value must be associated to the symbol.
b – auto-defined term indicating the length attibute desired to be associated to the symbol..
If b is omitted, the length of the first (or only) term of the expression is assumed to be the length attribute of
the symbol:
--- If it is a Location Counter reference (*), an auto-defined term or a length attribute reference (L’x), 1 is
assumed.
--- If it is a symbol used in a DC or DS, it’s assumed the symbol’s length attribute.
--- If it’s a symbol used in a machine instruction, the length of the instruction is assumed as length attribute
(2,4 or 6 Bytes)
--- If it’s a symbol used in a assembler command (except DC, DS and CCW), 1 is assumed.
c – auto-defined term indicatiing the type attribute desired to be associated to the symbol. If omitted, U assumed.
Summary
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Commands
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Assembler commands - EQU
EQU (Equate - Igualar)
Examples:
R5
EQU
...
LA
5
R5,TABLE
Normally one uses to equate the registers numbers (addresses) to a symbol (e.g. R0 up to
R15 to the general registers, and FP0 etc to the floating point registers), to “force” the
references to them to be listed in the cross-reference produced by the assembler.
INST
EQU
*
LA
R13,SAVEAREA
Is often used rather than
INST
LA
R13,SAVEAREA
Note that the address will probably be the same: the location counter has the same value in
both cases, unless in the first case there’s an area definition with odd nymber of bytes.
The choice for the use of QUE is just for “elegance purposes”.
Note that with the EQU the length attribute for INST symbol is 1, and using the symbol in the
LA instruction the length attribute is 4 (LA instruction length).
Summary
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Commands
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168
Assembler commands - EQU
EQU (Equate - Igualar)
Examples:
OFF
ON
PAID
EQU
EQU
EQU
X'00'
X'FF'
X'80‘
This type of use is common also due to the listing of symbols in the cross-reference.
If one uses the symbols rather than the values in instructions that need a mask, it’s easier to
find (via cross-reference) which are the instructions manipulating the masks; if the autodefined terms are used, no references are listed in the cross-reference.
NI
OI
TM
FLAGUSED,OFF
FLAGERR,ON
FLAGPAY,PAID
RESET USE FLAG
SET ERROR FLAG
TEST PAYMENT
NI
OI
TM
FLAGUSED,X’00’
FLAGERR,X’FF’
FLAGPAY,X’80’
RESET USE FLAG
SET ERROR FLAG
TEST PAYMENT
Rather than
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Commands
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169
Assembler commands - EXTRN
EXTRN (External - Externo)
This command identifies the symbols referred to in the program, but defined externally (in another program).
EXTRN
symbol[,symbol...]
In the program that defines the symbol therre must be an ENTRY command for the symbol.
* ROUTINE IS DEFINED HERE IN PROG1
PROG1
START
0
.
.
ROUTINE
EQU
*
.
.
ENTRY
ROUTINE
END
Summary
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Commands
* ROUTINE IS REFERENCED HERE IN PROG2
PROG2
START
0
.
.
CONST
DC
A(ROUTINE)
.
.
EXTRN
ROUTINE
END
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Assembler commands - ICTL
ICTL (Input Control)
As seen in the assembler statements syntax:
--- Symbol must begin at position 1
--- Last position is 71
--- Continuation (if exists) must begin at position 16
ICTL command, if used, must be the first statement in the source program (only 1 ICTL in the source program),
and it’s used to change the structure above remembered. Syntax:
ICTL
ICTL
ICTL
a
a,b
a,b,c
or
or
Where:
a – specifies the 1st position of the symbols. May be from 1 up to 40.
b – specifies the last position of an instruction (from 41 up to 80); if omitted, 71 is assumed. It must be greater
than or equal to a+1.
c –specifies the continuation position. It may be from 2 up to 40. If omitted or if 80 is specified assembler
assumes that continuation is not allowed.
ICTL
Summary
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4,70,71
Commands
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Assembler commands - ISEQ
ISEQ (Input Sequence)
Indicates to the assembler to validate the input sequence of the source statements.Syntax:
ISEQ
[a,b]
Where:
a – sequence field 1st position
b - sequence field last position
OBS:- a <= b
Wow! It was used when the source statements were in cards, to assure that they weren’t messed!
Summary
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Commands
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Assembler commands - LOCTR
LOCTR (Multiple Location Counters)
This command is used to specify multiple location counters to a Control Section. Syntax:
symbol
LOCTR
The first location counter of a section is automatically defined when assembler gets each first START, CSECT,
DSECT and COM, and it works as if the assembler gets the section name and uses it as the counter’s name .
Using the LOCTR command, one specifies another name, used to christen the 2nd location counter of the
section, and so on.
If one specifies a name already used, the location counter use is resumed.
See the example following
Summary
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Commands
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Assembler commands - LOCTR
LOCTR (Multiple Location Counters)
PROGRAM
PGM1
X
AREA1
AREA2
PGM1
Y
TAB1
TAB2
PGM1
X
AREA11
AREA12
PGM1
Active Loc.Counter
CSECT
.
.
.
LOCTR
DS
DS
LOCTR
.
.
.
LOCTR
DS
DS
LOCTR
.
.
.
LOCTR
DC
DC
LOCTR
LTORG
END
Summary
CL80
CL4
CL10000
CL20000
C'*'
F'0'
Prev.Page
PGM1
PGM1
PGM1
PGM1
X
X
X
PGM1
PGM1
PGM1
PGM1
Y
Y
Y
PGM1
PGM1
PGM1
PGM1
X
X
X
PGM1
PGM1
Commands
part
part
part
part
part
part
part
part
part
part
part
part
part
part
part
part
part
part
part
part
part
part
part
1
1
1
1
1
1
1
2
2
2
2
1
1
1
3
3
3
3
2
2
2
4
4
Generated Object
CSECT PGM1 (with “7 parts”)
PGM1 =
(part 1 of loc counter PGM1) +
(part
(part
(part
(part
(part
(part
2
3
4
1
2
1
of
of
of
of
of
of
loc
loc
loc
loc
loc
loc
counter
counter
counter
counter
counter
counter
PGM1)
PGM1)
PGM1)
X)
X)
Y)
+
+
+
+
+
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Assembler commands - LTORG
LTORG
LTORG command causes the declaration of all literals so far referenced.
Before definition, Location Counter is aligned to a boundary 8 address. Because of this characteristic, you’ll
sometimes find 2 LTORGS one followed by another: the first to align and declare all literals, and the second one
just to align the location counter. One could use , instead of the 2nd LTORG, a CNOP 0,8 or a DS 0D.
No symbol nor operands are allowed.
LTORG
LTORG
, DECLARING LITERALS
LTORG
, ALIGNMENT
Note that to insert the coments, as no operands are allowed, one must insert the comma before the comments to
indicate the operands absence.
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Commands
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175
Assembler commands - LTORG
LTORG
000476 0000 0000 0000 00000 00000
59
IEV044 *** ERROR *** UNDEFINED SYMBOL
00047C D241 6000 B021 03000 00021
60
000482 D257 7000 B02C 04000 0002C
61
000488 D20A B037 B042 00037 00042
62
63 *
00048E 41C0 7FFF
04FFF
64
000492 0000 0000
00000
65
IEV034 *** ERROR *** ADDRESSABILITY ERROR
000496 0000 0000
00000
66
IEV034 *** ERROR *** ADDRESSABILITY ERROR
00049A 58C0 34A8
004A8
67
00049E D20F 3400 34AC 00400 004AC
68
69 *
0004A8
70
0004A8 00005000
71
0004AC 5C
72
73 *
0004AD 00
0004AE D20F 3400 40E4 00400 010E4
74
0004B4 0000 0000
00000
75
IEV034 *** ERROR *** ADDRESSABILITY ERROR
0004B8 58C0 40E0
010E0
76
Summary
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Commands
MVC
E,DSEKCOP3
MVC
MVC
MVC
.
LA
LA
G,DSEKCPO4
I,DSEKCPO5
DSEKCPO6,DSEKCPO7
.
12,Z-1
12,Z+1
LA
12,Z
L
MVC
.
LTORG
.
12,=A(Z)
A,=C'*'
.
,
=A(Z)
=C'*'
.
MVC
LA
A,=C'*'
12,Z
L
12,=A(Z)
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Assembler commands - OPSYN
OPSYN (Operation Synonim)
The OPSYN command establishes an equivalence between a symbol and an operation code of a machine
instruction or an Assembler command. Syntax:
Symbol
OPSYN
[code]
Where:
Symbol – any valid Assembler symbol or operation code (if the operand is omitted).
Code – any valid operation code. If omitted, the command unassigns the operation code previously assigned as
symbol.
The OPSYN command must be inserted after ICTL (if ICTL is present) and can br preceded only by EJECT, ISEQ,
PRINT, SPACE and TITLE. Example:
MYMOVE
MVC
OPSYN
OPSYN
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MVC
Commands
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Assembler commands - ORG
ORG
The ORG command alters the value of the Location Counter, setting it up with the value of the expression
specified as operand. Syntax:
symbol
ORG
[expression]
If the operand is omitted the value set in the Location Counter is the highest it has reached. Example:
Note: the symbols used as ORG operands must be defined before ORG command.
Loc.Counter
Before
.
.
.
0AB84C
0AB94C
0AB93C
0AB946
.
Loc.Counter
After
.
.
.
0AB94C
TABNUM
0AB93C
0AB946
0AB94C
.
Summary
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.
.
.
DC
ORG
DC
ORG
.
Commands
256X'FF'
TABNUM+240
10X'00'
Location Counter reaches 0AB94C
Return to 0AB93C
Reaches 0AB946
Return to the highest so far: 0AB94C
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178
Assembler commands - POP
POP
The POP command restores the PRINT and/or USING status saved by PUSH command. Syntax:
Summary
POP
PRINT
POP
USING
POP
PRINT,USING
POP
USING,PRINT
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Commands
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179
Assembler commands - PRINT
PRINT
The PRINT command is used to control the contents of the listing the assembler produces. Syntax:
PRINT
options
The options must be specified separeated by commas, and they indicate to the assembler what must be printed
or not. Valid options are:
ON
OFF
GEN
NOGEN
DATA
NODATA
-
Listing is produced
Listing not produced (at least until next PRINT ON)
Macro-instruction-generated instructions must be listed.
Macro-instruction-generated instructions mustn’t be listed.
The contents of the defined areas must be listed.
The contents of the defined areas must have its first (or max) 8 bytes listed.
PRINT
OFF,DATA
If no PRINT command is specified (or until it is specified) it is assumed
PRINT
ON,GEN,NODATA
One can use as many PRINT commands as necessary / desired.
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Commands
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180
Assembler commands - PUNCH
PUNCH
The PUNCH command indicates to the Assembler to write to the object file 1 record which value is the value
specified as the PUNCH operand. Syntax:
PUNCH
a
Where a is a string from 1 to 80 characters between apostrophes. If the character is an apostrophe (') or an
ampersand (&), it must be twice specified. Example:
PUNCH
'
CATALR
MOD'
The result record is:
pos
pos
pos
pos
pos
Summary
1-2
3-8
9-10
11-13
14-80
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:
:
:
:
:
spaces
CATALR
spaces
MOD
spaces
Commands
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181
Assembler commands - PUSH
PUSH
The PUSH command saves the status of PRINT and USING. Syntax:
PUSH
PUSH
PUSH
PUSH
Summary
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PRINT
USING
PRINT,USING
USING,PRINT
Commands
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182
Assembler commands - REPRO
REPRO
The REPRO command indicates to the Assembler to write to the object file 1 record which value is the value of
the statement following the REPRO command. No symbol nor operands are allowed.
CATALR
REPRO
MOD
At this point a record with “CATALR
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MOD” is written to the SYSPUNCH file.
Commands
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183
Assembler commands - RMODE
RMODE (Residence Mode)
This command is used to indicate to the assembler the residence mode associated to a Control Section.
[symbol]
RMODE
n
n may be 24 or ANY.
Symbol is optional.
If omitted, the residence mode will be associated to the blank (no name) Control Section that must exist in the
program.
If specified, the residence mode will be associated to the Contro,l Section with the same name as indicated in the
symbol.
The operand indicates the residence mode that must be associated with the Control Section. One must specify
24 (24-bit residence = the CSECT must reside bellow the 16MB line), or ANY (24-bit or 31-bit residence = the
CSECT may reside bellow or above the 16MB line).
There must be only one RMODE for each Control Section.
The RMODE command may be specified at any point in the program.
RMODE ANY is not compatible with AMODE 24.
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Commands
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184
Assembler commands - RMODE
RMODE (Residence Mode)
If one specifies only AMODE or RMODE (or even none of them) the defaults are:
Specified
Assumed
None
AMODE
AMODE
AMODE
RMODE
RMODE
AMODE
RMODE
RMODE
RMODE
AMODE
AMODE
24
31
ANY
24
ANY
Summary
24
24
24
24
24
31
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and
RMODE 24
Commands
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185
Assembler commands - SPACE
SPACE
The SPACE command, when detected by the assembler, results in a skip of n lines in the SYSPRINT listing,
where n is specified in the operand (if omitted, 1 is assumed).
SPACE
[n]
SPACE
3
Example:
Summary
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Commands
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186
Assembler commands - START
START
This command sets the initial value in the LOCATION COUNTER. It must be one of the first commands in the
source program (it can’t have any instruction or command that alters the Location Counter before the START
command). The syntax is:
[symbol]
START
a
where:
Symbol: START command defines the first Control Section (CSECT) of the program. If the symbol is specified, it
will be the section’s name. If not specified, the first control section is considered as no name.
a = Auto-defined term = its value must be multiple of 8.Tit indicates the initial value of the Location Counter.
If omitted, zero is assumed.
PROG1
START
X'308'
START
10240
If START command is omitted,
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START 0
Commands
is assumed.
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Assembler commands - TITLE
TITLE
The TITLE command specifies the title of the listing produced by the Assembler. Syntax:
[symbol]
TITLE
a
Symbol --- in VSE : 1 to 4 characters (it will be used to fill positions 73 to 76 of the object program records).
a -- 1 to 100 characters string between apostrophes. If a character must be an apostrophe (') or an ampersand
(&), it must be twice specified.
Example:
P001
TITLE
'EMISSAO NOTAS FISCAIS'
At each TITLE command a page skip is provided.
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Commands
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188
Assembler commands - USING
USING (Usando)
The USING command is used to provide addressability to symbols, by indicating to the Assembler:
a) The value of the 1st base register (1st operand)
b) The base register(s) of the program (2nd operand, 3rd operand and so on)
Syntax:
USING
a,1br[,2br,[3br] .......[16br]]
Where a is an expression indicating to the Assembler the value the first base register [1br] is assumed to have
when the program is running.
If a second base register [2br] is specified, it is assumed to have a+4096 when program is running.
If a third base register [3br] is specified, it is assumed to have a+8192 when program is running. And so on.
USING
*,3,8
In this example: registers 3 and 8 are the base registers.
Register 3 is assumed to have the value of the Location Counter when the program is running.
Register 8 is assumed to have the value of the Location Counter+4096 when the program is running.
Note that the USING command only warns the Assembler about the value at execution time; it DOES NOT LOAD
the value. It’s the programmer’s responsibility to load the correct value (in the example corresponding to the
values of the Location Counter and Location Counter+4096.
Normally one uses the BALR instruction to load the first base register and LA to load the other ones.
For DSECTs : specify the DSECT symbol as the first operand.
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Commands
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189
Assembler commands - WXTRN
WXTRN (Weak Extrn)
This command is similar to the EXTRN command, but:
- with the EXTRN command the Linkage Editor searches autoimatically the libraries to find the modules that
contains the symbols specified as operands in teh EXTRN command(s).
- with the WXTRN command no auto search is provided. The references will be solved by the Linkage Editor only
if the specified symbols are defined:
-- in a module link-edited and loaded together with the program with the WXTRN command OR
-- in a module linked from a library because it has an EXTRN command in another module (linkedited and loaded
together with the program with WXTRN).
Syntax:
WXTRN
symbol[,symbol ....... ]
Example:
WXTRN
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MOD
Commands
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Assembler commands - Defining areas
Defining Areas
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Commands
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191
Assembler commands - Defining areas
DC = Define Constant
to define areas WITH contents (storage allocation, with
contents, with a name [symbol], address [value], length
attribute and type attribute)
DS = Define Storage
to define areas WITHOUT contents (storage allocation, with a
name [symbol], address [value], length attribute and type
attribute)
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Commands
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192
Assembler commands - Defining areas
What does exactly mean to allocate an area without contents
(without an initial value)?
(e.g. DS in Assembler, or a field declared without the VALUE clause in Cobol)
Executable
Storage
LOADER
???????????
???????????
Instructions
Areas with contents (DC)
Areas without contents (DS)
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Commands
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193
Assembler commands - Defining areas
General syntax:
Da = duplication attibute: how many areas to define
Type = contents (value) type; it’s used to attribute the value
and to establish the length attibute if La is not specified.
NO validation is done at assembly time.
La = Length attribute
Ic = initial contents (value)
[name]
DC
[Da]type[La]Ic
[name]
DS
[Da]type[La][Ic]
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Commands
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194
Assembler commands - Defining areas
Examples:
[name]
DC
[Da]type[La]Ic
SEPARAT1 DC 132CL1’*’ Da=132;Type=C;La=L1;Ic=‘*’
* Declares 132 areas, 1 byte each (all 132 bytes with *)
SEPARAT2 DC CL132’*’ Da=omitted;Type=C;La=L132;Ic=‘*’
* Declares 1 area, length=132 bytes ( 1st byte has * all others with spaces )
CONTLIN
DC PL2’99’
Da=omitted;Type=P;La=L2;Ci=‘99’
* Declares 1 area 2 bytes long (value=99 in packed decimal)
ADRSTAB
DC A(TABAGE) Da=omitted;Type=A;La=omitted;Ic=(TABAGE)
*
Declares 1 área 4 bytes long (value = address of TABAGE)
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Commands
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195
Assembler commands - Defining areas
Examples:
[name]
DS
[Da]type[La][Ic]
SEPARAT1 DS 132CL1
Da=132;Type=C;La=L1;Ic=omitted
* Declares 132 areas, 1 byte each (NO INITIAL CONTENTS)
SEPARAT2 DS CL132
Da=omitido;Type=C;La=L132;Ic=omitted
* Declares 1 area, length=132 bytes (NO INITIAL CONTENTS)
CONTLIN
DS PL2
Da=omitted;Type =P;La=L2 ;Ic=omitted
* Declares 1 area 2 bytes long (NO INITIAL CONTENTS)
ADRSTAB
DS A
Da=omitted;Type =A;La=omitted ;Ic=omitted
* Declares 1 area 4 bytes long (NO INITIAL CONTENTS)
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Commands
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196
Defining areas – DC (define constant)
DC - Define Constant
Area WITH value (initial contents)
Summary
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Commands
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197
Assembler commands - Defining areas - Summary
Area types - summary
Typ
e
Length
assumed
Alignment
Valid
Length
Constants
p/operand
Filled
From-To
Filled
with
Truncat
ed at
Valid
characters
Each
char
C
enough
byte
1 to 256
1
LR
spaces
Right
qualquer
1 byte
X
enough
byte
1 to 256
multiple
RL
X’0’
Left
0 to F
½ byte
B
enough
byte
1 to 256
multiple
RL
B’0’
Left
0 to 1
1 bit
F
4 bytes
FullWord
1 to 8
multiple
RL
(1)
Left
+ - 0 to 9
(2) (4)
H
2 bytes
HalfWord
1 to 8
multiple
RL
(1)
Left
+ - 0 to 9
(3) (4)
P
enough
Byte
1 to 16
multiple
RL
X’0’
Left
+ - 0 to 9
½ byte (5)
Z
enough
Byte
1 to 16
multiple
RL
C’0’
Left
+ - 0 to 9
1 byte
D
8 bytes
DoubWord
1 to 8
multiple
-x-
-x-
-x-
+ - 0 to 9
-x-
A
4 bytes
FullWord
1 to 4
multiple
LR
B’0’
Left
expression
-x-
Y
2 bytes
HalfWord
1 to 2
multiple
LR
B’0’
Left
expression
-x-
S
2 bytes
HalfWord
2
multiple
-x-
-x-
-x-
expression
-x-
remarks:- (1) 0's if positive number; 1's if negative number
(2) Up to 2**31 - 1
(3) Up to 2**15 - 1
(4) Decimal-point does not use any space
(5) The sign uses 1/2 byte
Summary
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Commands
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198
Defining areas – Type C (character)
C-type DC (character)
[name]
Summary
DC
Prev.Page
[Da]C[La]Ic
DC/DS Summary
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199
Defining areas – Type C (character)
Each character occupies 1 bytes (EBCDIC format)
If no length attribute specified: assumed (the default is) the enough to fit the initial contents.
If length attribute (La) specified: the La will be considered rather than the enough to fit the value.
If La specified is greater than the enough to fit the value, the remaining bytes to the right will be
filled with spaces (X'40').
If the length attribute specified is less than the enough to fit the value specified, the rightmost
characters of the value will be truncated (error will be flagged).
Se o tamanho for insuficiente, será feito truncamento à direita (e será indicado erro).
Maximum length = 256 bytes.
When the desired character in value is apostrophe (“’”) or ampersand (“&”) it is needed to specify it
twice.
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
Summary
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DC/DS Summary
1CL1'*'
2CL1'*'
CL1'*'
CL2'*'
2CL2'*'
C'ABC'
CL1'ABC'
C'A&&B'
C‘JO''S'
C''''
5C
5C5C
5C
5C40
5C405C40
C1C2C3
C1
C150C2
D1D67DE2
7D
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200
Defining areas – Type X (hexadecimal)
X-Type DC (hexadecimal)
[name]
Summary
DC
Prev.Page
[Da]X[La]Ic
DC/DS Summary
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201
Defining areas – Type X (hexadecimal)
Valid characters: hexadecimal algarisms (0 to F)
Each hexadecimal algarism occupies ½ byte.
Field is filled from right to left.
If La specified is greater than the enough to fit the value, the remaining half-bytes to the left will be
filled with x’0’.
If La specified is less than the enough to fit the value, the leftmost half-bytes will be truncated.
Maximum length = 256 bytes.
Multiple definitions per constant are allowed (see last example).
DC
DC
DC
DC
DC
DC
Summary
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DC/DS Summary
1XL1'0B'
3X'5C'
XL3'5C'
XL2'AB0C14'
X'1A2'
X'00A,B,5A8'
0B
5C5C5C
00005C
0C14
01A2
000A0B05A8
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202
Defining areas – Type B (binary)
B-type DC (binary)
[name]
Summary
DC
Prev.Page
[Da]B[La]Ic
DC/DS Summary
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203
Defining areas – Type B (binary)
Valid characters: binary algarisms (0 and 1)
Each binary algarism occupies 1 bit.
Field is filled from right to left.
If La specified is greater than the enough to fit the value, the remaining bits to the left will be filled
with binary zeros.
If La specified is less than the enough to fit the value, the leftmost bits will be truncated.
Maximum length = 256 bytes.
Multiple definitions per constant are allowed (see last example).
DC
DC
DC
DC
DC
DC
Summary
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DC/DS Summary
BL1'0'
BL2'010001001'
B'0101'
BL2'1'
2B'1'
B'1,00101,001'
00
0089
05
0001
0101
010501
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204
Defining areas – Type F (full word)
F-type DC (full-word)
[name]
Summary
DC
Prev.Page
[Da]F[La]Ic
DC/DS Summary
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205
Defining areas – Type F (full word)
The value must be specified in decimal (Assembler will convert it to binary to fill the full-word)
If no sign is specified, number will be assumed positive.
If sign is specified, it must be unique, and must come before the value.
If no La is specified, ALIGNMENT will be done to next address multiple of 4, before the area
allocation.
If La is specified, NO ALIGNMENT will be done.
Maximum length = 256 bytes.
Multiple definitions per constant are allowed (see last example).
DC
DC
DC
DC
Summary
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F'138'
F'+138'
F'-138'
F'4,392'
DC/DS Summary
0000008A
0000008A
FFFFFF76
0000000400000188
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Defining areas – Type H (half word)
H-type DC (half-word)
[name]
Summary
DC
Prev.Page
[Da]H[La]Ic
DC/DS Summary
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207
Defining areas – Type H (half word)
The value must be specified in decimal (Assembler will convert it to binary to fill the half-word)
If no sign is specified, number will be assumed positive.
If sign is specified, it must be unique, and must come before the value.
If no La is specified, ALIGNMENT will be done to next address multiple of 2, before the area
allocation.
If La is specified, NO ALIGNMENT will be done.
Maximum length = 256 bytes.
Multiple definitions per constant are allowed (see last example).
DC
DC
DC
DC
Summary
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H'138'
H'+138'
H'-138'
H'4,392'
DC/DS Summary
008A
008A
FF76
00040188
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208
Defining areas – Type P (packed)
P-type DC (Packed)
[name]
Summary
DC
Prev.Page
[Da]P[La]Ic
DC/DS Summary
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209
Defining areas – Type P (packed)
The value must be specified in decimal. Each decimal algarism occupies ½ byte, plus ½ byte to the
sign. Maximum length = 16 bytes (31 algarisms). Field is filled from right to left.
If La specified is greater than the enough to fit the value, the remaining half-bytes to the left will be
filled with binary zeros.
If La specified is less than the enough to fit the value, the leftmost half-bytes will be truncated.
If no La is specified, it will be allocated the enough to fit the value (including ½ byte for the sign).
Remember that if you specify an even number of algarisms, it will be needed one more half-byte to
complete the field.
Multiple definitions per constant are allowed (see 3rd example).
DC
DC
DC
DC
DC
DC
DC
DC
Summary
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P'122'
P'10'
P'-345,45,21.6,7'
P'0'
P'+66'
PL3'1'
PL2'43556'
3P'1'
DC/DS Summary
122C
010C
345D045C216C7C
0C
066C
00001C
556C
1C1C1C
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Defining areas – Type Z (zoned)
Z-type DC (zoned)
[name]
Summary
DC
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[Da]Z[La]Ic
DC/DS Summary
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211
Defining areas – Type Z (zoned)
The value must be specified in decimal. Each decimal algarism occupies 1 byte.
Maximum length = 16 bytes (16 algarisms). Field is filled from right to left.
If La specified is greater than the enough to fit the value, the remaining half-bytes to the left will be
filled with zoned zeros (x’F0’).
If La specified is less than the enough to fit the value, the leftmost bytes will be truncated.
If no La is specified, it will be allocated the enough to fit the value.
Multiple definitions per constant are allowed (see 2nd example).
DC
DC
DC
DC
DC
DC
Summary
Z'122'
Z'-345,45'
Z'+66'
ZL3'1'
ZL2'43556'
3Z'1'
Prev.Page
DC/DS Summary
F1F2C2
F3F4D5F4C5
F6C6
F0F0C1
F5C6
C1C1C1
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212
Defining areas – Type A (address)
A-type DC (address)
[name]
Summary
DC
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[Da]A[La]Ic
DC/DS Summary
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213
Defining areas – Type A (address)
The value must be specified as an expression (Assembler will convert it to a value / address to fill
the full-word)
If no La is specified, ALIGNMENT will be done to next address multiple of 4, before the area
allocation.
If La is specified, NO ALIGNMENT will be done.
Multiple definitions per constant are allowed (see last example).
CAMPO
DC
DC
DC
DC
DC
DC
DC
DC
Summary
A(TABELA)
A(TABELA-50)
A(*)
A(259)
3A(*-CAMPO)
A(TCABC+28*52)
A(FIM-COMECO)
A(1,2,3)
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DC/DS Summary
00000103
00000000.00000004.00000008
00000001.00000002.00000003
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Defining areas – Type A (address)
IMPORTANT:
Addresses with relocatable values (green) are updated by Linkage Editor and
Loader; the absolute addresses (red) keep unchanged .
CAMPO
DC
DC
DC
DC
DC
DC
DC
DC
Summary
A(TABELA)
A(TABELA-50)
A(*)
A(259)
3A(*-CAMPO)
A(TCABC+28*52)
A(FIM-COMECO)
A(1,2,3)
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DC/DS Summary
00000103
00000000.00000004.00000008
00000001.00000002.00000003
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215
Defining areas – Type A (address)
Example:
(part of a program)
0008A0 47F0 38AC
008AC
008A4
0008A4 000008B2
0008A8 000008B5
008AC
244+
245+IHB0004
246+
247+
248+IHB0004A
B
EQU
DC
DC
EQU
IHB0004A
*
A(ENTRA)
A(SAI)
*
(part of the RELOCATION DICTIONARY of the program)
RELOCATION DICTIONARY
POS.ID
REL.ID
FLAGS
0001
0001
0C
0001
0001
08
0001
0001
0C
0001
0001
0C
0001
0001
0C
0001
0001
0C
0001
0001
0C
0001
0001
0C
0001
0001
0C
0001
0001
04
0001
0001
04
0001
0001
04
0001
0001
04
Summary
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ADDRESS
000070
0001B9
000860
000864
000868
00086C
000874
0008A4
0008A8
000A46
000A48
000A54
000A56
DC/DS Summary
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216
Defining areas – Type A (address)
Example:
Souce program (VALIDATE routine;
suppose that VALIDS address is
X’00001BC0’)
...
VVV
...
...
...
VALIDS
...
DC
Assembler
A(VALIDS)
DC
C’AEIOUaeiou’
Object program to be called
(suppose length = 4K = X’1000’)
...
00001BC0
...
...
...
C1C5C9D6E481858996A4
...
Caller : from X’0000’ to X’9FFF’)
Caller (main) object program
(suopose length = 40K =
X’A000’)
...
...
...
CALL VALIDATE
...
...
...
Caller : from X’0000’ to X’9FFF’)
Lked
Adds called routine to the
caller program and ADJUSTS
the relocatable address
variables.
Called routine: starting address =
X’A000’ : occupies in the executable
from X’A000’ to X’AFFF’
VVV contents is adjusted to
X’0000BBC0’
...
0000BBC0
...
Executable
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217
Defining areas – Type A (address)
Example:
Storage
Executable program
...
0000BBC0
...
Loader
Loads the executable program
into storage (e.g. at address
X’0BC40000’) and ADJUSTS the
relocatable address constants.
Executable program loaded (LOAD
POINT) at address X’0BC40000’
...
0BC4BBC0
...
VVV contents is adjusted to
X’0BC40000’ + X’0000BBC0’ =
X’0BC4BBC0’
Load Point = X’0BC40000’
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218
Defining areas – Type Y (2-byte address)
Y-type DC (address with 2 bytes)
[name]
Summary
DC
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[Da]Y[La]Ic
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219
Defining areas – Type Y (2-byte address)
The value must be specified as an expression (Assembler will convert it to a value / address to fill
the half-word)
If no La is specified, ALIGNMENT will be done to next address multiple of 2, before the area
allocation.
If La is specified, NO ALIGNMENT will be done.
Multiple definitions per constant are allowed (see last example).
Note that the maximum allowed value is x'FFFF‘.
DC
DC
DC
DC
DC
DC
DC
Y(TABELA)
Y(TABELA-50)
Y(*)
Y(259)
Y(TCABC+28*52)
Y(FIM-COMECO)
Y(1,2,3)
0103
0001.0002.0003
IMPORTANT:
Addresses with relocatable values are updated by Linkage Editor and Loader; the
absolute addresses keep unchanged .
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220
Defining areas – Type S (Base+Shift address)
S-type DC (base + shift address)
[name]
Summary
DC
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[Da]S[La]Ic
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221
Defining areas – Type S (Base+Shift address)
The value must be specified as an expression (Assembler will convert it to a base+shift addres to fill
the half-word)
If no La is specified, ALIGNMENT will be done to next address multiple of 2, before the area
allocation.
If La is specified, NO ALIGNMENT will be done.
Multiple definitions per constant are allowed (see last example).
DC
DC
DC
DC
DC
Summary
S(TABELA)
S(TABELA-50)
S(*)
S(TCABC+28*52)
S(*,*+2,*+4)
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Defining areas – Type V (external address)
V-type DC (external address)
[name]
Summary
DC
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[Da]V[La]Ic
DC/DS Summary
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223
Defining areas – Type V (external address)
It is analogue to the A-type constant, with the difference that the address is not possible to be
solved at assembly time due to external symbol reference (e.g. an external routine).
The value is set to zero, and is filled in the object program at linkedit / load time.
DC
Summary
V(ROUTINE)
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224
Defining areas – Type Q (external DSECT address)
Q-type DC (external DSECT shift)
[nome]
Summary
DC
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[ad]Q[at]ci
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225
Defining areas – Type Q (external DSECT address)
This constant is used to do reference to a shift in an external DSECT.
The value is set to zero, and is filled in the object program at linkedit time.
The value must be specified as an expression (Assembler will conThe symbol refered to in the
value must be previously externally defined as a DXD symbol or as a DSECT.
DC
Summary
Q(DUMMYEXT)
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Defining areas - DS
DS - Define Storage
Areas WITHOUT initial contents
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227
Defining areas - DS
DS command is used to define an area without initial contents.
The syntax is analogue to the DC command.
WARNING! If initial contents is specified it WON’T BE CONSIDERED.
Summary
DS
CL3
DS
XL4
DS
PL4'0'
DS
3CL8
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228
Defining areas - DS
DS command allows zero (0) duplication attribute. Examples:
READAREA
DS
0CL80
CODE
DS
CL10
DATE
DS
CL8
NAME
DS
CL50
CITY
DS
CL12
The duplication attribute does not define any area, it only “warns” that the
next 80 bytes will be the area named READAREA (READAREA length
attribute is 80).
In other words, the field starting at the byte pointed by the Location
Counter is 80 bytes length and is named READAREA.
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229
Defining areas - DS
The duplication attribute zero is often used to do alignment:
FLDWITH4
DS
0F
BYTE1
DS
CL1
BYTE2
DS
CL1
BYTE3
DS
CL1
BYTE4
DS
CL1
In this case, the assembler:
- aligns to the next boundary 4 address (address multiple of 4) due to the
F-type specified), and then allocates the fields BYTE1, BYTE2, BYTE3 e
BYTE4.
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230
Defining areas - DS
Another example of alignment use:
ALFA
DC
F’0’
BETA
DC
C’XYZ’
DS
0H
GAMA
DS
CL1
DELTA
DS
CL1
Alfa
Beta
Gama Delta
(no
name)
ALFA is aligned because the F-type constant do the alignment.
BETA is aligned due to the alignment and length of ALFA.
GAMA, if it was declared just after BETA, won’t be aligned because BETA
has 3 bytes. To align GAMA (to a boundary 2 address) it was included the
H-type DS declaration with duplication attribute of zero.
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231
Defining areas - DS
Another use of DS command is to redefine areas (to attribute different names to same physical areas).
See bellow:
AREA1
A1PART1
A1PART2
A1PART3
A1PART4
A1PART5
A1PART6
A1PART7
A1PART8
AREA2
A2PART1
A2PART2
A2PART3
A2PART4
AREA3
A3PART1
A3PART2
A3PART3
A3PART4
A3PART5
A3PART6
A3PART7
DS
DS
DS
DS
DS
DS
DS
DS
DS
ORG
DS
DS
DS
DS
DS
ORG
DS
DS
DS
DS
DS
DS
DS
DS
Summary
0CL80
CL10
CL10
CL10
CL10
CL10
CL10
CL10
CL10
, RETURN TO AREA1 ADDRESS
0CL80
CL20
CL20
CL20
CL20
, RETURN TO AREA1 ADDRESS
0CL80
CL5
CL5
CL20
CL30
CL3
CL4
CL13
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DC/DS Summary
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Machine Instructions
MACHINE INSTRUCTIONS
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233
Machine Instructions – Hints and Tips
Hints and Tips
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234
Machine Instructions – Hints and Tips 1
1 - STORE = FROM register TO storage
2 - LOAD = FROM storage TO register
3 - xxxxR = RR instruction, operands are both registers
Example: AR,SR, LR, MR, DR, LTR
4 - xxxxI = SI instruction, 1 operand is an immediate operand;
it is the 2nd byte of the instruction, and is specified via an
self-defining term (1 byte length)
Example: MVI, SI, NI, OI, XI, etc
5 - xxxxP = SS instruction, decimal packed operands, 2
lengths specification
Example: AP, SP, MP, DP, ZAP
6 - xxxxH = RX instruction, operands are 1 register and 1
halfword storage field
Example: LH, SH, AH
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235
Machine Instructions – Hints and Tips 2
7 - Nxxxx = boolean instruction AND
Example: NI, NC, N, NR
8 - Oxxxx = boolean instruction OR
Example: OI, OC, O, OR
9 - Xxxxx = boolean instruction Exclusive OR
Example: XI, XC, X, XR
10 - Most instructions (except CVD and the STORE ones STC, ST,
STH, STCM, STM):
symbol instruction receiver_operand,emitter_operand
11 - STORE and CVD instructions:
symbol instruction emitter_operand,receiver_operand
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236
Machine Instructions – Hints and Tips 3
12 - SS-L instructions (only one length) are:
MVN, MVC, MVZ, NC, CLC, OC, XC,
TR, TRT, ED, EDMK, MVCIN
Maximum length of each operand is 256 bytes.
13 - SS-L1/L2 instructions (2 lengths) are:
MVO, PACK, UNPK, ZAP, CP, AP, SP, MP, DP
Maximum length for each operand is 16 bytes.
14 – SRP instruction is an exception in the SS group: it has a
reference to a length (1st half of the 2nd byte), and a round
(in the other half of the 2nd byte)
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237
Machine Instructions – Hints and Tips 4
15 – Use of Boolean instructions:
OR = To force bits to 1 (turn ON bits)
This can be used to (for instance) :
(a) Set program flags to ON
(b) Transform lowercase leters into uppercase letters
(mask 0100 0000 : note in an EBCDIC table that the difference
between lowercase and uppercase letters is always
x’40’ (b’0100 0000’); turning the 2nd bit ON one can transform
a lowercase letter into an uppercase letter.
(c) Transform a binary number into the nearest high odd number
(turning rightmost bit ON)
Example: 1111 1110 is decimal 254. Turning rightmost bit ON:
1111 1111 it becomes decimal 255
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238
Machine Instructions – Hints and Tips 4
15 – Use of Boolean instructions:
AND = Force bits to 0 (turn bits OFF)
This can be used to (for instance) :
(a) Set program flags to OFF
(b) Transform uppercase leters into lowercase letters
(mask 1011 1111 : note in an EBCDIC table that the difference
between uppercase and lowercase letters is always
x’40’ (b’0100 0000’); turning the 2nd bit OFF one can transform
an uppercase letter into a lowercase letter.
(c) Transform a binary number into the nearest low even number
(turning rightmost bit OFF)
Example: 1111 1111 is decimal 255. Turning rightmost bit OFF:
1111 1110 it becomes decimal 254
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239
Machine Instructions – Hints and Tips 4
15 – Use of Boolean instructions:
XOR (ou exclusivo) = To invert bit setting
(turns OFF if it is on, turns ON if it is OFF)
This can be used to (for instance) :
(a) Inverte program flags (toggle flags)
(b) Transform lowercase into uppercase letter and vice-versa
(mask 0100 0000) :
letter x1xx xxxx becomes x0xx xxxx
letter x0xx xxxx becomes x1xx xxxx
(c) Transform binary even numbers into odd numbers and viceversa: (mask 0000 0001) : rightmost bit is inverted
(d) Exchange the contents of 2 area without a 3rd auxiliary area :
XOR A,B + XOR B,A + XOR A,B
(e) “Clear” (move binary zeros) an area :
XOR A,A
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240
Machine Instructions – Hints and Tips 4
16 – Arithmetic and bit shift operations (algebraic / logic operations):
Unless othewise stated, these operations are done algebraically.
This is always true for decimal packed fields.
For binary fixed point numbers (in storage and/or registers) some operations that
work algebraically and other operations work logically.
Algebraic operations uses:
15-bit binary numbers + 1 bit sign for 2 byte numbers
31-bit binary numbers + 1 bit sign for 4 byte numbers
63-bit binary numbers + 1 bit sign for 8 byte numbers
Logical operations assume numbers are always positive and uses:
16-bit binary numbers for 2 byte numbers
32-bit binary numbers for 4 byte numbers
64-bit binary numbers for 8 byte numbers
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241
Machine Instructions
Machine instructions (alphabetically)
A
BCR
CLI
EDMK
LR
MVO
SH
SRDL
TRT
AH
BCT
CLM
EX
LTR
MVZ
SL
SRL
TS
AL
BCTR
CLR
IC
M
N
SLA
SRP
UNPK
ALR
BSM
CP
ICM
MC
NC
SLDA
ST
X
AP
BXH
CR
IPM
MH
NI
SLDL
STC
XC
AR
BXLE
CS
L
MP
NR
SLL
STCK
XI
BAL
C
CVB
LA
MR
O
SLR
STCM
XR
BALR
CDS
CVD
LCR
MVC
OC
SP
STH
ZAP
BAS
CH
D
LH
MVCIN
OI
SPM
STM
BASR
CL
DP
LM
MVCL
OR
SR
SVC
BASSM
CLC
DR
LNR
MVI
PACK
SRA
TM
BC
CLCL
ED
LPR
MVN
S
SRDA
TR
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242
Machine Instructions
(Some) Machine instructions (by group)
- Storage to Storage move : MVC, MVZ, MVN, MVI, MVO, ZAP, MVCL, PACK, UNPK, MVCIN
- Register to Storage move : ST, STH, STM, STC, STCM, CVD
- Storage to Register move : L, LH, LM, IC, ICM, CVB
- Register to Register move : LR, LPR, LNR, LCR, LTR
- Arithmetic with Storage fields in the packed format : AP, SP, MP, DP, SRP
- Arithmetic with Registers (fixed point binary) : AR, SR, MR, DR, ALR, SLR
- Arithmetic with Register and Storage (fixed point binary) : A, S, M, D, AH, SH, MH, AL, SL
- Compare : CP, CLC, CLI, CLCL, C, CH, CL, CLM, CR, CLR
- Branch : BC, BCR
- Loop Control : BCT, BCTR, BXH, BXLE
- Edition : ED, EDMK
- Byte Translation and test: TR, TRT
- Register Shift : SLL, SRL, SLDL, SRDL, SLA, SRA, SLDA, SRDA
- Boolean Algebra : N, O, X, NR, OR, XR, NI, OI, XI, NC, OC, XC
- Load and branch : BALR, BAL, BAS, BASR, BASSM, BSM
- Misc : LA, TM, EX, SVC, MC, SPM, IPM, STCK, TS, CS, CDS
Summary
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Machine Instructions
Hints: what instruction do I have to use to move data from a
place to another?
Origin
Destination
Instruction
Storage
Storage
MVC
Register
Register
LR
Storage (zoned)
Storage (packed)
PACK
Storage (packed)
Storage (zoned)
UNPK (maybe, additionally, MVZ / OI)
Register
Storage
ST
Storage (binary)
Register
L
Storage (packed)
Register (binary)
CVB
Register (binary)
Storage (packed)
CVD
(address)
Register
LA [ or L
(address)
Storage (contents=address)
LA + ST [ or L
Summary
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reg,=A(address) ]
+ ST ]
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Machine Instructions - A
A (ADD)
Machine Instruction
Code
5A (RX Instruction)
Condition code
00
01
10
11
Possible
Interruptions
0005,0008
Result = 0
Result < 0
Result > 0
Overflow
Instruction A adds algebraically the binary number in the 1st operand and the bynary number in a storage field
(2nd operand – a full-word). Result is loaded into 1st operand register. Examples:
Suppose the operands with the length and values shown in the “before” line
A
5,=F'259'
A
7,FULL
A
7,4(2,8)
A
7,4(2)
A
7,4(,8)
Summary
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register 1st operand before
register 1st operand after
00.00.BF.D2
00.00.C0.D5
00.00.00.0D
00.00.01.10
07.FF.FF.FE
07.FF.FF.FF
07.FF.FF.FF
07.FF.FF.FE
00.00.00.00
FF.FF.FF.FF
Mach.Inst.Summary
2nd operand before
2nd operand after
00.00.01.03
00.00.01.03
00.00.01.03
00.00.01.03
00.00.00.01
00.00.00.01
FF.FF.FF.FF
FF.FF.FF.FF
FF.FF.FF.FF
FF.FF.FF.FF
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Machine Instructions - AH
AH (Add Halfword)
Machine Instruction
Code
4A (RX Instruction)
Condition code
00
Result = 0
01
Result < 0
10
Result > 0
11
Overflow
0005,0008
Possible
Interruptions
This instruction adds algebraically two binary numbers. One of them is in the register specified as 1st
operand, and the other is a storage half-word specified as 2nd operand.
Before the operation is executed, the half-word is internally expanded to 32 bits by repeating (to the
left) the leftmost bit (sign bit). Result is loaded into 1st operand register. Examples:
Suppose the operands with the length and values shown in the “before” line
AH
5,=H'259'
AH
5,HALF
AH
5,4(2,8)
AH
5,4(2)
Summary
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register 1st operand before
register 1st operand after
00.00.2B.C4
00.00.2C.C7
00.00.00.0D
00.00.01.1A
11.11.11.11 (decimal 286331153)
11.10.99.99 (decimal 286300569)
11.11.11.11 (decimal 286331153)
11.11.89.99 (decimal 286362009)
Mach.Inst.Summary
2nd operand before
2nd operand after
01.03
01.03
01.0D
01.0D
88.88 (decimal –30584)
88.88
78.88 (decimal +30856)
78.88
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Machine Instructions - AL
AL (Add Logical)
Machine Instruction
Code
5E (RX Instruction)
Condition code
00
01
10
11
Possible
Interruptions
0005
Result
Result
Result
Result
= 0, sign not lost
<> 0, sign not lost
= 0, sign lost
<> 0, sign lost
This instruction adds logically two binary numbers. One of them is in the register specified as 1st
operand, and the other is a storage full-word specified as 2nd operand. Both numbers are considered
as positive 32-bit numbers. Result is loaded into 1st operand register. Examples:
Suppose the operands with the length and values shown in the “before” line
AL
5,=F'259'
AL
5,FULL
AL
5,4(2,8)
AL
5,4(2)
AL
5,4(,8)
Summary
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register 1st operand before
register 1st operand after
00.00.00.00
00.00.01.03
00.B0.C4.E2
00.B0.C4.E3
7F.FF.FF.FF
80.00.00.00
FF.FF.FF.FF
00.00.00.00
80.00.00.00
80.00.00.01
Mach.Inst.Summary
2nd operand before
2nd operand after
00.00.01.03
00.00.01.03
00.00.00.01
00.00.00.01
00.00.00.01
00.00.00.01
00.00.00.01
00.00.00.01
00.00.00.01
00.00.00.01
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Machine Instructions - ALR
ALR (Add Logical Register)
Machine Instruction
Code
1E (RR Instruction)
Condition code
00
01
10
11
Possible
Interruptions
No interruptions occur
Result
Result
Result
Result
= 0, sign not lost
<> 0, sign not lost
= 0, sign lost
<> 0, sign lost
This instruction adds logically the contents of two binary numbers, both located in registers.
Both numbers are considered as positive 32-bit numbers.
Result is loaded into 1st operand register. Examples:
Suppose the operands with the length and values shown in the “before” line
ALR
7,12
ALR
8,8
ALR
10,10
ALR
10,10
Summary
register 1st operand before
register 1st operand after
00.B0.C4.E2
00.B0.C4.E3
7F.FF.FF.FF
80.00.00.00
FF.FF.FF.FF
00.00.00.00
80.00.00.00
00.00.00.00
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Mach.Inst.Summary
2nd operand before
2nd operand after
00.00.00.01
00.00.00.01
00.00.00.01
00.00.00.01
00.00.00.01
00.00.00.01
80.00.00.00
80.00.00.00
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Machine Instructions - AP
AP (Add Packed)
Machine Instruction
Code
FA (SS Instruction – L1 e L2)
Condition code
00
01
10
11
Possible
Interruptions
0001,0004,0005,0007,000A
Result = 0
Result < 0
Result > 0
Overflow
This instruction adds the contents of two packed numbers, both located in storage fields.
Both numbers must be in the decimal packed format.
Result is stored into 1st operand field.
Examples:
FLDB
FLDA
FLDA
AP
before
12.3C
12.34.5C
AP
before
45.2C
FLDA,FLDB
after
12.3C
12.46.8C
FLDA,FLDA
after
90.4C
See more examples following:
Summary
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Mach.Inst.Summary
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Machine Instructions - AP
AP (Add Packed)
Machine Instruction
Code
Condition code
Possible
Interruptions
FA (SS Instruction – L1 e L2)
00
Result = 0
01
Result < 0
10
Result > 0
11
Overflow
0001,0004,0005,0007,000A
Suppose the operands with the length and values shown in the “before” line
1st operand before
1st operand after
AP HOWMANY,=P'1'
00.00.5F
00.00.6C
AP ARL+2(5),ARL+7(2)
01.23.40.00.0C
01.23.40.98.7C
AP TOTAL,2(3,7)
55.66.77.78.8C
55.66.66.67.7C
AP 4(3,8),WALFA
01.99.9F
02.01.9C
AP 7(07,8),14(2,3)
00.00.00.00.01.23.4C
00.00.00.00.01.23.9C
AP GRANDTOT,SMALLTOT
00.00.00.0C
00.00.10.1C
Summary
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Mach.Inst.Summary
2nd operand before
2nd operand after
1C
1C
98.7C
98.7C
11.11.1D
11.11.1D
02.0C
02.0C
00.5C
00.5C
00.10.1C
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Machine Instructions - AR
AR (Add Register)
Machine Instruction
Code
1A (RR Instruction)
Condition code
00
01
10
11
Possible
Interruptions
0008
Result = 0
Result < 0
Result > 0
Overflow
This instruction adds the contents of two binary numbers, both located in registers.
The value of the register 2nd operand is added to the value of the register 1st operand.
Result is stored into register 1st operand. Examples:
Suppose the operands with the length and values shown in the “before” line
AR
7,8
AR
2,2
Summary
register 1st operand before
register 1st operand after
00.00.FF.FF
00.01.00.00
00.00.FF.FF
00.01.FF.FE
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Mach.Inst.Summary
2nd operand before
2nd operand after
00.00.00.01
00.00.00.01
00.00.FF.FF
00.01.FF.FE
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Machine Instructions – BAL
BAL (Branch And Link)
Machine Instruction
Code
Condition code
45 (RX Instruction)
Possible
Interruptions
No interruptions occur
Remains unchanged
BAL instruction is similar to the BALR instruction; the difference is that the address where the branch
is to be made to (specified by the 2nd operand) is the instruction address in the base+displacement
format (rather than the address in the register as in the BALR instruction).
Note that to load the next instruction address (generally used as the return address when branching to
execute a routine) BAL loads the last 4 bytes of PSW into 1st operand register. Examples:
BAL
BAL
BAL
BAL
BAL
9,ROUTINE
14,WRTHDR
7,2(5)
7.2(,8)
7,2(5,8)
Summary
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...
...
BAL
EQU
RETINS
...
...
ROUTINE ST
....
....
L
BR
Mach.Inst.Summary
9,ROUTINE
* continuation
9,SAVEREG9
BAL loads the address of
instruction labeled
RETINS into register 9
Save register 9 (return
address) into
SAVEREG9
Restore return address
9,SAVEREG9
9
Goback (to RETINS)
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252
Machine Instructions - BALR
BALR (Branch And Link Register)
Machine Instruction
Code
Condition code
05 (RR Instruction)
Possible
Interruptions
No interruptions occur
Remains unchanged
BALR instruction is similar to the BAL instruction; the difference is that the address where branch is
to be made to (specified by the 2nd operand) is the value of the register 2nd operand (rather than the
address in the base+displacement format as in the BAL instruction).
Important: if the second operand is register zero, branch won’t be executed.
Note that to load the next instruction address (generally the return address) BALR loads the last 4
bytes of PSW. Examples:
BALR
BALR
...
3,0
14,15
LA
15,ROUTINE
BALR 14,15
EQU * continuation
LA loads the address of
instruction labeled
ROUTINE into register 15
Summary
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RETINS
...
...
ROUTINE ST
....
....
L
BR
Mach.Inst.Summary
14,SAVEREG
BALR loads the address of
instruction labeled
RETINS into register 14
Save register 14 (return
address) into SAVEREG
Restore return address
14,SAVEREG
14
Goback (to RETINS)
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253
Machine Instructions - BAS
BAS (Branch And Save)
Machine Instruction
Code
Condition code
4D (RX Instruction)
Possible
Interruptions
No interruptions occur
Remains unchanged
The address of the next instruction (following BAS) is loaded in the register 1st operand:
- Bytes 5, 6 and 7 (last 3 bytes of PSW) are loaded into bytes 1, 2 and 3 of the register
- Leftmost byte of register 1st operand is set to zero (this is the difference between BAS and BAL)
After loading the address, there’s a branch (jump) to the instruction specified in the 2nd operand.
Example:
BAS
14,ROUTINE
...
...
BAS
EQU
RETINS
...
...
ROUTINE ST
....
....
L
BR
Summary
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9,ROUTINE
* continuation
9,SAVEREG
BAS loads the address of instruction labeled RETINS
into register 9 bytes 1,2,3 and sets byte 0 with zero
Save register 9 (return
address) into SAVEREG
Restore return address
9,SAVEREG
9
Mach.Inst.Summary
Goback (to RETINS)
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254
Machine Instructions - BASR
BASR (Branch And Save Register)
Machine Instruction
Code
Condition code
0D (RR Instruction)
Possible
Interruptions
No interruptions occur
Remains unchanged
The address of the next instruction (following BASR) is loaded in the register 1st operand:
- Bytes 5, 6 and 7 (last 3 bytes of PSW) are loaded into bytes 1, 2 and 3 of the register
- Leftmost byte of register 1st operand is set to zero (this is the difference between BASR and BALR)
After loading the address, there’s a branch (jump) to the instruction specified in the 2nd operand.
Example:
BASR
14,15
LA loads the address of
instruction labeled
ROUTINE into register 15
Restore return address
Goback (to RETINS)
Summary
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...
LA
15,ROUTINE
BASR 14,15
EQU * continuation
RETINS
...
...
ROUTINE ST
....
....
L
BR
Mach.Inst.Summary
BASR sets register 14 byte 0 with
zero and loads the address of
instruction labeled RETINS into
bytes 1,2,3 of register 14
14,SAVEREG
14,SAVEREG
14
Save register 14 (return
address) into SAVEREG
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255
Machine Instructions - BASSM
BASSM (Branch And Save and Set Mode)
Machine Instruction
Code
Condition code
0C (RR Instruction)
Possible
Interruptions
No interruptions occur
Remains unchanged
The address of the next instruction (following BASSM) is loaded in the register 1st operand:
- Bytes 4, 5, 6 and 7 (last 4 bytes of PSW) are loaded into bytes 0, 1, 2, 3 of the register 1st operand
- The value of register 2nd operand is loaded into bytes 4-7 of PSW; it includes leftmost bit
(addressing mode) and (next) instruction address.
Due to this, the addressing mode is (re)set and a branch is provided. BASSM :
Example:
BASSM
14,15
- Sets register 14 with the address
LA loads the address of
instruction labeled
ROUTINE into register 15
ICM sets addressability
mode into register 15 bits
Restore return address
Goback (to RETINS)
Summary
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LA
ICM
BASSM
EQU
RETINS
...
...
ROUTINE ST
....
....
L
BR
Mach.Inst.Summary
15,ROUTINE
15,8,AMODE
14,15
* continuation
of instruction labeled RETINS into
register 14 (taken from PSW)
- Loads contents of register 15 into
PSW bytes 4-7
(Addressing mode is set [from reg.
15 into PSW] ) and
(Branch to ROUTINE is executed)
14,SAVEREG
14,SAVEREG
14
Save register 14 (return
address) into SAVEREG
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256
Machine Instructions - BC
BC (Branch on Condition)
There are 2 branch instructions: BC (RX Instruction) and BCR (RR Instruction).
But they have many auxiliary mnemonic codes, named extended mnemonic codes.
The branch instruction execution is based upon the status of Condition Code (remember?
Those 2 bits of PSW) and the mask provided in the instruction (in the left half of its 2nd byte).
The 4 different status Condition Code can be are: 00, 01, 10 and 11.
For each one of them there is a corresponding code:
STATUS
CODE
00
8
01
4
10
2
11
1
The MASK occupies half byte and indicates the condition in which branch MUST be done.
It can vary from X'0' to X'F' (decimal 0 up to 15).
MASK 8, CC B'00‘ = Branch executed
MASK 4, CC B'01‘ = Branch executed
MASK 2, CC B'10“ = Branch executed
MASK 1, CC B’11’ = Branch executed
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257
Machine Instructions - BC
BC (Branch on Condition)
One can do a combination of the masks, by adding their value.
For instance, if mask is X'C', it means that branch must occur if Condition Code is in the 8 or 4 status
(8 + 4 = 12).
If mask is zero, no branch will be done (NOP/NOPR = no operation).
If mask is 15 (X'F') branch will be done no matter waht is the Condition Code setting, because 15 =
all codes added (8+4+2+1); it is an unconditional branch.
Branch instructions with masks from 1 to 14 are conditional branches: the branch will only be done if
Condition Code is apropriately set.
See in the following slide the list of mnemonic codes, the valid masks and the extended mnemonic
codes.
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258
Machine Instructions - BC
BC (Branch on Condition)
-------------------------------------------------------------------------USE
MNEMONIC
MEANING
BC/BCR EQUIVALENCE
-------------------------------------------------------------------------General
B or BR
Allways branches
BC 15 or BCR 15
NOP or NOPR
Never branches
BC 0
or BCR 0
-------------------------------------------------------------------------After
BH or BHR
Branch if A > B
BC 2
or BCR 2
Compare
BL or BLR
Branch if A < B
BC 4
or BCR 4
BE or BER
Branch if A = B
BC 8
or BCR 8
BNH or BNHR
Branch if A < or = B
BC 13 or BCR 13
BNL or BNLR
Branch if A > or = B
BC 11 or BCR 11
BNE or BNER
Branch if A not = B
BC 7
or BCR 7
-------------------------------------------------------------------------After
BO or BOR
Branch if overflow
BC 1
or BCR 1
Arithmetic
BP or BPR
Branch if R > 0
BC 2
or BCR 2
Instructions BM or BMR
Branch if R < 0
BC 4
or BCR 4
BZ or BZR
Branch if R = 0
BC 8
or BCR 8
BNP or BNPR
Branch if R < or = 0
BC 13 or BCR 13
BNM or BNMR
Branch if R > or = 0
BC 11 or BCR 11
BNZ or BNZR
Branch if R not = 0
BC 7
or BCR 7
-------------------------------------------------------------------------After TM
BO or BOR
Branch if all bits 1
BC 1
or BCR 1
BM or BMR
Branch if mixed
BC 4
or BCR 4
BZ or BZR
Branch if all bits 0
BC 8
or BCR 8
BNO or BNOR
Branch if some are 1
BC 14 or BCR 14
-------------------------------------------------------------------------Notes: A = 1st operand ; B = 2nd operand ; R = 1st operand after compute
Summary
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259
Machine Instructions - BC
BC (Branch on Condition)
The extended menmonic codes are:
B
NOP
BH
BL
BE
BNH
BNL
BNE
BO
BP
BM
BZ
BNP
BNM
BNZ
BO
BM
BZ
BNO
Summary
Prev.Page
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
=
Branch
No Operation
Branch High
Branch Low
Branch Equal
Branch Not High
Branch Not Low
Branch Not Equal
Branch If Overflow
Branch If Plus
Branch If Minus
Branch If Zero
Branch If Not Plus
Branch If Not Minus
Branch If Not Zero
Branch If Ones
Branch If Mixed
Branch If Zeros
Branch If Not Ones
Mach.Inst.Summary
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Machine Instructions - BC
BC (Branch on Condition)
BC (Branch on Condition)
Machine Instruction
Code
Condition code
47 (RX Instruction)
Possible
Interruptions
No interruptions occur
Remains unchanged
This instruction branches (or not) to another instruction. The format is:
1st byte = operation code = 47
2nd byte – 1st half = mask
2nd byte – 2nd half = index register for 2nd operand (branch instruction address)
3rd and 4th byte = 2 bytes with base+displacement of 2nd operand (branch instruction address)
1st operand is the mask; it indicates the condition branch must be
done (or not).
2nd operand address is the address to branch to.
If condition indicated by the mask is not satisfied, branch is not
done, the execution resumes on the next intruction (instruction
following BC).
If condition indicated by the mask is satisfied, branch is done,
the execution resumes on the intruction addressed by the 2nd
operand.
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261
Machine Instructions - BC
BC (Branch on Condition)
BC (Branch on Condition)
Machine Instruction
Code
Condition code
47 (RX Instruction)
Possible
Interruptions
No interruptions occur
Remains unchanged
If one uses the mnemonic code, only one “operand” must be
specified: the address to branch to; in this case the mask is
implicit in the mnemonic. Example:
BC
8,AGAIN
is the same as
BE
AGAIN
BE is the same as BC 8.
In this case, the branch will be done when condition code is 00. Other examples:
B
READ
same as
BC 15,READ
BH
AGAIN
same as
BC 2,AGAIN
BL
COMPARE
same as
BC 4,COMPARE
BE
0(2)
same as
BC 8,0(2)
BE
0(,4)
same as
BC 8,0(,4)
BE
0(2,4)
same as
BC 8,0(2,4)
NOP
TOGGLE1
same as
BC 0,TOGGLE1
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262
Machine Instructions - BC
BC (Branch on Condition)
BC (Branch on Condition)
Machine Instruction
Code
Condition code
47 (RX Instruction)
Possible
Interruptions
No interruptions occur
Remains unchanged
Other examples:
B
BNH
BNL
BNE
BZ
BNZ
BM
Summary
READ
LOOP1
LOOP2
0(2)
0(,4)
0(2,4)
BTAB(15)
Prev.Page
Mach.Inst.Summary
same
same
same
same
same
same
same
as
as
as
as
as
as
as
BC
BC
BC
BC
BC
BC
BC
15,READ
13,AGAIN
11,COMPARE
7,0(2)
8,0(,4)
7,0(2,4)
4,BTAB(15)
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Machine Instructions - BCR
BCR (Branch on Condition Register)
BCR
(Branch on Condition Register)
Machine Instruction Code
07 (RX Instruction)
Condition code
Remains unchanged
Possible Interruptions
No interruptions occur
BCR instruction is similar to BC instruction. SEE BC INSTRUCTION.
The format is:
1st byte = operation code = x’07’
2nd byte – 1st half = mask (1st operand)
2nd byte – 2nd half = register 2nd operand containing the branch instruction address
1st operand is the mask; it indicates the condition branch must be
done (or not).
2nd operand register must contain the address to branch to.
If condition indicated by the mask is not satisfied, branch is not
done, the execution resumes on the next intruction (instruction
following BCR).
If condition indicated by the mask is satisfied, branch is done, the
execution resumes on the intruction addressed by the 2nd operand.
If one uses the mnemonic code, only the register 2nd operand must be
specified.
See examples following:
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Machine Instructions - BCR
BCR (Branch on Condition Register)
BCR
(Branch on Condition Register)
Machine Instruction Code
07 (RX Instruction)
Condition code
Remains unchanged
Possible Interruptions
No interruptions occur
BCR
8,15
is the same as
BER
15
BER is the same as BCR 8.
In this case, the branch will be done when condition code is 00. Other examples:
BCR
BR
BNER
BLR
Summary
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2,10
7
10
15
Mach.Inst.Summary
same
same
same
same
as
as
as
as
BHR
BCR
BCR
BCR
10
15,R7
7,R10
4,R15
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Machine Instructions - BCT
BCT (Branch on CounT)
Machine Instruction
Code
Condition code
46 (RX Instruction)
Possible
Interruptions
No interruptions occur
Remains unchanged
This instruction has 2 operands: the first one is a register, and the second is an instruction address.
BCT subtracts 1 from the register 1st operand and after it compares the resulting number with zero.
 If result not equal to zero, it will provide a branch to the instruction referred in the 2nd operand
 If result is zero the branch won’t be done, processing will resume at the next instruction after BCT.
Examples:
BCT
BCT
BCT
BCT
5,AGAIN
2,0(4,7)
2,0(4)
2,0(,7)
...
AGAIN
Prev.Page
11,=F’200’
0(3,5),CODE
FOUND
BCT
EQU
11,AGAIN
*
EQU
*
...
...
NOTFND
....
....
FOUND
...
Summary
L
CLC
BE
Mach.Inst.Summary
L loads into register 11
number of times loop
must be repeated
At the end of the set of loop
instructions, BCT subtracts 1
from register 11. If zero not
reached, branchs to AGAIN.
If zero, resumes execution at
NOTFND
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Machine Instructions - BCTR
BCTR (Branch on CounT Register)
Machine Instruction
Code
Condition code
06 (RX Instruction)
Possible
Interruptions
No interruptions occur
Remains unchanged
BCTR instruction has 2 operands, both in registers.
BCTR subtracts 1 from the register 1st operand and after it compares the resulting number with zero.
 If result not = zero, a branch is provided to the instruction whose address is in the register 2nd operand
 If result is zero the branch won’t be done, processing will resume at the next instruction after BCTR.
IMPORTANT: If 2nd operand is register zero, branch won’t be done; this is often used just to
subtract 1 from a register, rather than, for instance, the S or SH instructions. Examples:
BCTR
BCTR
2,7
4,0
LA loads into register 15
the address of AGAIN
instruction
Summary
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AGAIN
LA
L
CLC
BE
15,AGAIN
11,=F’200’
0(3,5),CODE
FOUND
...
...
NOTFND
....
....
FOUND
...
Mach.Inst.Summary
BCTR 11,15
EQU *
EQU
*
L loads into register 11
number of times loop
must be repeated
At the end of the set of loop
instructions, BCTR subtracts
1 from register 11. If zero not
reached, branchs to AGAIN.
If zero, resumes execution at
NOTFND
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Machine Instructions - BSM
BSM (Branch and Set Mode)
Machine Instruction
Code
Condition code
0B (RR Instruction)
Possible
Interruptions
No interruptions occur
Remains unchanged
The PSW’s addressing mode (bit 32) is loaded into bit 0 of the register 1st operand; bits 1-31
remain unchanged , and after that
(b) PSW’s Bytes 4-7 is loaded with contents of register 2nd operand (including addressing mode
bit and next instruction address)
Thus a addressing mode setting is done followed by a branch.
If 2nd operand is register zero, branch is not executed.
Example:
(a)
BSM
14,15
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Machine Instructions - BXH
BXH (Branch on indeX High)
Machine Instruction
Code
Condition code
86 (RX Instruction)
Possible
Interruptions
No interruptions occur
Remains unchanged
1st and 2nd operands are registers.
3rd operand is an instruction address.
(a) The contents of register 2nd operand is added to the contents of register 1st operand,
the result set into register 1st operand.
(b) Result is compared with:
 Contents of register 2nd operand (if it is an odd register) or
 Contents of register following register 2nd operand (if it is an even register)
If the compare result is
 Greater than it will be executed a branch to the instruction addressed by 3rd operand
 Less than or equal to the branch will not be executed; processing resumes at the
instruction following BXH
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Machine Instructions - BXH
BXH (Branch on indeX High)
Machine Instruction
Code
Condition code
86 (RX Instruction)
Possible
Interruptions
No interruptions occur
Remains unchanged
Examples:
BXH
7,8,AGAIN
R7 = R8 + R7; If R7 > R9 Branch to AGAIN;
If R7 <= R9 next instruction
BXH
7,9,AGAIN
R7 = R9 + R7; If R7 > R9 Branch to AGAIN;
If R7 <= R9 next instruction
BXH
7,9,8(4)
R7 = R9 + R7; If R7 > R9 Branch to instruction
whose address is [ (contents R4) + x’008’ ]
If R7 <= R9 next instruction
*
*
*
*
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270
Machine Instructions - BXH
BXH (Branch on indeX High)
Machine Instruction
Code
Condition code
86 (RX Instruction)
Possible
Interruptions
No interruptions occur
Remains unchanged
Example: Use in a search loop:
R7 = begins with table address;
incremented by element table length via R8
R8 = Table element length
R9 = Last element address
NOTFOUND : all table read, desired item not found.
*
*
L R7,=A(TABADRS)
L R8,=A(20)
L R9,=A(TABADRS+(HOWMANY-1)*LENGTH)
NEXTITEM pointed item vs desired one
if found, process it and
go to TABLSEEN
if not, point to next item
BXH R7,R8,NOTFOUND
B NEXTITEM
TABLSEEN ...
BXH
7,8,NOTFOUND R7 = R8 + R7;
If R7 > R9 all table already read; end search
If R7 <= R9 table not exhausted; continue search
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271
Machine Instructions - BXLE
BXLE (Branch on indeX Less or Equal)
Machine Instruction
Code
Condition code
87 (RS Instruction)
Possible
Interruptions
No interruptions occur
Remains unchanged
BXLE is similar to BXH instruction; the difference is that the branch is done if the result
of the compare is Less or Equal.
1st and 2nd operands are registers.
3rd operand is an instruction address.
(a) The contents of register 2nd operand is added to the contents of register 1st operand,
the result set into register 1st operand.
(b) Result is compared with:
 Contents of register 2nd operand (if it is an odd register) or
 Contents of register following register 2nd operand (if it is an even register)
If the compare result is
 Less or Equal to : it will be executed a branch to the instruction addressed by 3rd
operand
 Greater than : the branch will not be executed; processing resumes at the instruction
following BXLE
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Machine Instructions - BXLE
BXLE (Branch on indeX Less or Equal)
Machine Instruction
Code
Condition code
87 (RS Instruction)
Possible
Interruptions
No interruptions occur
Remains unchanged
Examples:
BXLE
7,8,AGAIN
R7 = R8 + R7; If R7 <= R9 Branch to AGAIN;
If R7 > R9 next instruction
BXLE
7,9,AGAIN
R7 = R9 + R7; If R7 <= R9 Branch to AGAIN;
If R7 > R9 next instruction
BXLE
7,9,8(4)
R7 = R9 + R7; If R7 <= R9 Branch to instruction
Whose address is [ (contents R4) + x’008’ ]
If R7 > R9 next instruction
*
*
*
*
Summary
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273
Machine Instructions - BXLE
BXLE (Branch on indeX Less or Equal)
Machine Instruction
Code
Condition code
87 (RS Instruction)
Possible
Interruptions
No interruptions occur
Remains unchanged
Example: Use in a search loop:
R7 = begins with table address;
incremented by element table length via R8
R8 = Table element length
R9 = Last element address
NOTFOUND : all table read, desired item not found
*
*
L R7,=A(TABADRS)
L R8,=A(20)
L R9,=A(TABADRS+(HOWMANY-1)*LENGTH)
NEXTITEM compare pointed item vs desired one
if found, process it and
go to TABLSEEN
if not, point to next item
BXLE R7,R8,NEXTITEM
NOTFOUND ...
TABLSEEN ...
BXLE
7,8,NOTFOUND R7 = R8 + R7;
If R7 <= R9 table not exhausted; continue search
If R7 > R9 all table already read; end search
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Machine Instructions - C
C (Compare)
Machine Instruction
Code
59 (RX Instruction)
Condition code
00
01
10
11
Possible
Interruptions
0005
1st operand = 2nd
1st operand < 2nd
1st operand > 2nd
Condition code is
operand
operand
operand
not set as 11 after C
C performs an algebraic compare between a binary number in a register (1st operand) and a binary
number in a storage field (a full-word, the 2nd operand).
Example:
C
C
C
C
C
C
Summary
9,CPO
8,=F'0'
13,=A(TABLE+430)
1,2(4)
1,2(,4)
1,2(7,4)
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Machine Instructions - CDS
CDS (Compare Double and Swap)
Machine Instruction
Code
Condition code
Possible
Interruptions
BB (RS Instruction)
00 1st operand equal to 2nd operand, 3rd operand
moved to 2nd operand
01 1st operand not equal to 2nd operand, 2nd
operand moved to 1st operand 10 Condition code is
not set as 11 after CDS
11 Condition code is not set as 11 after CDS
0004,0005,0006
1st and 3rd operands are even registers. They are considered an indication of:
1st operand: double-word composed by R1 and R1+1
3rd operand: double-word composed by R3 and R3+1
2nd operand is an storage field (double-word).
Contents of 1st operand (R1 and R1+1) is compared with the contents of the double-word
2nd operand.
If they are equal, the contents of the 3rd operand (R3 and R3+1) is stored into the 2nd
operand double-word.
If they are not equal, the contents of the double-word 2nd operand is loaded into the 1st
operand (R1 and R1+1).
See the following examples:
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Machine Instructions - CDS
CDS (Compare Double and Swap)
Machine Instruction
Code
Condition code
Possible
Interruptions
CDS
BB (RS Instruction)
00 1st operand equal to 2nd operand, 3rd operand
moved to 2nd operand
01 1st operand not equal to 2nd operand, 2nd
operand moved to 1st operand 10 Condition code is
not set as 11 after CDS
11 Condition code is not set as 11 after CDS
0004,0005,0006
CDS
4,8,DW
4,8,DW
Before: R4/R5
R8/R9
DW
00.BF.C4.20.50.CC.A0.00
7D.48.C0.00.00.00.00.02
00.BF.C4.20.50.CC.A0.00
Before: R4/R5
R8/R9
DW
00.CC.DD.EE.FF.FF.FF.FF
7D.48.C0.00.00.00.00.02
00.BF.C4.20.50.CC.A0.00
After:
00.BF.C4.20.50.CC.A0.00
7D.48.C0.00.00.00.00.02
7D.48.C0.00.00.00.00.02
After:
00.BF.C4.20.50.CC.A0.00
7D.48.C0.00.00.00.00.02
00.BF.C4.20.50.CC.A0.00
R4/R5
R8/R9
DW
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Mach.Inst.Summary
R4/R5
R8/R9
DW
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Machine Instructions - CH
CH (Compare Halfword)
Machine Instruction
Code
49 (RX Instruction)
Condition code
00
01
10
11
Possible
Interruptions
1st operand = 2nd
1st operand < 2nd
1st operand > 2nd
Condition code is
operand
operand
operand
not set as 11 after
CH
0005
CH performs an algebraic compare between a binary number in a register (1st operand) and a binary
number in a storage field (a half-word, the 2nd operand). To do that, the 2nd operand is expanded
(internally in the CPU) to 4 bytes, by repeating (to the left) 16 times the leftmost bit of the half-word.
Example:
CH
9,FLD
1st operand = R9; 2nd operand = FLD field
CH
8,=H'0'
1st operand = R8; 2nd operand = half-word with zeros
CH
13,=Y(TAB+430)
1st operand = R13; 2nd operand = half-word with address of TAB+430
CH
1,2(4)
1st operand = R1; 2nd operand = storage half-word which
*
address = value of index register R4 +0[base register omitted] + x’2’
CH
1,2(,4)
1st operand = R1; 2nd operand = storage half-word which
*
address = value of base register R4 +0[index register omitted] + x’2’
CH
1,2(7,4)
1st operand = R1; 2nd operand = storage half-word which
*
address = value of base register R4 +R7[index register] + x’2’
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278
Machine Instructions - CL
CL (Compare Logical)
Machine Instruction
Code
55 (RX Instruction)
Condition code
00
01
10
11
0005
Possible
Interruptions
1st operand = 2nd
1st operand < 2nd
1st operand > 2nd
Condition code is
operand
operand
operand
not set as 11 after CL
The CL instruction compares logically the contents of register 1st operand and the contents of a storage
full-word (2nd operand).
Logical compare is done left to right, one bit at a time; the first couple of unequal bits finish the operation..
Examples:
CL
9,CPO
32 bits of register 9 compared with 32 bits of 4-byte CPO
CL
8,=F'0'
32 bits of register 8 compared with 32-bit of 4-byte full-word with zero
CL
1,2(4)
32 bits of register 1 compared with 4-byte storage field
* ( 2nd operand address = contents of index reg. 4 + displacement X’2’ [base reg. omitted = zero = not considered] )
CL
1,2(,4)
32 bits of register 1 compared with 4-byte storage field
* ( 2nd operand address = [ index reg. Omitted = zero = not considered] + displacement X’2’ + base reg.4 )
CL
1,2(7,4)
32 bits of register 1 compared with 4-byte field
* ( 2nd operand address = contents of index reg. 7 + displacement X’2’ + contents of base reg. 4 )
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Machine Instructions - CLC
CLC (Compare Logical Character)
Machine Instruction
Code
D5 (SS Instruction – L)
Condition code
00
01
10
11
Possible
Interruptions
0005
1st operand = 2nd
1st operand < 2nd
1st operand > 2nd
Condition code is
operand
operand
operand
not set as 11 after CLC
This instruction compares logically (left to right, one bit at a time) two storage fields. The first not equal
couple of bits finish the compare. Examples:
CLC
CPOA,CPOB
Only one length used = length of CPOA (e.g. 100 bytes)
CLC
AE+78(2),=C'*1'
2-byte (AE+78 and AE+79) storage field is compared with
*
2-byte storage field referenced via literal (contents = X’5CF1’)
CLC
4(2,7),2(9)
2 bytes field (address = base register 7 + displacement X’4’)
*
is compared with storage field ( address = base register 9 + displacement X’2’ )
CLC
ID,2(7)
n-byte storage field ID is compared with n-byte storage field
*
(address = base register 7 + displacement X’2’ )
CLC
194(5,11),AE+3
5-byte storage field (address = base register 11 + displacement X’C2’)
*
is compared with 5-byte storage field ( address = AE+3 )
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Machine Instructions- CLCL
CLCL (Compare Logical Character Long)
Machine Instruction
Code
0F (RR Instruction)
Condition code
00 1st operand =
have zero length.
01 1st operand <
10 1st operand >
11 Condition code
0005,0006
Possible
Interruptions
2nd operand or both operands
2nd operand
2nd operand
is not set as 11 after CLCL
This instruction compares two storage fields, in a similar way the CLC does.
Both 1st and 2nd operands must be even registers. They indicate (each one of them) a pair of even-odd
registers. We’ll call them: 1st pair = R1st and R1st+1; 2nd pair = R2nd and R2nd+1
The 1st operand (receiver field) address must be in the last 3 bytes (righmost) of R1st.
The 2nd operand (sender field) address must be in the last 3 bytes (righmost) of R2nd.
The 1st operand length must be in the last 3 bytes (rightmost) of R1st+1.
The 2nd operand length must be in the last 3 bytes (rightmost) of R2nd+1.
The leftmost byte of R2nd+1 must have the padding character.
The leftmost byte of R1st, the leftmost byte of R2nd and the leftmost byte of R1st+1 are not considered in the
operation. Example:
CLCL
2,8
R2=1st operand register (dubbed as R1st above); note that R1st+1 = register 3
R8=2nd operand register (dubbed as R2nd above); note that R2nd+1 = register 9
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Machine Instructions- CLCL
CLCL (Compare Logical Character Long)
Machine Instruction
Code
Condition code
Possible
Interruptions
0F (RR Instruction)
00 1st operand =
zero length.
01 1st operand <
10 1st operand >
11
Condition code
0005,0006
2nd operand or both operands are
2nd operand
2nd operand
is not set as 11 after CLCL
Compare is done one bit at a time, from left to right. When not 2 bits unequal are found OR when length
of greater operand is exhausted compare is finished.
If the operands have no equal kengths, the smaller one is extended with the padding character (internally,
without any change in the field).
If compare is finished due to 2 bits unequal encountered:
- From the value in the rightmost 3 bytes of R1st+1 and R2nd+1 is subtracted the amount of equal bytes;
if the difference was found with the padding character the rightmost 3 bytes of R1st OR R2nd+1 are
zeroed (the ones who have the smallest length).
- To the value of the rightmost 3 bytes of R1st and R2nd is added the amount of equal bytes.
If both operands are equal (including the padding character, if needed):
- The 3 rightmost bytes of R1st+1 AND R2nd+1 are zeroed.
- To the 3 rightmost bytes of R1st AND R2nd is added the amount of equal bytes.
In both cases : the leftmost byte of R1 and the leftmost byte of R2 are zeroed, and the leftmost byte of
R1st+1 and R2nd+1 remain unchanged.
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282
Machine Instructions- CLCL
CLCL (Compare Logical Character Long)
Machine Instruction
Code
Condition code
Possible
Interruptions
0F (RR Instruction)
00 1st operand =
zero length.
01 1st operand <
10 1st operand >
11
Condition code
0005,0006
2nd operand or both operands are
2nd operand
2nd operand
is not set as 11 after CLCL
Example:
LA loads into register 8
the BUFERIN address
LA loads into register 9 the
BUFERIN length
CLCL executes the compare
between a 12000-byte field
(BUFEROUT) and a 20000byte field (BUFERIN)
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AGAIN
DIFFS
...
...
...
...
EQUALS
...
Mach.Inst.Summary
LA
LA
LA
LA
ICM
CLCL
BE
EQU
2,BUFEROUT
3,12000
8,BUFERIN
9,20000
9,B'1000',C' '
8,9
EQUALS
*
EQU
*
LA loads into register 2
the BUFEROUT address
LA loads into register 3
the BUFEROUT length
ICM inserts padding
character into leftmost byte
of register 9
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Machine Instructions - CLI
CLI (Compare Logical Immediate)
Machine Instruction
Code
Condition code
Possible
Interruptions
95 (SI Instruction)
00
01
10
11
0005
1st operand = 2nd
1st operand < 2nd
1st operand > 2nd
Condition code is
operand
operand
operand
not set as 11 after CLI
This instruction compares logically (left to right, one bit at a time) two storage fields.
The first operand is a “normal” storage field with its address expressed with a base+displacement address.
The second operand is also a storage field, but it is located IN the instruction: it is the instruction’s 2nd byte.
It’s not necessary to specify its address, only its contents.
Examples (note that b1d1d1d1 is the address of the 1st operand, in the base+displacement format):
CLI
AE+79,C'*'
Machine code = 95.5C.b1d1.d1d1 Compare with asterisk
CLI
2(5),X'00'
Machine code = 95.00.50.02
CLI
BYTE,B'11110000'
Machine code = 95.F0.b1d1.d1d1 Compare with character zero
CLI
NOP+1,240
Machine code = 95.F0.b1d1.d1d1
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Compare with binary zeros
Compare with character zero
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Machine Instructions - CLM
CLM (Compare Logical under Mask)
Machine Instruction
Code
Condition code
Possible
Interruptions
BD (RS Instruction)
00
Selected bytes are equal, or mask is zero
01
Selected field of the 1st operand is less
than 2nd operand
10 Selected field of the 1st operand is greater
than 2nd operand
0005
11 Condition code is not set as 11 after CLM
The contents of register 1st operand is logically compared (left to right, one bit at a time) with the contents of
the 2nd operand, based on the control of the mask 3rd operand. The result is reflected in the setting of the
condition code.
It’s a RS instruction, with the following format:
Byte 1= x’BD’ (operation code);
Byte 2 = left half = R1 = register 1st
operand; right half = M3 =(mask)
Bytes 3 and 4 = 2nd operand address (base+displacement)
The 4-bit mask, left to right, are related to the 4 bytes of the register 1st operand. The register bytes whose
bits in the mask are ON are considered as a contiguous field, and compared with the storage field specified in
the 2nd operand (the 2nd operand must have a length equal to the number of bits ON in the mask.
The register bytes whose bits in the mask are OFF are not considered in the operation. Example:
CLM
5,B'1011',ARCOMP
The “field” composed by 1st , 3rd and 4th bytes of register 5 is compared with the 3-byte field named
ARCOMP.
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Machine Instructions - CLR
CLR (Compare Logical Register)
Machine Instruction
Code
15 (RR Instruction)
Condition code
00
01
10
11
Possible
Interruptions
No interruptions occur
1st operand = 2nd
1st operand < 2nd
1st operand > 2nd
Condition code is
operand
operand
operand
not set as 11 after CLR
The CLR instruction compares logically the contents of the 2 registers (1st operand and 2nd operand).
Logical compare is done left to right, one bit at a time; the first couple of unequal bits found finish the
operation. Examples:
CLR
4,5
32-bit “string” of register 4 compared with 32 bit “string” of register 5
CLR
8,13
32-bit “string” of register 8 compared with 32-bit “string” of rregister 13
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Machine Instructions - CP
CP (Compare Packed)
Machine Instruction
Code
F9 (SS Instruction – L1 e L2)
Condition code
00
01
10
11
Possible
Interruptions
0005,0007
1st operand = 2nd
1st operand < 2nd
1st operand > 2nd
Condition code is
operand
operand
operand
not set as 11 after CP
The CP instruction compares the contents of 2 storage fields ( 1st and 2nd operands). Both must be in the
decimal packed format, and remain unchanged. The lengths can be different: the values are compared, not the
sizes. Examples:
CP
FLDA,FLDB
If FLDA = X’00000009999C’ and FLDB = X’10000C’
*
Result is : 1st operand less than 2nd operand
CP
COUNTLIN,=P'1'
If COUNTLIN = X’999999D’ compared with X’1C’
Result is : 1st operand less than 2nd operand
CP
0(5,9),=P'0'
Compares contents of 5-byte field at address
(base register 9 + X’0’) with zero
CP
TOTAL,2(7,9)
Compares contents of TOTAL with 7-byte field
address (base register 9 + displacement X’2’)
*
*
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Machine Instructions - CR
CR (Compare Register)
Machine Instruction
Code
19 (RR Instruction)
Condition code
00
01
10
11
Possible
Interruptions
No interruptions occur
1st operand = 2nd
1st operand < 2nd
1st operand > 2nd
Condition code is
operand
operand
operand
not set as 11 after CR
The CR instruction compares 2 binary numbers within 2 registers (1st and 2nd operands). Both
remain unchanged. Examples:
CR
4,5
31-bit binary number in register 4 compared with 31-bit binary number in register 5
CR
8,13
31-bit binary number in register 8 compared with 31-bit binary number in register
13
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Machine Instructions - CS
CS (Compare and Swap)
Machine Instruction
Code
Condition code
Possible
Interruptions
BA (RS Instruction)
00 1st operand equal to 2nd operand, 3rd
moved to 2nd operand
01 1st operand not equal to 2nd operand,
operand moved to 1st operand
10 Condition code is not set as 10 after
11
Condition code is not set as 11 after
0004,0005,0006
operand
2nd
CS
CS
1st and 3rd operands are registers.
2nd operand is a storage field (full-word).
The contents of the register 1st operand is compared with the 2nd operand full-word.
If they are equal, the contents of register 3rd operand is stored in the 2nd operand full-word.
If they are unequal the contents of the 2nd operand full-word is loaded into register 1st operand.
Examples:
CS
5,8,FW
Before: R5 00.BF.C4.20
R8 7D.48.C0.00
FW 00.BF.C4.20
After: R5 00.BF.C4.20
R8 7D.48.C0.00
FW 7D.48.C0.00
CS
Before: R5
After: R5
Summary
00.BF.C4.20
00.FF.EE.DD
Prev.Page
5,8,FW
R8 7D.48.C0.00
R8 7D.48.C0.00
Mach.Inst.Summary
FW
FW
00.FF.EE.DD
00.FF.EE.DD
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Machine Instructions - CVB
CVB (ConVert to Binary)
Machine Instruction
Code
Condition code
4F (RX Instruction)
Possible
Interruptions
0005, 0007, 0009
Remains unchanged
The decimal packed number within the 8-byte field 2nd operand (normally a double-word – it remains
unchanged), is converted to binary and loaded into 1st operand register. Examples:
Suppose the operands with the length and values shown in the “before” line
CVB
8,DOUBLE
CVB
8,0(5,9)
CVB
8,0(,9)
CVB
8,0(5)
*
*
*
*
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register 1st operand before 2nd operand before
register 1st operand after 2nd operand after
12.BC.4F.CA
00.00.00.00.00.01.02.4D
FF.FF.FC.00
00.00.00.00.00.01.02.4D
2nd operand = DOUBLE
FF.FF.FF.FF
00.00.00.00.00.01.02.5C
00.00.04.01
00.00.00.00.00.01.02.5C
2nd operand address = index register 5 + base register 9 + X’0’
FF.FF.FF.FF
00.00.00.00.00.01.02.3F
00.00.03.FF
00.00.00.00.00.01.02.3F
2nd operand address = index register 0 + base register 9 + X’0’
FF.FF.FF.FF
00.00.00.00.00.01.02.3C
00.00.03.FF
00.00.00.00.00.01.02.3C
2nd operand address = index register 5 + base register 0 + X’0’
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Machine Instructions - CVD
CVD (ConVert to Decimal [packed])
Machine Instruction
Code
Condition code
4E (RX Instruction)
Possible
Interruptions
0004,0005
Remains unchanged
The binary number within the register 1st operand is converted to decimal packed format and stored
into the 8-byte field 2nd operand (normally a double-word).
For positive numbers or zero, sign is ‘C’. For negative numbers sign is ‘D’.
Examples:
Suppose the operands with the length and values shown in the “before” line
CVD
8,DOUBLE
CVD
8,0(5,9)
CVD
8,0(,9)
CVD
8,0(5)
*
*
*
*
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register 1st operand before 2nd operand before
register 1st operand after 2nd operand after
00.00.10.00
00.00.00.00.00.00.00.70
00.00.10.00
00.00.00.00.00.04.09.6C
2nd operand = DOUBLE
FF.FF.FF.FF
00.00.FB.EC.44.CC.F0.F1
FF.FF.FF.FF
00.00.00.00.00.00.00.1D
2nd operand address = index register 5 + base register 9 + X’0’
00.00.99.99
98.BA.76.FE.54.DC.32.B9
00.00.99.99
00.00.00.00.00.39.32.1C
2nd operand address = index register 0 + base register 9 + X’0’
00.00.AA.AA
00.00.00.00.00.00.00.0C
00.00.AA.AA
00.00.00.00.00.43.69.0C
2nd operand address = index register 5 + base register 0 + X’0’
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Machine Instructions - D
D (Divide)
Machine Instruction
Code
Condition code
5D (RX Instruction)
Possible
Interruptions
0005,0006,0008
Remains unchanged
This instruction executes a division between 2 binary numbers.
1st operand indicate an even register; it is the the first of a couple registers (even+odd); together they
must have a fixed-point number, whose format is: 1 sign bit + 63 binary-digit bits.
The number within this couple of registers is the dividend.
The divisor is the number within the 2nd operand storage field (full-word).
After division:
-The remainder is stored into the even register from the even-odd couple.
- The quotient is stored in the odd register from the even-odd couple.
Examples:
L
L
D
6,=F'0'
7,=F'257'
6,=F'4'
Dividend: Registers 6-7 together;
They have the number 257
Divisor: (literal) with number 4; Quotient: Register 7 = 64; Remainder: Register 6 = 1
L
L
D
10,=F'0'
11,=F'17'
10,=F'3'
Dividend: Registers 10-11 together;
They have the number 17
Divisor: (literal) with number 3; Quotient: Register 11 = 5; Remainder: Register 10 = 2
*
*
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Machine Instructions - DP
DP (Divide Packed)
Machine Instruction
Code
Condition code
FD (SS Instruction – L1 e L2)
Possible
Interruptions
0004,0005,0006,0007,000B
Remains unchanged
The DP instruction executes a division between 2 storage fields, both in packed decimal format.
1st operand is the dividend, and 2nd operand is the divisor.
After division the quotient and the remainder are stored in the 1st operand storage field.
2nd operand remains unchanged.
About the 2nd operand divisor (a) it remains unchanged after division (b) it cannot exceed 8
bytes (c) its length cannot be greater than or equal to the 1st operand length (d) if condition b or c
occurs, program will interrupt with code 0006.
The remainder is stored in the rightmost bytes of the 1st operand, with divisor’s length.
Code 000B interruption occurs when:
 Quotient’s length is greater than the length available to it in the 1st operand
 Dividend has not at least 1 leftmost zero algarism.
 Divisor is zero.
See the following examples:
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Machine Instructions - DP
DP (Divide Packed)
Machine Instruction
Code
Condition code
FD (SS Instruction – L1 e L2)
Possible
Interruptions
0004,0005,0006,0007,000B
Remains unchanged
Suppose the operands with the length and values shown in the “before” line
DP
FLDA,FLDB
DP
FLDA,FLDB
DP
VALUE,=P'5'
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1st operand before
1st operand after
00.00.45.67.8C
22.83.9C.00.0C
00.00.00.11.1C
00.05.5C.00.1C
00.00.00.00.00.12.7C
00.00.00.00.02.5C.2C
2nd operand before
2nd operand after
00.2C
00.2C
00.2C
00.2C
5C
5C
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Machine Instructions - DR
DR (Divide Register)
Machine Instruction
Code
Condition code
1D (RR Instruction)
Possible
Interruptions
0006,0009
Remains unchanged
This instruction executes a division between 2 binary numbers, both in registers.
1st operand must indicate an even register; it is the the first of a couple registers (even+odd); together they
must have a fixed-point number, whose format is: 1 sign bit + 63 binary-digit bits.
The number within this couple of registers is the dividend. 2nd operand is the divisor.
After division:
- The quotient is stored into the odd register
- The remainder is stored into the even register
- If the remainder and/or quotient are = 0, their sign will be 0; remainder’s sign is the same as dividend’s sign
Examples:
L
L
L
DR
12,=F'2'
4,=F'0'
5,=F'257'
4,12
Divisor: Register 12 with number 2
Dividend: Registers 4-5 together;
They have the number 257
Quotient: Register 5 = 128; Remainder: Register 4 = 1
L
L
L
DR
9,=F'12'
6,=F'0'
7,=F'148'
6,9
Divisor: Register 9 with number 12
Dividend: Registers 6-7 together;
They have the number 148
Quotient: Register 7 = 12; Remainder: Register 6 = 4
*
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Machine Instructions - ED
ED (Edit)
Machine Instruction
Code
Condition code
Possible
Interruptions
Syntax:
[symbol]
DE (SS Instruction – L)
00
Last field = 0
01
Last field < 0
10
Last field > 0
11
Condition code is not set as 11 after ED
0004,0005,0007
ED
receiving_field,sending_field
The 1st operand must have been prepared, prior to the edition, with the edition mask (e.g. move the
edition mask to the 1st operand of edit instruction).
The sending field (2nd operand) is converted from packed decimal to zoned decimal, and stored into
the receiving field (1st operand), ovelaying therefore the mask in the 1st operand.
Edition means the control and inclusion, if needed, of sign, visual characters (e.g. decimal point, 3digit separators), and supression of non-significant zeros.
One may edit many packed fields in just one execution of ED instruction.
The (only) length specified is applied just to the 1st operand.
The 2nd operand must be in the decimal packed format. If any byte of the 2nd operand have in his left
half the configurations A, B, C, D , E or F, it will occur a program interruption (code 0007).
Edit is done left to right.
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Machine Instructions - ED
ED (Edit)
Machine Instruction
Code
DE (SS Instruction – L)
Condition code
00
01
10
11
Possible
Interruptions
0004,0005,0007
Last field = 0
Last field < 0
Last field > 0
Condition code is not set as 11 after ED
The bytes of mask may have: X'20‘ = digit selector; X’21’ = significance trigger, X’22’ ) = field
separator , or any other contents (in this last case, it’s just a character to be inserted for visual
pirposes)
During edition, each character of the receiving field (mask – 1st operand) may have go into one of the
3 ways:
Remain unchanged
 Substituted by an algarism of the sending field (converted to zoned format)
 Substituted by the leftmost character of the 1st operand mask (FILLING character).
To make the opetion from the 3 alternatives, CPU must analyse the mask, and consider the algarism
being edited (is it zero or not?).
The process is as follows:
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Machine Instructions - ED
ED (Edit)
Machine Instruction
Code
DE (SS Instruction – L)
Condition code
00
01
10
11
Possible
Interruptions
0004,0005,0007
Last field = 0
Last field < 0
Last field > 0
Condition code is not set as 11 after ED
 The mask’s leftmost byte is analysed; if it is X’20’ or X’21’ it’s assigned as padding character and
the edition starts with it.
 Each one of the following bytes can have one of the following configurations:
Digit selector (X'20') or S-Trigger (X'21') or Field separator (X'22') or Any other
 In the edition, when is detected a X’20’ or X’21’ in the 1st operand, instruction v erifies:
- The S-Trigger : significance indicator; it is a CPU flag; it can be ON or OFF.
- The digit carresponding at the 2nd operand.
As a result of the verification, the configuration in the mask in the 1st operand will be substituted
by the corresponding digit in the 2nd operand converted to zoned (if digit in the 1st operand is
X’20’ or X’21’), or by the padding character (if not X’20’ nor X’21’).
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Machine Instructions - ED
ED (Edit)
Machine Instruction
Code
DE (SS Instruction – L)
Condition code
00
01
10
11
Possible
Interruptions
0004,0005,0007
Last field = 0
Last field < 0
Last field > 0
Condition code is not set as 11 after ED
About the S-trigger:
 It is turned OFF (a) at the beginning of the ED execution or (b) after a X’22’ is found in the mask or
(c) when a X’A’ or X’C’ or ‘E’ or ‘F’ is found in the right phalf of any byte of the 2nd operand (the
packed field being edited)
 It is turned ON (a) after a X’21’ is detected in the mask or (b) when a ‘X20’ is detected in the mask
WITH its corresponding digit in the sending field being NOT zero. For these 2 cases the right half of
the byte in the sending field doesn’t have X’A’ or X’C’ or ‘E’ or ‘F’.
About Field separator (X'22') : it identifies fields in a multi-field edition. It is always substituted by
the padding character
Examples:
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Machine Instructions - ED
ED (Edit)
Machine Instruction
Code
DE (SS Instruction – L)
Condition code
00
01
10
11
Possible
Interruptions
0004,0005,0007
Last field = 0
Last field < 0
Last field > 0
Condition code is not set as 11 after ED
Note that lowercase b means a (blank) space.
MVC
WPAREA+5(10),MASK
ED
WPAREA+5(10),TOTAL
...
MASK
DC
X'4020204B2021206B2020'
Before:
TOTAL
WPAREA+5(10)
00.12.34.5C
40.20.20.4B.20.21.20.6B.20.20
b b b b 1 2 3 , 4 5
After:
TOTAL
WPAREA+5(10)
00.12.34.5C
40.40.40.40.F1.F2.F3.6B.F4.F5
b b b b 1 2 3 , 4 5
Other examples:
ED
ED
ED
Summary
0(5,7),CPO
ARIMP+17(8),ISDRT
4(12,9),2(10)
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300
Machine Instructions - EDMK
EDMK (Edit and Mark)
Machine Instruction
Code
DF (SS Instruction – L)
Condition code
00
01
10
11
Possible
Interruptions
0004,0005,0007
Last field = 0
Last field < 0
Last field > 0
Condition code is not set as 11 after EDMK
This instruction is analog to the ED instruction.
It loads into register 1 (bits 8-31; bits 0-7 remain unchanged) the address of the byte in the 1st
operand who received the 1st non-zero digit.
Note that the address is not loaded when significance is forced (using X'21').
Example:
EDMK
ARIMP+5(10),TOTAL
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301
Machine Instructions - EX
EX (Execute)
Machine Instruction
Code
Condition code
Possible
Interruptions
44 (RX Instruction)
The setting (or not) depends on the executed
instruction
0003,0005,0006
The 2nd operand specifies an instruction address.
The instruction it refers to is temporarily (internally in theCPU) modified according to the value of the
register specified as 1st operand. With this tomporary change, it is executed.
The temporary changing is made applying a boolean OR (mask = rightmost byte of 1st operand
register; object = 2nd byte of instruction addressed by 2nd operand).
Note that both EX operands remain unchanged.
If 1st operand is register 0, OR won’t be done, the instruction will be executed as it is in storage, with
no change in the 2nd byte.
Example:
L
5,=F'22'
EX
5,MVC
.
.
MVC
MVC
0,(0,12),=CL256' '
Move will be executed with length 23
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302
Machine Instructions - IC
IC (Insert Character)
Machine Instruction
Code
Condition code
43 (RX Instruction)
Possible
Interruptions
0005
Remains unchanged
The contents of the byte specified in the 2nd operand is inserted into the rightmost byte of the register
1st operand; leftmost 3 bytes remain unchanged. Example:
Suppose the operands with the length and values shown in the “before” line
register 1st operand before
2nd operand before
register1st operand after
2nd operand after
IC 4,BYTE
00.00.45.67.8C
6B
00.00.45.67.6B
6B
IC 8,=C'K'
00.00.00.11.1C
D2
00.00.00.11.D2
D2
IC 11,=HL1'125'
00.00.00.00.00.12.7C
7D
00.00.00.00.02.5C.2C
7D
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Machine Instructions - ICM
ICM (Insert Character under Mask)
Machine Instruction
Code
Condition code
Possible
Interruptions
BF (RS Instruction)
00
All inserted bits are 0, or mask is zero.
01
1st bit of inserted field is 1.
10
1st bit of inserted field is 0, and not all
inserted bits are zero.
11
0005 Condition code is not set as 11 after ICM.
The format of this instruction is:
1st byte: X’BF’ (operation code); 2nd byte, left half : 1st operand register ; 2nd byte, right half : 3rd operand (mask);
3rd and 4th bytes : 2nd operand address, base+displacement format.
The 4 bits in the mask correspond to the 4 bytes of the 1st operand register.
The storage field specified in the 2nd operand must have as many bytes as the ON bits in the mask.
The storage bytes are inserted left to right into the bytes of 1st operand byteswhose bits in the mask are ON.
The remaining bytes of the register remain unchanged. Example:
Suppose the operands with the length and values shown in the “before” line
register 1st operand before
2nd operand before
register1st operand after
2nd operand after
ICM 5,B'1010',TWOBYTES
00.00.45.67
9A.BC
9A.00.BC.67
9A.BC
1st byte from TWOBYTES is inserted into 1st byte of register 5 and 2nd byte from TWOBYTES is inserted
into the 3rd byte of register 5.
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Machine Instructions - IPM
IPM (Insert Program Mask)
Machine Instruction
Code
Condition code
B222 (RR InstructionE)
Possible
Interruptions
No interruptions occur
Remains unchanged
Bits 16-23 (3rd byte) and 28-31 (4th byte right) of the instruction are ignored.
Condition code and program mask (from PSW) are copied into bits 2-3 (condition code) and bits 4-7
(program mask) into the corresponding bits of 1st operand register.
Bits 0-1 of the register are zeroed, and bits 8-31 remain unchanged.
Example:
Suppose PSW with condition code ’01’ and program mask ‘1100’
register 8 before
register 8 after
IPM
8
C4.56.78.9A
1C.56.78.9A
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Machine Instructions - L
L (Load)
Machine Instruction
Code
Condition code
58 (RX Instruction)
Possible
Interruptions
0005
Remains unchanged
The contents of the field specified as 2nd operand (remains unchanged
1st operand. Examples:
Suppose the operands with the length and values shown in the “before” line
register 1st operand before
register1st operand after
L 7,FULL
FE.DC.BA.98
00.01.00.00
L 14,SALVA
00.00.00.11
FF.FF.FF.FD
L 11,=F'125'
00.00.00.00
00.00.00.7D
Other examples:
L
8,0(10)
L
8,0(,11)
L
8,0(10,11)
L
5,=F'200'
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and) is loaded into the register
2nd operand before
2nd operand after
00.01.00.00
00.01.00.00
FF.FF.FF.FD
FF.FF.FF.FD
00.00.00.7D
00.00.00.7D
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Machine Instructions - LA
LA (Load Address)
Machine Instruction
Code
Condition code
41 (RX Instruction)
Possible
Interruptions
No interruptions occur
Remains unchanged
The instruction computes the 2nd operand address and loads it into the 3 rightmost bytes of register 1st
operand. The leftmost byte of register is set ro zero. Example:
Suppose the registers with the values shown bellow (for symbol references register 3 is supposed to be the base
register for the referenced fileds, and the displacements are just for example purposes; )
register 1st operand before machine instruction register 3 before register 9 before
register1st operand after
register 3 after
register 9 after
LA
5,TABLE
01.12.34.56 41.50.3A.C2 00.0B.88.40 not used
00.0B.93.02
00.0B.88.40 not used
LA
5,FLD+17
01.12.34.56 41.50.3F.03 00.A0.00.00 not used
00.A0.0F.03
00.A0.00.00 not used
LA
5,FLD+17(9) 01.12.34.56 41.59.3F.03 00.A0.00.00 00.00.00.14
00.A0.0F.17
00.A0.00.00 00.00.00.14
LA
5,2(9,3)
01.12.34.56 41.59.30.02 00.A0.00.00 00.00.00.14
00.A0.00.16
00.A0.00.00 00.00.00.14
LA
5,200
01.23.45.67 41.50.00.C8 not used
not used
00.00.00.C8
not used
not used
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Machine Instructions - LA
LA (Load Address)
Machine Instruction
Code
Condition code
41 (RX Instruction)
Possible
Interruptions
No interruptions occur
Remains unchanged
The instruction computes the 2nd operand address and loads it into the 3 rightmost bytes of register 1st
operand. The leftmost byte of register is set ro zero. Example:
Suppose the registers with the values shown bellow
register 1st operand before
register1st operand after
LA
5,4095
LA
5,4095(3)
LA
5,4095(3,9)
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01.23.45.67
00.00.0F.FF
01.23.45.67
00.0A.8F.FF
01.23.45.67
00.0A.10.00
Mach.Inst.Summary
machine instruction register 3 before
register 3 after
41.50.0F.FF
41.53.0F.FF
41.53.9F.FF
not used
not used
00.0A.80.00
00.0A.80.00
00.0A.00.00
00.0A.80.00
register 9 before
register 9 after
not used
not used
not used
not used
00.00.00.01
00.00.00.01
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Machine Instructions - LCR
LCR (Load Complement Register)
Machine Instruction
Code
13 (RR Instruction)
Condition code
00
01
10
11
Possible
Interruptions
0008
Result = 0
Result < 0
Result > 0
Overflow
The binary number in the register 2nd operand is complemented and stored into the register 1st
operand.
If the number is positive, it becomes negative; if it is negative it becomes positive.
Example:
Suppose the operands with the length and values shown in the “before” line
register 1st operand before
register 2nd operand before
register1st operand after
register 2nd operand after
LCR 4,5
00.00.00.00
FF.FF.FF.FC
00.00.00.04
FF.FF.FF.FC
LCR 4,4
00.00.00.02
00.00.00.02
FF.FF.FF.FE
00.00.00.02
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Machine Instructions - LH
LH (Load Halfword)
Machine Instruction
Code
Condition code
48 (RX Instruction)
Possible
Interruptions
0005
Remains unchanged
The 2-byte field specified as 2nd operand (remains unchanged and) is loaded into the rightmost 2
bytes of the register 1st operand. The leftmost bit of the storage field is used to fill the leftmost 2
bytes of the register 1st operand: it is expanded / copied to all bits of the first 2 bytes of the register.
Example:
Suppose the operands with the length and values shown in the “before” line
register 1st operand before
2nd operand before
register1st operand after
2nd operand after
LH 5,FLD
00.00.00.00
8A.B4
FF.FF.8A.B4
8A.B4
LH 8,HWORD
FF.FF.FF.FF
7A.B4
00.00.7A.B4
7A.B4
LH
LH
LH
LH
LH
More examples:
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7,HALF
8,0(10)
8,0(,11)
8,0(10,11)
8,=H'200'
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Machine Instructions - LM
LM (Load Multiple)
Machine Instruction
Code
Condition code
98 (RX Instruction)
Possible
Interruptions
0005
Remains unchanged
This instruction works with 3 operands: 1st and 3rd are registers, and 2nd is a storage field.
It loads the contents of the storage field 2nd perand into the registers specified as a range by the 1st and 3rd
operands.
The length of the field depends on how many registers must be loaded. To load 2 registers, the area must have
8 bytes; to load 3 registers, the area must have 12 bytes, and so on.
Example:
LM
14,1,SAVEAREA
Reg. 14
Reg.15
Reg.0
Reg.1
<----------><---------><----------><---------->
|------- SAVEAREA ----------------------------|
SAVEAREA = 16 bytes (bytes 0-3 = contents loaded into register 14; bytes 4-7 = contents loaded into register
15; bytes 8-11 = contents loaded into register 0; bytes 12-15 = contents loaded into register 1)
Another example:
LM
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1,7,2(10)
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Machine Instructions - LNR
LNR (Load Negative Register)
Machine Instruction
Code
11 (RR Instruction)
Condition code
00
01
10
11
Possible
Interruptions
No interruptions occur
Result = 0
Result < 0
Condition code is not set as 10 after LNR
Condition code is not set as 11 after LNR
The binary number of the 2nd operand is converted to negative and
Negative numbers and zero remain unchanged.
Example:
Suppose the operands with the length and values shown in the “before” line
register 1st operand before
register1st operand after
LNR 4,5
00.00.00.00
FF.FF.FF.FE
LNR 4,5
00.00.00.02
FF.FF.FF.FE
LNR 4,8
00.00.00.02
00.00.00.00
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loaded into the register 1st operand.
register 2nd operand before
register 2nd operand after
FF.FF.FF.FC
FF.FF.FF.FC
00.00.00.02
00.00.00.02
00.00.00.00
00.00.00.00
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Machine Instructions - LPR
LPR (Load Positive Register)
Machine Instruction
Code
10 (RR Instruction)
Condition code
00
01
10
11
Possible
Interruptions
0008
Result = 0
Condition code is not set as 1 after LPR.
Result > 0
Overflow
The binary number of the 2nd operand converted to positive and loaded into the register 1st operand.
Positive numbers and zero remain unchanged.
The overflow occurs when the maximum negative value is converted to positive; in this case, the number
remains unchanged. Examples:
Suppose the operands with the length and values shown in the “before” line
register 1st operand before
register 2nd operand before
register1st operand after
register 2nd operand after
LPR 4,5
00.00.00.00
FF.FF.FF.FC
00.00.00.04
FF.FF.FF.FC
LPR 4,5
00.00.00.02
00.00.00.02
00.00.00.02
00.00.00.02
LPR 4,8
00.00.00.FF
00.00.00.00
00.00.00.00
00.00.00.00
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Machine Instructions - LR
LR (Load Register)
Machine Instruction
Code
Condition code
18 (RR Instruction)
Possible
Interruptions
No interruptions occur
Remains unchanged
The contents of the register 2nd operand is loaded into the register 1st operand. Example:
Suppose the operands with the length and values shown in the “before” line
register 1st operand before
register 2nd operand before
register1st operand after
register 2nd operand after
LR 4,5
00.00.00.00
FF.FF.FF.FC
FF.FF.FF.FC
FF.FF.FF.FC
LR 4,5
00.00.12.34
00.00.00.02
00.00.00.02
00.00.00.02
LR 4,8
00.00.00.02
00.00.00.00
00.00.00.00
00.00.00.00
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Machine Instructions - LTR
LTR (Load and Test Register)
Machine Instruction
Code
12 (RR Instruction)
Condition code
00
01
10
11
Possible
Interruptions
No interruptions occur
Result = 0
Result < 0
Result > 0
Condition code is not set as 11 after LTR
The contents of register 2nd operand is loaded into the register 1st operand; the condition code is set
according to the number loaded. Example:
Suppose the operands with the length and values shown in the “before” line
register 1st operand before
register 2nd operand before
register1st operand after
register 2nd operand after
LTR 4,5
00.00.00.00
FF.FF.FF.FC
FF.FF.FF.FC
FF.FF.FF.FC
LTR 4,5
00.00.12.34
00.00.00.02
00.00.00.02
00.00.00.02
LTR 4,8
00.00.00.02
00.00.00.00
00.00.00.00
00.00.00.00
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Machine Instructions - M
M (Multiply)
Machine Instruction
Code
Condition code
5C (RX Instruction)
Possible
Interruptions
0005,0006
Remains unchanged
This instruction multiplies two binary numbers.
Register 1st operand must be an even register. The odd register following it must contain the
multiplicand.
The 2nd operand storage field must contain the multiplier.
The result is a 64-bit fixed-point binary number stored into the pair of even-odd registers (specified by
the 1st operand). Examples:
Register 6 before Register 7 before
2nd operand before
Register 6 after
Register 7 after
2nd operand after
M
6,FLDA
[ Multiplicand: Register 7; Multiplier: FLDA; Result: Registers 6 and 7 together ]
00.00.00.00 00.00.00.0A
00.00.00.02
00.00.00.00 00.00.00.14
00.00.00.02
M
6,=F'256' Multiplicand: Register 7; Multiplier: 256; Result: Registers 6 and 7 together
00.00.00.00 00.00.04.00
00.00.00.FF
00.00.00.00 00.03.FC.00
00.00.00.FF
M
6,4(2,8) Multiplicand: Register 7; Multiplier address: Index reg 2 + Base reg 8 + X’4’;
Result: Registers 6 and 7 together
00.00.00.00 00.00.04.00
00.00.01.0A
00.00.00.00 00.04.28.00
00.00.01.0A
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Machine Instructions - M
M (Multiply)
Machine Instruction
Code
Condition code
5C (RX Instruction)
Possible
Interruptions
0005,0006
Remains unchanged
More examples:
M
M
Register 6 before Register 7 before
2nd operand before
Register 6 after
Register 7 after
2nd operand after
6,4(2)
Multiplicand: Register 7; Multiplier address: Reg index 2 [ + Reg base 0 ] + X’4’;
Result: Registers 6 and 7 together
00.00.00.00 00.00.00.0C
00.00.00.02
00.00.00.00 00.00.00.18
00.00.00.02
6,FLD+4(1) Multiplicand: Reg 7; Multiplier address: Reg index 1 + Base register of FLD+4
+ Displacement of FLD+4 + X’4’; Result: Registers 6 and 7 together
00.00.00.00 00.00.AA.AA
00.11.22.33
00.00.00.0B 6C.16.93.DE
00.11.22.33
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Machine Instructions - MC
MC (Monitor Call)
Machine Instruction
Code
Condition code
AF (SI Instruction)
Possible
Interruptions
0006,0040
Remains unchanged
This instruction causes a program interruption if the bit that controls this event is ON in the control
register.
The control register mask bits are the bits 16-31, end they correspond to the classes 0-15 respectively.
The leftmost 4 bits of 2nd operand (immediate) must be zero.
The rightmost 4 bits of 2nd operand specify abinary number indicating the desired interruption class.
If the corresponding bit in the control register 8is ON, interruption will occur.
The 2nd operand address is not a storage address; it is a code to be stored at the storage address
X'000156'.
If the mask referred to the desired interruption is OFF in the control register 8, instruction processes
as a NOP (no operation).
Example:
MC
MONITCOD,7
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Machine Instructions - MH
MH (Multiply Halfword)
Machine Instruction
Code
Condition code
4C (RX Instruction)
Possible
Interruptions
0005
Remains unchanged
This instruction multiplies two binary numbers.
Register 1st operand must have the multiplicand. The 2nd operand 2-byte storage field must contain the
multiplier.
The result is a 32-bit fixed-point binary number stored into the register 1st operand. Example:
Note that if an overflow occurs (this event is NOT indicated in the condition code) the result sign may not be
correct. If result = zero, sign is same as positive number.
Examples:
Register 1st operand before 2nd operand before
Register 1st operand after
2nd operand after
MH 5,=H'4' [ Multiplicand: Register 5; Multiplier: literal 4; Result: Register 5 ]
00.00.00.0A
00.04
00.00.00.28
00.04
MH 5,=F'2' Multiplicand: Register 5; Multiplier: 0 [ left half of the fullword is taken as the
halfword 2nd operand] ; Result: Register 5
00.00.04.00
00.00
[TAKE CARE! right half with 00.02 not taken! ]
00.00.00.00
00.00
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Machine Instructions - MP
MP (Multiply Packed)
Machine Instruction
Code
Condition code
FC (SS Instruction – L1 e L2)
Possible
Interruptions
0001,0004,0005,0006,0007
Remains unchanged
This instruction multiplies two decimal packed numbers, both in storage fields.
The result is stored in the 1st operand.
2nd operand can be up to 8 bytes.
2nd operand length must be less than the length of the 1st operand.
If 2nd operand length is greater than or equal to the length of the 1st operand, an interruption will occur
(code 0006).
1st operand must have as many zero leftmost digits as many digits the 2nd operand has. If it doesn’t happen,
interruption 0007 will occur.
Example:
MP
FLDA,FLDB
1st operand before
2nd operand before
1st operand after
2nd operand after
00.09.99.9C
99.9C
99.89.00.1C
99.9C
00.19.99.9C
99.9C
00.19.99.9C
99.9C
(Error! FLDA must have at least 3 leftmost digits with zero)
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Machine Instructions - MR
MR (Multiply Register)
Machine Instruction
Code
Condition code
1C (RR Instruction)
Possible
Interruptions
0006
Remains unchanged
This instruction multiplies two binary numbers, both in registers.
Register 1st operand must be an even register (its contents is not considered in the operation, unless it is
[also] the multiplier). The odd register following it must contain the multiplicand.
The 2nd operand register must contain the multiplier.
The result is a 64-bit fixed-point binary number stored into the pair of even-odd registers (specified by
the 1st operand). Example:
MR
6,9
MR
6,9
Register 6 before Register 7 before
Register 9 before
Register 6 after
Register 7 after
Register 9 after
[ Multiplicand: Register 7; Multiplier: register 9; Result: Registers 6 and 7 together ]
00.00.00.00 00.00.00.0A
00.00.00.02
00.00.00.00 00.00.00.14
00.00.00.02
[ Multiplicand: Register 7; Multiplier: register 9; Result: Registers 6 and 7 together ]
00.00.00.00 99.AA.BB.CC
00.FF.FF.FF
00.99.AA.BB 32.55.44.34
00.FF.FF.FF
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Machine Instructions - MVC
MVC (MoVe Character)
Machine Instruction
Code
Condition code
D2 (SS Instruction - L)
Possible
Interruptions
0004,0005
Remains unchanged
This instruction moves (copies) the contents of stotage field to another storage field.
The move is done left to right, each byte at a time. Example:
MVC FLDA,FLDB
before
after
FLDB
C1.C2.C3
C1.C2.C3
FLDA
C4.C5.C6
C1.C2.C3
The sending field is the 2nd operand and remains unchanged (unless part of it is at the same time the
receiving field = overlapping). The receiving field is the 1st operand. The quantity of bytes moved is
determined by the 1st operand length, and both operands are treated with this same length. Examples:
Suppose the operands with the length and values shown in the “before” line
1st operand before
2nd operand before
1st operand after
2nd operand after
MVC
WA+5(3),WR+2
40.40.40
E5.C1.D3
E5.C1.D3
E5.C1.D3
MVC
WOUT,WIN
00.00.00.00.00
00.00.00.00.1C
00.00.00.00.1C
00.00.00.00.1C
MVC
NICKNAM,=C'SMAIL' C3.D9.E8.40.40
E2.D4.C1.C9.D3
E2.D4.C1.C9.D3
E2.D4.C1.C9.D3
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Machine Instructions - MVC
MVC (MoVe Character)
Machine Instruction
Code
Condition code
D2 (SS Instruction - L)
Possible
Interruptions
0004,0005
Remains unchanged
More examples:
Move spaces using an auxiliary 5-byte field (a 5-byte literal) :
Suppose the operands with the length and values shown in the “before” line
1st operand before
2nd operand before
1st operand after
2nd operand after
MVC
WA(5),=CL5' '
5C.5C.5C.5C.5C
40.40.40.40.40
40.40.40.40.40
40.40.40.40.40
Alternatively, one may propagate spaces using na auxiliary 1-byte area (the literal) !
- The first MVC moves space to the leftmost byte of WA.
- The second one moves 4 bytes; remember that MVC operates one byte at a time.
- Follow the 4-byte move, one at a time:
 The 1st byte is moved to the 2nd; The 2nd to the 3rd; The 3rd byte to the 4th; The 4th byte to the 5th.
Initial MVC for the leftmost byte:
MVC
WA(1),=C' '
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5C.??.??.??.??
40.??.??.??.??
Mach.Inst.Summary
40
40
before
after
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323
Machine Instructions - MVC
MVC (MoVe Character)
Machine Instruction
Code
Condition code
D2 (SS Instruction - L)
Possible
Interruptions
0004,0005
Remains unchanged
Propagation from 1st to 2nd, from 2nd to 3rd, from 3rd to 4th and from 4th to 5th
MVC
WA+1(4),WA
Or, better yet:
Follow MVC one byte at a time :
40.??.??.??.??
40.40.??.??.??
40.??.??.??.??
40.40.??.??.??
1st move: 40.??.??.??.?? Before
40.40.??.??.??
40.40.40.??.??
40.40.??.??.??
40.40.40.??.??
2nd move: 40.40.??.??.?? Before
3rd byte move :
40.40.40.??.??
40.40.40.40.??
40.40.40.??.??
40.40.40.40.??
3rd move: 40.40.40.??.?? Before
4th byte move :
40.40.40.40.??
40.40.40.40.40
40.40.40.40.??
40.40.40.40.40
1st byte move:
2nd byte move :
40.40.??.??.?? After
40.40.40.??.?? After
40.40.40.40.?? After
4th move: 40.40.40.40.?? Before
40.40.40.40.40 After
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Machine Instructions - MVCIN
MVCIN (MoVe Character Inverted)
Machine Instruction
Code
Condition code
E8 (SS Instruction – L)
Possible
Interruptions
0001,0004,0005
Remains unchanged
This instruction moves (copies) the contents of the 2nd operand to the 1st operand (both are storage
fields) in an inverted sequence.
Note that the 1st operand address is its leftmost byte, and the 2nd operand address is its rightmost byte.
Move is done each byte at a time.
From the sending field’s view its from right to left.
From the receiving field’s view its from left to right.
If occurs any overlay (superposition), results are unpredictable.
Example:
Suppose the operands with the length and values shown in the “before” line
1st operand before
2nd operand before
1st operand after
2nd operand after
MVCIN A(3),B+2
C4.C5.C6
C1.C2.C3
C3.C2.C1
C1.C2.C3
MVCIN A(5),BETA
C4.C5.C6.C7.C8
C1.C2.C3.C4.C5
C5.C4.C3.C2.C1
C1.C2.C3.C4.C5
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325
Machine Instructions - MVCL
MVCL (MoVe Character Long)
Machine Instruction
Code
0E (RR Instruction)
Condition code
00
Length of 1st operand is equal to length of
2nd operand
01
Length of 1st operand is less than length of
2nd operand
10
Length of 1st operand is greater than length
0004,0005,0006
of 2nd operand
11
Move not executed
Possible
Interruptions
Both 1st and 2nd operands must be even registers. They indicate a couple of (even-odd) registers, herein
dubbed R1st, R1st+1, R2nd and R2nd+1
This instruction move a storage field (sending field) to another storage field (receiving field), each byte at a
time, left to right.
Receiving field address must be in the 3 rightmost bytes of R1st.
Sending field address must be in the 3 rightmost bytes of R2nd.
Receiving field length must be in the 3 rightmost bytes of R1st+1.
Sending field length must be in the 3 rightmost bytes of R2nd+1.
The leftmost byte of R2nd+1 must contain the padding character.
The leftmost byte of R1st is ignored. Same happens with leftmost byte of R1st+1 and leftmost byte of R2nd.
Example:
MVCL
2,8
See details on following slide.
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Machine Instructions - MVCL
MVCL (MoVe Character Long)
Machine Instruction
Code
Condition code
Possible
Interruptions
L
L
L
L
ICM
MVCL
0E (RR Instruction)
00
Length of 1st operand is equal to length of
2nd operand
01
Length of 1st operand is less than length of
2nd operand
10
Length of 1st operand is greater than length
0004,0005,0006
of 2nd operand
11
Move not executed
2,=A(RECEIVE)
3,=A(L’RECEIVE)
8,=A(SENDING)
9,=A(L’SENDING)
9,B'1000',=C'*'
2,8
If sending field wraps from byte 16.777.215 to byte 0 (or not), move is executed this way:
· The move is executed while the receiving field’s leftmost byte is the same or it’s at the left of the leftmost
byte of the sending field OR the move is executed while the receiving field’s leftmost byte is at the right of
the rightmost byte of the sending field.
· The move is executed while the receiving field’s leftmost byte is the same or is at the left of the leftmost
byte of the sending field AND the receiving field’s leftmost byte is at the right of the rightmost byte of the
sending field.
The (address of the) rightmost byte of the sending field is computed using the length of the receiving or
sending field (the smaller).
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Machine Instructions - MVCL
MVCL (MoVe Character Long)
Machine Instruction
Code
Condition code
Possible
Interruptions
0E (RR Instruction)
00
Length of 1st operand is equal to length of
2nd operand
01
Length of 1st operand is less than length of
2nd operand
10
Length of 1st operand is greater than length
0004,0005,0006
of 2nd operand
11
Move not executed
After move:
- The 3 rightmost bytes of R1st+1 (previously with the receiving field length) are set to zero (in fact, at each
byte moved, it’s decremented by 1; , it is the amount of remaining bytes to move; at the end of operation
remaining bytes to move = zero).
To the 3 rightmost bytes of R1st (previously with the receiving field address) is added the length originally
specified in R1st+1 (in fact, at each byte moved, it’s incremented by 1 = next receiving byte address).
From the 3 rightmost bytes of R2nd+1 (originally with the sending field length) is subtracted the amount of
moved bytes (in fact at each byte move it is decremented by 1, it is the amount of remaining bytes to move;
at the end remaining bytes to move = zero)
- To the 3 rightmost bytes of R2nd (previously with sending field address) it is added the number of bytes
moved from sending to receiving field (in fact, at each byte moved, it’s incremented by 1 = next sending byte
address)
Leftmost R1st byte and leftmost R2nd byte are set to zero, even if move is not done.
- Leftmost R1st+1 byte and leftmost R2nd+1 byte remain unchanged.
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Machine Instructions - MVI
MVI (MoVe Immediate)
Machine Instruction
Code
Condition code
92 (SI Instruction)
Possible
Interruptions
0004,0005
Remains unchanged
This instruction moves (copies) a constant 1-byte storage field (2nd operand – immediate operand) to
another storage 1-byte field.
2nd operand (mmediate operand) is the sending field and 1st operand is the receiving field.
Examples:
MVI
FLDA,C'*'
or
MVI
FLDA,X'5C'
or
MVI
FLDA,B'01011100'
or
MVI
FLDA,92
FLDA before
FLDA after
12
5C
Immediate operand before
Immediate operand after
5C
5C
Other examples:
MVI
MVI
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WAREA+72,C'/'
0(4),X'80'
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329
Machine Instructions - MVN
MVN (MoVe Numerics)
Machine Instruction
Code
Condition code
D1 (SS Instruction - L)
Possible
Interruptions
0004,0005
Remains unchanged
This instruction is similar to MVC, but it moves onle the right half of the bytes.
Example:
Suppose the operands with the length and values shown in the “before” line
1st operand before
2nd operand before
1st operand after
2nd operand after
MVN FLDA,FLB
12.34.56
78.9A.BC
18.3A.5C
78.9A.BC
MVN TOT+4(1),=X'0C' 00.12.30.00.2F
0C
00.12.30.00.2C
0C
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Machine Instructions - MVO
MVO (MoVe with Offset)
Machine Instruction
Code
Condition code
F1 (SS Instruction – L1 e L2)
Possible
Interruptions
0004,0005
Remains unchanged
The MVO instruction moves the contents of the 2nd operand storage field to the 1st operand storage field,
from righ to left, with displacement of half byte: the right half of the receveing field rightmost byte remains
unchanged. The right half of the rightmost byte of sending field is sent to the left half of the rightmost byte of
receiving field. And so on.
If 1st operand isn’t large enough to receive all digits sent from the 1st operand, the leftmost half-bytes are
truncated.
If 1st operand is larger than enough to receive all digits sent from the 1st operand, the leftmost half-bytes are
filled with X’0’.
Examples:
MVO
RECFLD,SENFLD
SENFLD Before
00.00.12.00
SENFLD After
00.00.12.00
RECFLD Before
00.00.00.0C
RECFLD After
00.01.20.0C
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Machine Instructions - MVO
MVO (MoVe with Offset)
Machine Instruction
Code
Condition code
F1 (SS Instruction – L1 e L2)
Possible
Interruptions
0004,0005
MVO
Remains unchanged
CPOA,CPOB
Before
After
1º Case
CPOB
CPOA
12.34.56
78.9A
12.34.56
45.6A
CPOB
CPOA
AB.72
4A.5C.B9.FC
AB.72
00.0A.B7.2C
2º Case
Other examples:
MVO
MVO
MVO
MVO
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ARCALC(5),ARCALC(4)
0(4,7),ARCALC
AREA,2(5,8)
2(7,13),19(5,15)
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Machine Instructions - MVZ
MVZ (MoVe Zones)
Machine Instruction
Code
Condition code
D3 (SS Instruction – L)
Possible
Interruptions
0004,0005
Remains unchanged
The MVZ instruction is similar to the MVC, but it moves onle the left half of the bytes. Examples:
Suppose the operands with the length and values shown in the “before” line
1st operand before
2nd operand before
1st operand after
2nd operand after
MVZ FLDA,FLB
12.34.56
78.9A.BC
72.94.B6
78.9A.BC
MVZ TOT,=4C'0'
01.02.03.04.C5
F0.F0.F0.F0.F0
F1.F2.F3.F4.F5
F0.F0.F0.F0.F0
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Machine Instructions - N
N ([boolean] aNd)
Machine Instruction
Code
54 (RX Instruction)
Condition code
00
01
10
11
0005
Possible
Interruptions
Result = 0
Result <> 0
Condition code is not set as 10 after N
Condition code is not set as 11 after N
This instruction executes a boolean AND between a register (1st operand) and a 4-byte storage field
(2nd operand).
Mask bit =0 then result bit = 0; mask bit = 1 then reault bit =
remain unchanged
Example:
N
13,FIELDX
Before
After
Register 13
B4.EF.2F.A8
00.00.00.A8
FIELDX
00.00.00.FF
00.00.00.FF
Other examples:
N
11,=F'15'
N
3,0(4)
N
3,0(,4)
N
3,0(8,4)
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Machine Instructions - NC
NC ([boolean] aNd Character)
Machine Instruction
Code
D4 (SS Instruction – L)
Condition code
00
01
10
11
Possible
Interruptions
0004, 0005
Result = 0
Result <> 0
Condition code is not set as 10 after NC
Condition code is not set as 11 after NC
This instruction executes a boolean AND between 2 storage fields (1st and 2nd operands).
Mask bit =0 then result bit = 0; mask bit = 1 then reault bit =
remain unchanged
Example:
NC
FLDA
FLDB
Summary
FLDA,FLDB
Before
After
EF.2F.A8
00.00.A8
00.00.FF
00.00.FF
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Machine Instructions - NI
NI ([boolean] aNd [with] Immediate [operand])
Machine Instruction
Code
94 (SI Instruction)
Condition code
00
01
10
11
Possible
Interruptions
0004, 0005
Result = 0
Result <> 0
Condition code is not set as 10 after NI
Condition code is not set as 11 after NI
This instruction executes a boolean AND between 2 storage fields (1 byte each; 1st operand = field
specified using its address; 2nd operand = immediate field, it’s the 2nd byte of the instruction).
Mask bit =0 then result bit = 0; mask bit = 1 then reault bit =
remain unchanged
Example:
NI
BYTE,X'0F'
Before
After
BYTE
B4
04
Immediate Op. 0F
0F
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Machine Instructions - NR
NR ([boolean] aNd Register)
Machine Instruction
Code
14 (RR Instruction)
Condition code
00
01
10
11
Possible
Interruptions
No interruptions occur
Result = 0
Result <> 0
Condition code is not set as 10 after NR
Condition code is not set as 11 after NR
This instruction executes a boolean AND between 2 registers.
Mask bit =0 then result bit = 0; mask bit = 1 then reault bit =
remain unchanged
Example:
NR
5,8
Before
After
Register 5
B4.EF.2F.A8
00.00.00.A8
Register 8
00.00.00.FF
00.00.00.FF
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Machine Instructions - O
O ([boolean] Or)
Machine Instruction
Code
56 (RX Instruction)
Condition code
00
01
10
11
Possible
Interruptions
0005
Result = 0
Result <> 0
Condition code is not set as 10 after O
Condition code is not set as 11 after O
This instruction executes a boolean OR between a register (1st operand) and a 4-byte storage field
(2nd operand).
Mask bit =0 then result bit = remains unchanged; mask bit = 1 then
reault bit = 1
Example:
O
Register 13
FIELDF
Summary
13,FIELDF
Before
After
B4.EF.2F.A8
00.00.00.FF
B4.EF.2F.FF
00.00.00.FF
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Machine Instructions - OC
OC ([boolean] Or Character)
Machine Instruction
Code
D6 (SS Instruction – L)
Condition code
00
01
10
11
Possible
Interruptions
0004, 0005
Result = 0
Result <> 0
Condition code is not set as 10 after OC
Condition code is not set as 11 after OC
This instruction executes a boolean OR between 2 storage fields (1st and 2nd operands).
Mask bit =0 then result bit = remains unchanged; mask bit = 1
then reault bit = 1
Example:
OC
FLDA,FLDB
FLDA
FLDB
Summary
Before
After
EF.2F.A8
00.00.FF
EF.2F.FF
00.00.FF
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Machine Instructions - OI
OI ([boolean] Or [with] Immediate [operand])
Machine Instruction
Code
96 (SI Instruction)
Condition code
00
01
10
11
Possible
Interruptions
0004, 0005
Result = 0
Result <> 0
Condition code is not set as 10 after OI
Condition code is not set as 11 after OI
This instruction executes a boolean OR between 2 storage fields (1 byte each; 1st operand = field
specified using its address; 2nd operand = immediate field, it’s the 2nd byte of the instruction).
Mask bit =0 then result bit = remains unchanged; mask bit = 1 then
reault bit = 1
Example:
OI
BYTE,X'0F'
Before
After
B4
0F
BF
0F
BYTE
Immediate Operand
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Machine Instructions - OR
OR ([boolean] Or Register)
Machine Instruction
Code
16 (RR Instruction)
Condition code
00
01
10
11
Possible
Interruptions
No interruptions occur
Result = 0
Result <> 0
Condition code is not set as 10 after OR
Condition code is not set as 11 after OR
This instruction executes a boolean OR between 2 registers.
Mask bit =0 then result bit = remains unchanged; mask bit = 1 then
reault bit = 1
Example:
OR
5,8
Reg. 5
Reg. 8
Before
After
B4.EF.2F.A8
00.00.00.FF
B4.EF.2F.FF
00.00.00.FF
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Machine Instructions - PACK
PACK
Machine Instruction
Code
Condition code
F2 (SS Instruction – L1 e L2)
Possible
Interruptions
0004,0005
Remains unchanged
The PACK instruction moves a storage zoned field to a storage packed field. The intended function is
to convert a numeric field from zoned format to packed format. NO validation is done in the sending
field; if its contents is not a valid decimal zoned number, the operation flows normally.
1st operand is the receiving field and 2nd operand is the sending field. The operation is done from
right to left.
The two halves of the rightmost byte of the sending field are inverted and moved to the rightmost byte
of the receiving field.
After that, each right half byte of the sending field is sent to a half of the receiving field. 2nd operand
remains unchanged.
If the receiving field is smaller than needed to fit all digits from the sending field, the leftmost digits
are truncated.
If the receiving field is greater than needed to fit all digits from sending field, the remaining left digits
are filled with X’0’.
Example:
PACK
FLDA,FLDB
Before
After
FLDB
F1.F2.F3.F4
F1.F2.F3.F4
FLDA
00.B7.2A
01.23.4F
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Machine Instructions - PACK
PACK
Machine Instruction
Code
Condition code
F2 (SS Instruction – L1 e L2)
Possible
Interruptions
0004,0005
Remains unchanged
PACK
FLDA,FLDB
2ºcase
FLDB
FLDA
F1.F2.F3.F4
C9.4A
F1.F2.F3.F4
23.4F
3ºcase
FLDB
9A.48.F9.DB
9A.48.F9.DB
FLDA
19.B7.DF
0A.89.BD
Note the 3rd case. The sending field is not validated about being zoned. The receiving field may
not become a valid decimal packed field.
More examples:
PACK
VALUE,READAREA+5(9)
PACK
HOWMUCH+2(7),2(8,5)
PACK
0(10,2),AREA
PACK
2(5,7),2(3,8)
PACK
DOUBLE,DOUBLE
PACK
BYTE,BYTE
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Machine Instructions - S
S (Subtract)
Machine Instruction
Code
5B (RX Instruction)
Condition code
00
Result = 0
01
Result < 0
10
Result > 0
11
Overflow
0005,0008
Possible
Interruptions
Instruction S subtracts algebraically the binary number in the 4-byte storage field 2nd operand from
the bynary number of the register 1st operand. Result is stored into 1st operand register.
Examples:
Suppose the operands with the length and values shown in the “before” line
S
5,=F'259'
S
7,FULL
S
7,4(2,8)
S
7,4(2)
S
7,4(,8)
Summary
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register 1st operand before
register 1st operand after
00.00.BF.D2
00.00.BE.CF
00.00.00.0D
FF.FF.FF.0A
07.FF.FF.FE
07.FF.FF.FD
07.FF.FF.FF
07.FF.FF.FD
00.00.00.00
00.00.00.01
Mach.Inst.Summary
2nd operand before
2nd operand after
00.00.01.03
00.00.01.03
00.00.01.03
00.00.01.03
00.00.00.01
00.00.00.01
00.00.00.02
00.00.00.02
FF.FF.FF.FF
FF.FF.FF.FF
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Machine Instructions - SH
SH (Subtract Halfword)
Machine Instruction
Code
4B (RX Instruction)
Condition code
00
01
10
11
Possible
Interruptions
0005,0008
Result = 0
Result < 0
Result > 0
Overflow
Instruction SH subtracts algebraically the binary number in the 2-byte storage field 2nd operand from the
bynary number of the register 1st operand. Result is stored into 1st operand register. Examples:
Suppose the operands with the length and values shown in the “before” line
register 1st operand before
2nd operand before
register 1st operand after
2nd operand after
SH
5,=H'259'
00.00.2B.C4
01.03
00.00.2A.C1
01.03
SH
5,HALF
00.00.00.0D
01.0D
FF.FF.FF.00
01.0D
SH
5,4(2,8)
11.11.11.11 (decimal 286331153)
88.88 (decimal –30584)
11.11.88.89 (decimal 286361737)
88.88
SH
5,4(2)
11.11.11.11 (decimal 286331153)
78.88 (decimal +30856)
11.10.98.89 (decimal 286300297)
78.88
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Machine Instructions - SL
SL (Subtract Logical)
Machine Instruction
Code
Condition code
5F (RX Instruction)
Possible
Interruptions
0005
00
01
10
11
Condition code is not set as 00 after SL
Result <> 0, sign not lost
Result = 0, sign lost
Result <> 0, sign lost
Instruction S subtracts logically the binary number in the 4-byte storage field 2nd operand from the
binary number of the register 1st operand. Result is stored into 1st operand register. Examples:
Suppose the operands with the length and values shown in the “before” line
register 1st operand before
2nd operand before
register 1st operand after
2nd operand after
SL
5,=F'259'
00.00.BF.D2
00.00.01.03
00.00.BE.CF
00.00.01.03
SL
7,FULL
00.00.00.0D
00.00.00.03
00.00.00.0A
00.00.00.03
SL
7,4(2,8)
07.FF.FF.FE
00.00.00.01
07.FF.FF.FD
00.00.00.01
SL
7,4(2)
07.FF.FF.FF
00.00.00.02
07.FF.FF.FD
00.00.00.02
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Machine Instructions - SLA
SLA (Shift Left Algebraic)
Machine Instruction
Code
8B (RS Instruction)
Condition code
00
01
10
11
Possible
Interruptions
No interruptions occur
Result = 0
Result < 0
Result > 0
Overflow
This instruction shifts algebraically, to the left, the bits of the register 1st operand.
The sign bit remains unchanged, and the other 31 bits are shifted.
The “new” bits to the right are set to zero.
It’s an RS instruction, and its bits 12-15 are ignored.
The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of
bits to shift; maximum is 15.
Example:
SLA
5,3
Register 5 before Shift
FF.80.9A.00
Register 5 after Shift
FC.04.D0.00
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Machine Instructions SLDA
SLDA (Shift Left Double Algebraic)
Machine Instruction
Code
8F (RS Instruction)
Condition code
00
01
10
11
Possible
Interruptions
0004, 0008
Result = 0
Result < 0
Result > 0
Overflow
The register specified as 1st operand indicates the a pair of registers (R1st and R1st+1), taken as a
number with 64-bit (1 bit = sign; 63 bits = number).
This instruction shifts algebraically, to the left, the bits of the number inside the 2 registers (both
treated as only onr number).
The sign bit remains unchanged, and the other 63 bits are shifted.
The “new” bits to the right are set to zero.
It’s an RS instruction, and its bits 12-15 are ignored.
The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of bits
to shift; maximum is 63.
Example:
SLDA
8,3
Registers 8 and 9 before Shift
00.00.00.00 FF.80.9A.00
Registers 8 and 9 after Shift
00.00.00.07 FC.04.D0.00
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Machine Instructions - SLDL
SLDL (Shift Left Double Logical)
Machine Instruction
Code
Condition code
8D (RS Instruction)
Possible
Interruptions
0006
Remains unchanged
The register specified as 1st operand indicates a pair of registers (R1st and R1st+1), taken as a
number with 64-bit.
This instruction shifts logically, to the left, the bits of the number inside the 2 registers (both treated
as only onr number).
All 64 bits are shifted (including sign bit).
The “new” bits to the right are set to zero.
It’s an RS instruction, and its bits 12-15 are ignored.
The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of
bits to shift; maximum is 63.
Example: SLDL
8,4
Registers 8 and 9 before Shift
12.FE.3D.4C 5B.6A.78.90
8
9
Registers 8 and 9 after Shift
2F.E3.D4.C5 B6.A7.89.00
8
9
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Machine Instructions - SLL
SLL (Shift Left Logical)
Machine Instruction
Code
Condition code
89 (RS Instruction)
Possible
Interruptions
No interruptions occur
Remains unchanged
The register specified as 1st operand indicates a register, taken as a 32-bit number.
This instruction shifts logically, to the left, the bits of the number inside the register.
All 32 bits are shifted (including sign bit).
The “new” bits to the right are set to zero.
It’s an RS instruction, and its bits 12-15 are ignored.
The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of
bits to shift; maximum is 32.
Example:
SLL
5,2
Register 5 before Shift
B9.4F.FF.FF
Register 5 after Shift
E5.3F.FF.FC
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Machine Instructions - SLR
SLR (Subtract Logical Register)
Machine Instruction
Code
1F (RR Instruction)
Condition code
00
01
10
11
Possible
Interruptions
No interruptions occur
Condition code is not set as 00 after SLR
Result <> 0, sign not lost
Result = 0, sign lost
Result <> 0, sign lost
Instruction SLR subtracts logically the binary number in the register 2nd operand from the binary
number in the register 1st operand.
Result is stored into 1st operand register.
Example:
Suppose the operands with the length and values shown in the “before” line
SLR
7,12
SLR
10,11
Summary
register 1st operand before
register 1st operand after
00.B0.C4.E2
00.B0.C4.E1
80.00.00.00
7F.FF.FF.FF
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2nd operand before
2nd operand after
00.00.00.01
00.00.00.01
00.00.00.01
00.00.00.01
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Machine Instructions - SP
SP (Subtract Packed)
Machine Instruction
Code
FB (SS Instruction – L1 e L2)
Condition code
00
01
10
11
Possible
Interruptions
0001,0004,0005,0007,000A
Result = 0
Result < 0
Result > 0
Overflow
This instruction subtracts the contents of the 2nd operand from the contents of the 1st operand.
Both must be storage fields in the decimal packed format.
Result is stored into 1st operand field.
Examples:
SP
FLDA,FLDB
Before
After
FLDB
98.7C
98.7C
FLDA
12.34.5C
11.35.8C
More examples:
SP
VALUE,VALUE
SP
TOTAL,=P'1'
SP
AE+5(8),AE+15(3)
SP
0(2,7),4(1,8)
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Machine Instructions - SPM
SPM (Set Program Mask)
Machine Instruction
Code
Condition code
Possible
Interruptions
04 (RR Instruction)
Is set with the contents of bits 2 and 3 of
register 1st operand
No interruptions occur
This is RR instruction. Its bits 12-15 are not considered.
The contents of 1st operand register is used to take the values of condition code and program mask
to store them into PSW.
The value of bits 2-3 are set to the condition code.
The value of bits 4,5,6 and 7 are set to the PSW program mask.
The bits 0-1 and 8-31 are ignored.
Example:
SPM
8
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Machine Instructions - SR
SR (Subtract Register)
Machine Instruction
Code
1B (RR Instruction)
Condition code
00
01
10
11
Possible
Interruptions
0008
Result = 0
Result < 0
Result > 0
Overflow
This instruction subtracts the contents of the register 2nd operand from the contents of the register
1st operand. Result is stored into register 1st operand.
Then: Minuend : 1st operand ; Subtrahend : 2nd operand ; Result : 1st operand
Examples:
Suppose the operands with the length and values shown in the “before” line
Register 1st operand before
Register 2nd operand before
Register 1st operand after
Register 2nd operand after
SR 7,8
00.00.FF.FF
00.00.00.01
00.00.FF.FE
00.00.00.01
SR 2,2
00.00.FF.FF
00.00.FF.FF
00.00.00.00
00.00.00.00
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Machine Instructions - SRA
SRA (Shift Right Algebraic)
Machine Instruction
Code
8A (RS Instruction)
Condition code
00
01
10
11
Possible
Interruptions
No interruptions occur
Result = 0
Result < 0
Result > 0
Condition code is not set as 11 after SRA
This instruction shifts algebraically, to the right, the bits of the register 1st operand.
The sign bit remains unchanged, and the other 31 bits are shifted.
The “new” bits to the right are set to zero.
It’s an RS instruction, and its bits 12-15 are ignored.
The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of bits
to shift; maximum is 15.
Example:
SRA
5,3
Register 5 before Shift
FF.80.0A.00
Register 5 after Shift
8F.F0.01.40
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Machine Instructions - SRDA
SRDA (Shift Right Double Algebraic)
Machine Instruction
Code
8E (RS Instruction)
Condition code
00
01
10
11
Possible
Interruptions
0006
Result = 0
Result < 0
Result > 0
Condition code is not set as 11 after SRDA
The register specified as 1st operand indicates the a pair of registers (R1st and R1st+1), taken as a
number with 64-bit (1 bit = sign; 63 bits = number).
This instruction shifts algebraically, to the right, the bits of the number inside the 2 registers (both
treated as only one number).
The sign bit remains unchanged, and the other 63 bits are shifted.
The “new” bits to the left are set to zero.
It’s an RS instruction, and its bits 12-15 are ignored.
The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of
bits to shift; maximum is 63. Example:
SRDA
8,4
Registers 8 and 9 before Shift
04.20.08.91 C4.00.02.FF
Registers 8 and 9 after Shift
00.42.00.89 1C.40.00.2F
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Machine Instructions - SRDL
SRDL (Shift Right Double Logical)
Machine Instruction
Code
Condition code
8C (RS Instruction)
Remains unchanged
Possible
Interruptions
0006
The register specified as 1st operand indicates the a pair of registers (R1st and R1st+1), taken as a
number with 64-bit.
This instruction shifts logically, to the right, the bits of the number inside the 2 registers (both treated
as only onr number).
All 64 bits are shifted (including sign bit).
The “new” bits to the left are set to zero.
It’s an RS instruction, and its bits 12-15 are ignored.
The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of bits
to shift; maximum is 63.
Example:
SRDL
8,4
Registers 8 and 9 before Shift
12.FE.3D.4C 5B.6A.78.90
8
9
Registers 8 and 9 after Shift
01.2F.E3.D4 C5.B6.A7.89
8
9
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Machine Instructions - SRL
SRL (Shift Right Logical)
Machine Instruction
Code
Condition code
88 (RS Instruction)
Possible
Interruptions
No interruptions occur
Remains unchanged
The register specified as 1st operand indicates a register, taken as a 32-bit number.
This instruction shifts logically, to the right, the bits of the number inside the register.
All 32 bits are shifted (including sign bit).
The “new” bits to the left are set to zero.
It’s an RS instruction, and its bits 12-15 are ignored.
The 6 rightmost bits of the number computed as the 2nd operand address indicates the amount of
bits to shift; maximum is 32.
Example:
SRL
5,2
Register 5 before Shift
B9.4F.FF.FF
Register 5 after Shift
2E.53.FF.FF
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Machine Instructions - SRP
SRP (Shift and Round Packed)
Machine Instruction
Code
F0 (SS Instruction)
Condition code
00
01
10
11
Possible
Interruptions
0001,0004,0005,0007,000A
Result = 0
Result < 0
Result > 0
Overflow
This is a SS instruction, and its format is the following:
1 byte =
1/2 byte
1/2 byte
2 bytes
2 bytes
operation code
= L1 = 1st operand length - 1
= I3 = 3rd operand (immediate operand)
= 1st operand base+displacement address
= 2nd operand base+displacement address
The 1st operand is a decimal packed storage field; it is shifted based upon the information provided by the
2nd operand: the sense of shift and the amount of digits to be shifted.
If shift is to be done rightwards the number is rounded accordingly 3rd operand.
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Machine Instructions - SRP
SRP (Shift and Round Packed)
Machine Instruction
Code
F0 (SS Instruction)
Condition code
00
01
10
11
Possible
Interruptions
0001,0004,0005,0007,000A
Result = 0
Result < 0
Result > 0
Overflow
The 6 rightmost bits of the number computed as the “address” of 2nd operand are analysed this way:
 Leftmost bit indicates the sense of the shift: OFF means shift leftwards; ON means rightwards.
 The number composed by the remaining 5 bits indicates the amount of digits to be shifted (if shift
rightwards, this number is negative).
The round is done by adding the number specified in the 3rd operand to the last shifted digit and, if it is 1,
it is added to the number-result after shift. See the following examples:
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Machine Instructions - SRP
SRP (Shift and Round Packed)
Machine Instruction
Code
Condition code
Possible
Interruptions
SRP
SRP
F0 (SS Instruction)
00
Result = 0
01
Result < 0
10
Result > 0
11
Overflow
0001,0004,0005,0007,000A
TOTAL,61,5
TOTAL Before
12.34.56.78.9C
TOTAL After
00.01.23.45.7C
(shifts 3 digits to the right)
TOTAL,3,0
TOTAL Before
12.34.56.78.9C
TOTAL After
45.67.89.00.0C
(shifts 3 digits to the left)
These rules make it easier to specify shift sense and amount of digits:
Shift leftwards = specify directly the amount of digits
SRP TOTAL,3,5
Specify amount in the 2nd operand = shifts “amount” digits to the left
(in the example = 3)
Shift rightwards = specify (64 – amount of digits)
SRP TOTAL,64-3,5 Specify [64-amount] in the 2nd operand = shifts “amount” digits to the right
(In the example = 3)
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Machine Instructions - ST
ST (Store [from register to storage])
Machine Instruction
Code
Condition code
50 (RX Instruction)
Possible
Interruptions
0004,0005
Remains unchanged
The register 1st operand (remain unchanged and) is stored into the 2nd operand 4-byte storage field.
Examples:
Suppose the operands with the length and values shown in the “before” line
register 1st operand before
2nd operand before
register1st operand after
2nd operand after
ST 7,FULL
FE.DC.BA.98
00.01.00.00
FE.DC.BA.98
FE.DC.BA.98
ST 14,SAVE
00.00.00.11
FF.FF.FF.FD
00.00.00.11
00.00.00.11
Other examples:
ST
14,FULL+4
ST
14,0(2)
ST
14,0(,8)
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Machine Instructions - STC
STC (STore Character)
Machine Instruction
Code
Condition code
42 (RX Instruction)
Possible
Interruptions
0004,0005
Remains unchanged
The rightmost byte of register 1st operand (remain unchanged and) is stored into the 2nd operand
1-byte storage field. Examples:
Suppose the operands with the length and values shown in the “before” line
register 1st operand before
2nd operand before
register1st operand after
2nd operand after
STC 7,BYTE
FE.DC.BA.98
00
FE.DC.BA.98
98
STC 14,0(5)
00.00.00.11
FF
00.00.00.11
11
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Machine Instructions - STCK
STCK (STore ClocK)
Machine Instruction
Code
Condition code
Possible
Interruptions
B205 (Instrução S)
00 Clock status allows set
01 Clock status does not allow set
10 Clock status is error
11 Condition code is not set as 11 after STCK
0004
TOD clock contents is stored into the 8-byte storage field specified in the 2nd operand.
Clock must be is set, stop or no-set state.
The rightmost bytes are set to zero.
If TOD clock is in error state, contents stored is unpredictable.
If TOD clock is not operational, all bytes are set to zero.
Example:
STCK DW
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Machine Instructions - STCM
STCM (STore Character under Mask)
Machine Instruction
Code
Condition code
BE (RS Instruction)
Possible
Interruptions
0004,0005
Remains unchanged
The format of this instruction is:
1st byte: X’BE’ (operation code); 2nd byte, left half : 1st operand register ; 2nd byte, right half : 3rd operand (mask);
3rd and 4th bytes : 2nd operand address, base+displacement format.
The 4 bits in the mask correspond to the 4 bytes of the 1st operand register.
The storage field specified in the 2nd operand must have as many bytes as the ON bits in the mask.
The register 1st operand bytes corresponding to the ON bits of the mask are stored into the 2nd operand
storage bytes (taken as a contiguous field).
1st operand remains unchanged. Example:
Suppose the operands with the length and values shown in the “before” line
register 1st operand before
2nd operand before
register1st operand after
2nd operand after
STCM 5,B’1010’,TWOBYTES
00.00.45.67
9A.BC
00.00.45.67
00.45
1st byte of register 5 is stored into byte TWOBYTES and
3rd byte of register 5 is stored into byte TWOBYTES+1
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Machine Instructions - STH
STH (STore Halfword)
Machine Instruction
Code
Condition code
40 (RX Instruction)
Possible
Interruptions
0004,0005
Remains unchanged
The rightmost 2 bytes of register 1st operand (remain unchanged and) are stored into the 2nd operand
2-byte storage field. Example:
Suppose the operands with the length and values shown in the “before” line
register 1st operand before
2nd operand before
register1st operand after
2nd operand after
STH 5,FLD
00.00.00.0A
8A.B4
00.00.00.0A
00.0A
STH 8,HWORD
FF.FF.FF.FF
FF.FF
FF.FF.FF.FF
FF.FF
Other examples:
STH
14,SAVE+18
STH
14,0(2)
STH
14,0(,8)
STH
14,0(2,8)
STH
0,FLD
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Machine Instructions - STM
STM (STore Multiple)
Machine Instruction
Code
Condition code
Possible
Interruptions
90 (RX Instruction)
Remains unchanged
0004,0005
This instruction works with 3 operands: 1st and 3rd are registers, and 2nd is a storage field.
It stores the contents of the registers specified as a range by the 1st and 3rd operands into the storage field
2nd perand.
The length of the field depends on how many registers must be stored. To store 2 registers, the area must have
8 bytes; to store 3 registers, the area must have 12 bytes, and so on.
Example:
STM
14,1,SAVE
SAVE = 16 bytes (bytes 0-3 = contents of register 14; bytes 4-7 = contents of register ;
bytes 8-11 = contents of register 0; bytes 12-15 = contents of register 1)
|------- SAVE --------------------------------|
<----------><---------><----------><---------->
Reg. 14
Reg.15
Reg.0
Reg.1
Another example:
STM
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Machine Instructions - SVC
SVC (SuperVisor Call)
Machine Instruction
Code
Condition code
0A (RR Instruction)
Possible
Interruptions
No interruptions occur
(Remains unchanged in the old PSW)
The format of this instruction is:
1st byte = operation code; 2nd byte = SVC number
This instruction causes a program interruption; this interruption demands CPU to execute a call to the
operating system (supervisor) to execute some function.
The code (2nd byte – from 0 to 255 – X’00’ up to X’FF’) determines the function to be executed by
supervisor .
Examples:
SVC
0
SVC
7
Some MVS-z/OS SVCs:
X'00' (000) = EXCP/XDAP
X'13' (019) = OPEN
X'01' (001) = WAIT/WAITR/PRTOV
X'14' (020) = CLOSE
X'02' (002) = POST
X'23' (035) = WTO/WTOR
X'04' (004) = GETMAIN
X'24' (036) = WTL
X'05' (005) = FREEMAIN
X'5D' (093) = TGET/TPUT
X'0B' (011) = TIME
X'63' (099) = DYNALLOC
X'0D' (013) = ABEND
X'6B' (107) = MODESET
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Machine Instructions - TM
TM (Test under Mask)
Machine Instruction
Code
Condition code
91 (SI Instruction)
Possible
Interruptions
0005
00
01
10
11
All bits tested are OFF, or mask is zero
Some bits tested are ON and others are OFF
Condition code is not set as 10 after TM
All bits tested are ON
This instruction tests the bits of the 1-byte storage field specified by the 1st operand, using the mask
specified in the 2nd operand (self-defining term).
The mask indicates whose bits must be tested. The ON bits in the mask indicate the bits of the
stoprage byte to be tested.
Test means: is the bit(s) ON or OFF?
To reflect the result, condition code is set.
Example:
TM BYTE,X'9C'
Bits 0, 3, 4 and 5 of BYTE are tested
More examples:
TM KEYAB,B'10000001' Bits 0, and 7 of KEYAB are tested
TM 0(4),240
Bits 4,5,6 and 7 of [base register 4 + displacement X’0’] are tested
TM 2(8),X'80'
Bit 0 [base register 8 + displacement X’2’] is tested
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Machine Instructions - TR
TR (TRanslate)
Machine Instruction
Code
Condition code
DC (SS Instruction – L)
Possible
Interruptions
0004,0005
Remains unchanged
TR instruction moves the contents of 2nd operand to the 1st operand, according to the 1st operand
contents.
The move is done left to right, each byte at a time, this way:
 The contents of each byte of the 1st operand is added (internally) to the 2nd operand address;
 The byte at the resulting address is moved (copied) to the byte of the 1st operand.
 2nd operand remains unchanged
Example:
TR
ACSD,TABLE
Before
ACSD
02.00.08.FF.05
TABLE
C1.48.B9.D7.A1.C3.D9.5C.4B ........1A
256 bytes
After
ACSD
B9.C1.4B.1A.C3
TABLE
Remains unchanged
More examples :
TR
0(5,7),0(10)
TR
WAREA+7(10),TABASTER
TR
2(5,124),FIELD
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Machine Instructions - TR
TR (TRanslate)
Machine Instruction
Code
Condition code
DC (SS Instruction – L)
Possible
Interruptions
0004,0005
Remains unchanged
More examples :
To translate uppercase EBCDIC letters into lowercase EBCDIC letters; invalid letters are converted to EBCDIC spaces
CONVTB1 DC
256C' '
256 EBCDIC spaces
ORG CONVTB1+C'A'
“Return” to Uppercase A
DC C'abcdefghi'
Substitute original spaces by lowwercase
ORG CONVTB1+C'J'
“Return” to Uppercase J
DC C'jklmnopqr'
Substitute original spaces by lowwercase
ORG CONVTB1+C'S'
“Return” to Uppercase S
DC C'stuvwxyz'
Substitute original spaces by lowwercase
ORG
, Return to byte folowing CONVTB1
To translate uppercase EBCDIC letters into uppercase ASCII letters; invalid letters are converted to ASCII spaces
CONVTB2 DC
256X'20'
256 ASCII spaces
ORG CONVTB2+C'A'
“Return” to Uppercase A
DC X'414243444546474849'
Substitute EBCDIC value by ASCII value
ORG CONVTB1+C'J'
“Return” to Uppercase J
DC X'4A4B4C4D4E4F505152'
Substitute EBCDIC value by ASCII value
ORG CONVTB1+C'S'
“Return” to Uppercase S
DC X'535455565758595A'
Substitute EBCDIC value by ASCII value
ORG
, Return to byte folowing CONVTB2
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371
Machine Instructions - TR
TR (TRanslate)
Machine Instruction
Code
Condition code
DC (SS Instruction – L)
Possible
Interruptions
0004,0005
Remains unchanged
More examples :
To translate uppercase ASCII letters into uppercase EBCDIC letters; invalid “letters” are converted to EBCDIC spaces
CONVTB3 DC
256X'40'
256 EBCDIC spaces
ORG CONVTB2+X'41'
Volta para A maiusculo ASCII
DC C'ABCDEFGHIJKLMNOPQRSTUVWXYZ' Substitui ASCII value by EBCDIC
ORG
, Return to byte CONVTB3+256
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372
Machine Instructions - TRT
TRT (TRanslate and Test)
Machine Instruction
Code
Condition code
Possible
Interruptions
DD (SS Instruction – L)
00 All bytes tested are with X'00'
01 Test ended before the last byte to be tested.
10 Test ended at the last byte to be tested, and
it wasn’t with X'00'
11
0005Condition code is not set as 11 after TRT
This instruction tests bytes of the 2nd operand, verifying their status (X’00’ or not).
The 1st tested byte NOT in X’00’ ends the instruction execution.
1st operand indicates the 2nd operand bytes to be tested: TRT adds the contents of each byte of the 1st
operand to the 2nd operand address (same as TR instruction); the byte at the resulting address is tested
with X’00’.
When a non-X’00’ byte is detected instruction stores in the register 1 (bits 8-31; bits 0-7 remain
unchanged) the address of the 1st operand byte that lead to the 2nd operand non-X’00’ byte; it also
stores in register 2 (bits 24-31; bits 0-23 remain unchanged) the contents of the 2nd operand byte not
in X’00’.
This instruction is generally used to:
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Machine Instructions - TRT
TRT (TRanslate and Test)
Machine Instruction
Code
Condition code
Possible
Interruptions
DD (SS Instruction – L)
00 All bytes tested are with X'00'
01 Test ended before the last byte to be tested.
10 Test ended at the last byte to be tested, and
it wasn’t with X'00'
11 Condition code is not set as 11 after TRT
0005
a) Validate a decimal zoned field (1st operand – only valid digits):
TRT
CART+9(6),TABNUM
BZ
NUMÉRIC
.
.
.
TABNUM
DC
240X'FF',10X'00',6X'FF'
b) Validate an alphanumeric field (1st operand – only uppercase letters and spaces)
TRT
CART+9(6),TABALFAB
BZ
FABETIC
.
.
TABALFA
DC
CL256X'FF'
ORG
TABALFAB+C' '
DC
X'00'
ORG
TABALFAB+C'A'
DC
9X'00'
ORG
TABALFAB+C'J'
DC
9X'00'
ORG
TABALFAB+C'S'
DC
8X'00'
ORG
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374
Machine Instructions - TRT
TRT (TRanslate and Test)
Machine Instruction
Code
Condition code
Possible
Interruptions
DD (SS Instruction – L)
00 All bytes tested are with X'00'
01 Test ended before the last byte to be tested.
10 Test ended at the last byte to be tested, and
it wasn’t with X'00'
11 Condition code is not set as 11 after TRT
0005
c) Find a character (* in the example) in a string of characters (e.g. for parsing).
TABASTER
Summary
TRT
0(80,7),TABASTER
BZ
NOTASTER
register 1 has the byte with *
.
.
.
DC
256X'00'
ORG
TABASTER+C'*'
DC
X'FF'
ORG
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375
Machine Instructions - TS
TS (Test ans Set)
Machine Instruction
Code
93 (Instrução S)
Condition code
00
01
10
11
Possible
Interruptions
0004,0005
Leftmost bit OFF
Leftmost bit ON
Condition code is not set as 10 after TS
Condition code is not set as 11 after TS
Second byte of instruction is ignored.
The leftmost bit of the (only) operand is tested (ON or OFF).
After the test all bits of the byte are set to 1 (ON).
Condition code is set according to the result of the test.
Example:
TS
BYTE
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Machine Instructions - UNPK
UNPK (UNPacK)
Machine Instruction
Code
Condition code
F3 (SS Instruction – L1 e L2)
Possible
Interruptions
0004,0005
Remains unchanged
The UNPK instruction moves a storage packed field to a storage zoned field. The intended function
is to convert a numeric field from packed format to zoned format. NO validation is done in the
sending field; if its contents is not a valid decimal packed number, the operation flows normally.
1st operand is the receiving field and 2nd operand is the sending field. The operation is done from
right to left.
The two halves of the rightmost byte of the sending field are inverted and moved to the rightmost
byte of the receiving field.
After that, each half byte of the sending field is sent to a right half of a receiving field byte, and the
left half is set to X’F’. 2nd operand remains unchanged.
If the receiving field is smaller than needed to fit all digits from the sending field, the leftmost digits
are truncated.
If the receiving field is greater than needed to fit all digits from sending field, the remaining left
bytes are filled with X’F0’.
Example:
UNPK
FLDA,FLDB
Before
After
FLDB
12.34.5C
12.34.5C
FLDA
92.B8.4C.D0
F2.F3.F4.C5
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Machine Instructions - UNPK
UNPK (UNPacK)
Machine Instruction
Code
Condition code
F3 (SS Instruction – L1 e L2)
Possible
Interruptions
0004,0005
Remains unchanged
More examples:
UNPK
FLDB
FLDA
FLDA,FLDB
Before
12.3C
92.B8.4C.D0
UNPK
UNPK
UNPK
UNPK
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After
12.3C
F0.F1.F2.C3
WRITAREA+5(12),TOTLIQ
AX2,2(3,7)
17(10,8),T4B2F+3(5)
2(13,10),0(5,3)
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378
Machine Instructions - X
X ([boolean] eXclusive or Character)
Machine Instruction
Code
57 (RX Instruction)
Condition code
00
01
10
11
Possible
Interruptions
0005
Result = 0
Result <> 0
Condition code is not set as 10 after X
Condition code is not set as 11 after X
This instruction executes a boolean Exclusive OR between a register (1st operand) and a 4-byte
storage field (2nd operand).
Mask bit =0 then result bit = remains unchanged; mask bit = 1 then
reault bit = inverted
Example:
X
13,FIELDF
Before
Register 13 B4.EF.2F.A8
FIELDF
00.00.00.FF
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B4.EF.2F.57
00.00.00.FF
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Machine Instructions - XC
XC ([boolean] eXclusive or Character)
Machine Instruction
Code
D7 (SS Instruction – L)
Condition code
00
01
10
11
Possible
Interruptions
0004, 0005
Result = 0
Result <> 0
Condition code is not set as 10 after XC
Condition code is not set as 11 after XC
This instruction executes a boolean EXCLUSIVE OR between 2 storage fields (1st and 2nd
operands).
Mask bit =0 then result bit = remains unchanged; mask bit = 1 then
reault bit = inverted
Example:
XC
FLDA,FLDB
FLDA
FLDB
Summary
Before
EF.2F.A8
00.00.00
After
EF.2F.57
00.00.FF
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Machine Instructions - XI
XI ([boolean] eXclusive or [with] Immediate [operand])
Machine Instruction
Code
97 (SI Instruction)
Condition code
00
01
10
11
Possible
Interruptions
0004, 0005
Result = 0
Result <> 0
Condition code is not set as 10 after OI
Condition code is not set as 11 after OI
This instruction executes a boolean EXCLUSIVE OR between 2 storage fields (1 byte each; 1st
operand = field specified using its address; 2nd operand = immediate field, it’s the 2nd byte of the
instruction).
Mask bit =0 then result bit = remains unchanged; mask bit = 1 then
reault bit = inverted
Example:
NI
BYE,X’0F’
before
BYTE
B4
Immediate operand 0F
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BB
0F
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Machine Instructions - XR
XR ([boolean] eXclusive or Register)
Machine Instruction
Code
17 (RR Instruction)
Condition code
00
01
10
11
Possible
Interruptions
No interruptions occur
Result = 0
Result <> 0
Condition code is not set as 10 after XR
Condition code is not set as 11 after XR
This instruction executes a boolean EXCLUSIVE OR between 2 registers.
Mask bit =0 then result bit = remains unchanged; mask bit = 1 then
reault bit = inverted
Example:
XR
5,8
Register 5
Register 8
Summary
Before
B4.EF.2F.A8
00.00.00.FF
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After
B4.EF.2F.57
00.00.00.FF
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382
Machine Instructions - ZAP
ZAP (Zero and Add Packed)
Machine Instruction
Code
F8 (SS Instruction – L1 e L2)
Condition code
00
01
10
11
Possible
Interruptions
0001,0004,0005,0007,000A
Sender field = 0
Sender field < 0
Sender field > 0
Overflow
2nd operand must be a packeddecimal storage field.
This instruction zeroes (decimal packed zero) the 1st operand and add the value of the 2st operand to
the 1st. 2nd operand remains unchanged.
Note that this process is done internally (in the CPU).
That’s the reason one can specify the same storage field as 1st and also as 2nd operand; this is often
used to test the number (positive, negative or zero) because ZAP sets the condition code
When we do
ZAP FLD,FLD
before zeroing FLD, its contents are internally saved. After being zeroed, when add is done the
original contents is available; then it returns to the original value.
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Machine Instructions - ZAP
ZAP (Zero and Add Packed)
Machine Instruction
Code
F8 (SS Instruction – L1 e L2)
Condition code
00
01
10
11
Possible
Interruptions
0001,0004,0005,0007,000A
ZAP
Se o campo movido = 0
Se o campo movido < 0
Se o campo movido > 0
Overflow
CPOA,CPOB
Before
After
1st Case
CPOB
CPOA
12.34.5C
B4.F8
12.34.5C
34.5C
CPOB
CPOA
12.3C
07.B8.92
12.3C
00.12.3C
2nd Case
More examples:
ZAP
ZAP
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TOTAL,=P'0'
CONTLIN,=P'2'
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Macro Instructions
MACRO INSTRUCTIONS
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385
Macro Instructions
MACRO INSTRUCTIONS
Sorry... It’s not in the scope of this course...
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Appendix - Links
LINKS
z/Architecture
http://publibz.boulder.ibm.com/epubs/pdf/dz9zr006.pdf
ESA Enterprise Systems Architecture / XC Extended Configuration (para z/VM)
http://publib.boulder.ibm.com/infocenter/zvm/v5r3/index.jsp?topic=/com.ibm.zvm.v53.hcpb6/abstract.htm
High Level Assembler
http://publib.boulder.ibm.com/infocenter/ratdevz/v7r5/topic/com.ibm.ent.asm.zos.doc/topics/fn1lrmst02.htm#wq2
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387
Appendix – Instructions by operation code
Some instructions (ordered by operation code)
Mnemonic
BALR
BCTR
BCR
SVC
BSM
BASSM
BASR
MVCL
CLCL
LPR
LNR
LTR
LCR
NR
CLR
OR
XR
LR
CR
AR
Code
05
06
07
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
Type
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
RR
Mnemonic
SR
MR
DR
ALR
SLR
STH
LA
STC
IC
EX
BAL
BCT
BC
LH
CH
AH
SH
MH
BAS
CVD
Code
1B
1C
1D
1E
1F
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
Type Mnemonic
RR
CVB
RR
ST
RR
LAE
RR
N
RR
CL
RX
O
RX
X
RX
L
RX
C
RX
A
RX
S
RX
M
RX
D
RX
AL
RX
SL
RX
STD
RX
MXD
RX
LD
RX
CD
RX
AD
Code
4F
50
51
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
67
68
69
6A
Type
RX
RX
RX
RX
RX
RX
RX
RX
RX
RX
RX
RX
RX
RX
RX
RX
RX
RX
RX
RX
Continues...
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388
Appendix – Instructions by operation code
Some instructions (ordered by operation code)
Mnemonic
SD
MD
DD
AW
SW
STE
LE
CE
BXH
BXLE
SRL
SLL
SRA
SLA
SRDL
SLDL
SRDA
SLDA
STM
TM
Code
6B
6C
6D
6E
6F
70
78
79
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
Summary
Type Mnemonic
RX
MVI
RX
TS
RX
NI
RX
CLI
RX
OI
RX
XI
RX
LM
RX
MC
RS
LRA
RS
STCK
RS
CS
RS
CDS
RS
CLM
RS
STCM
RS
ICM
RS
MVN
RS
MVC
RS
MVZ
RS
NC
SI
CLC
Prev.Page
Code
92
93
94
95
96
97
98
AF
B1
B205
BA
BB
BD
BE
BF
D1
D2
D3
D4
D5
Type
SI
S
SI
SI
SI
SI
RS
SI
RX
S
RS
RS
RS
RS
RS
SS/L
SS/L
SS/L
SS/L
SS/L
Mnemonic
OC
XC
TR
TRT
ED
EDMK
MVCIN
SRP
MVO
PACK
UNPK
ZAP
CP
AP
SP
MP
DP
Code
D6
D7
DC
DD
DE
DF
E8
F0
F1
F2
F3
F8
F9
FA
FB
FC
FD
Type
SS/L
SS/L
SS/L
SS/L
SS/L
SS/L
SS/L
SS/L1I3
SS/L1L2
SS/L1L2
SS/L1L2
SS/L1L2
SS/L1L2
SS/L1L2
SS/L1L2
SS/L1L2
SS/L1L2
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389
Appendix – Instructions by mnemonic
Some instructions (ordered by mnemonic)
Mnemonic
A
AD
AH
AL
ALR
AP
AR
AW
BAL
BALR
BAS
BASR
BASSM
BC
BCR
BCT
BCTR
BSM
BXH
BXLE
Code
5A
6A
4A
5E
1E
FA
1A
6E
45
05
4D
0D
0C
47
07
46
06
0B
86
87
Type
RX
RX
RX
RX
RR
SS/L1L2
RR
RX
RX
RR
RX
RR
RR
RX
RR
RX
RR
RR
RS
RS
Mnemonic
C
CD
CDS
CE
CH
CL
CLC
CLCL
CLI
CLM
CLR
CP
CR
CS
CVB
CVD
D
DD
DP
DR
Code
59
69
BB
79
49
55
D5
0F
95
BD
15
F9
19
BA
4F
4E
5D
6D
FD
1D
Type
RX
RX
RS
RX
RX
RX
SS/L
RR
SI
RS
RR
SS/L1L2
RR
RS
RX
RX
RX
RX
SS/L1L2
RR
Mnemonic
ED
EDMK
EX
IC
ICM
L
LA
LAE
LCR
LD
LE
LH
LM
LNR
LPR
LR
LRA
LTR
M
MC
Code
DE
DF
44
43
BF
58
41
51
13
68
78
48
98
11
10
18
B1
12
5C
AF
Type
SS/L
SS/L
RX
RX
RS
RX
RX
RX
RR
RX
RX
RX
RS
RR
RR
RR
RX
RR
RX
SI
Continues...
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390
Appendix – Instructions by mnemonic
Some instructions (ordered by mnemonic)
Mnemonic
MD
MH
MP
MR
MVC
MVCIN
MVCL
MVI
MVN
MVO
MVZ
MXD
N
NC
NI
NR
O
OC
OI
OR
Code
6C
4C
FC
1C
D2
E8
0E
92
D1
F1
D3
67
54
D4
94
14
56
D6
96
16
Summary
Type
RX
RX
SS/L1L2
RR
SS/L
SS/L
RR
SI
SS/L
SS/L1L2
SS/L
RX
RX
SS/L
SI
RR
RX
SS/L
SI
RR
Prev.Page
Mnemonic
PACK
S
SD
SH
SL
SLA
SLDA
SLDL
SLL
SLR
SP
SR
SRA
SRDA
SRDL
SRL
SRP
ST
STC
STCK
Code
F2
5B
6B
4B
5F
8B
8F
8D
89
1F
FB
1B
8A
8E
8C
88
F0
50
42
B205
Type
SS/L1L2
RX
RX
RX
RX
RS
RS
RS
RS
RR
SS/L1L2
RR
RS
RS
RS
RS
SS/L1I3
RX
RX
S
Mnemonic
STCM
STD
STE
STH
STM
SVC
SW
TM
TR
TRT
TS
UNPK
X
XC
XI
XR
ZAP
Code
BE
60
70
40
90
0A
6F
91
DC
DD
93
F3
57
D7
97
17
F8
Type
RS
RX
RX
RX
RS
RR
RX
SI
SS/L
SS/L
S
SS/L1L2
RX
SS/L
SI
RR
SS/L1L2
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391
Appendix – EBCDIC - Some characters
Some EBCDIC configurations
HEX
CARATER
40
Space
60
- hiphen
81
a
A2
s
D0
} Right brace
F0
0
4B
. point
61
/ slash
82
b
A3
t
D1
J
F1
1
4C
< less than
6B
, comma
83
c
A4
u
D2
K
F2
2
4D
( Left parenheses
6C
% percent
84
d
A5
v
D3
L
F3
3
4E
+ Plus sign
6D
_ underscore
85
e
A6
w
D4
M
F4
4
4F
| Vertical bar
6E
> Greater than
86
f
A7
x
D5
N
F5
5
50
& Ampersand
6F
? Question mark
87
g
A8
y
D6
O
F6
6
5A
! Exclamation mark
7A
: colon
88
h
A9
z
D7
P
F7
7
5B
$ Dollar sign
7B
# number sign
91
i
C0
{ Left brace
D8
Q
F8
8
5C
* Asterisk
7C
@ at
92
j
C1
A
D9
R
F9
9
5D
) Right parentheses
7D
' apostrophe
93
k
C2
B
E0
\ Backslash
5E
; Semicolon
7E
= equals
94
l
C3
C
E2
S
5F

7F
" quotes
95
m
C4
D
E3
T
96
n
C5
E
E4
U
97
o
C6
F
E5
V
98
p
C7
G
E6
W
99
q
C8
H
E7
X
9A
r
C9
I
E8
Y
E9
Z
Not
Summary
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392
Appendix – ASCII - Some characters
Some ASCII configurations
HEX
CARATER
20
Space
30
0 zero
40
21
31
1 one
22
! exclamation
mark
“ quotes
32
23
# number
24
50
P
60
` grave accent
70
p
41
@
at
A
51
Q
61
a
71
q
2 two
42
B
52
R
62
b
72
r
33
3 three
43
C
53
S
63
c
73
s
$ dollar sign
34
4 four
44
D
54
T
64
d
74
t
25
% percent sign
35
5 five
45
E
55
U
65
e
75
u
26
& ampersand
36
6 six
46
F
56
V
66
f
76
v
27
‘ apostrophe
37
7 seven
47
G
57
W
67
g
77
w
28
( Left parentheses
38
8 eight
48
H
58
X
68
h
78
x
29
39
9 nine
49
I
59
Y
69
i
79
y
2A
) Right
parentheses
* asterisk
3A
: colon
4A
J
5A
Z
6A
j
7A
z
2B
+ plus sign
3B
; semicolon
4B
K
5B
[ Left bracket
6B
k
7B
{ Left brace
2C
, comma
3C
< less than
4C
L
5C
\ back slash
6C
l
7C
| Vertical Slash
2D
- hyphen
3D
= equals
4D
M
5D
] Right bracket
6D
m
7D
} Right brace
2E
. point
3E
> greater
4E
N
5E
^ circumflex
6E
n
7E
~ tilde
2F
/ slash
3F
? question mark
4F
O
5F
_
6F
o
Summary
Prev.Page
(underscore)
Alberto Romano Schiesari – www.profars.com
393
Questions
Questions
Summary
Prev.Page
Alberto Romano Schiesari – www.profars.com
394
(Q) Exercises 1-12 (Convert decimal to binary)
Exercise 1 : (987654)10 = (?)2
Exercise 2 : (4095)10 = (?)2
Exercise 3 : (7)10 = (?)2
Exercise 4 : (1023)10 = (?)2
Exercise 5 : (4096)10 = (?)2
Exercise 6 : (255)10 = (?)2
Exercise 7 : (1024)10 = (?)2
Exercise 8 : (10010001)10 = (?)2
Exercise 9 : (256)10 = (?)2
Exercise 10 : (1025)10 = (?)2
Exercise 11 : (999888)10 = (?)2
Exercise 12 : (65432)10 = (?)2
Summary
Prev.Page
Alberto Romano Schiesari – www.profars.com
395
(Q) Exercises 13-24 (Convert decimal to hexadecimal)
Exercise 13 : (987654)10 = (?)16
Exercise 14 : (4095)10 = (?)16
Exercise 15 : (7)10 = (?)16
Exercise 16 : (1023)10 = (?)16
Exercise 17 : (4096)10 = (?)16
Exercise 18 : (255)10 = (?)16
Exercise 19 : (1024)10 = (?)16
Exercise 20 : (10010001)10 = (?)16
Exercise 21 : (256)10 = (?)16
Exercise 22 : (1025)10 = (?)16
Exercise 23 : (999888)10 = (?)16
Exercise 24 : (65432)10 = (?)16
Summary
Prev.Page
Alberto Romano Schiesari – www.profars.com
396
(Q) Exercises 25-36 (Convert binary to hexadecimal)
Exercise 25 : (11111000111010100100001 )2 = (?)16
Exercise 26 : (1000000111000111111110000011111110)2 = (?)16
Exercise 27 : (1100)2 = (?)16
Exercise 28 : (11111110001)2 = (?)16
Exercise 29 : (1010101010101000110011000111)2 = (?)16
Exercise 30 : (110011001100110011001)2 = (?)16
Exercise 31 : (1000000000000001)2 = (?)16
Exercise 32 : (1000000001)2 = (?)16
Exercise 33 : (111111100000001111111)2 = (?)16
Exercise 34 : (1)2 = (?)16
Exercise 35 : (1100101011111110)2 = (?)16
Exercise 36 : (101011010111000111000000001111110001111)2 = (?)16
Summary
Prev.Page
Alberto Romano Schiesari – www.profars.com
397
(Q) Exercises 37-48 (Convert hexadecimal to binary)
Exercise 37 : (CAFE)16 = (?)2
Exercise 38 : (CDF)16 = (?)2
Exercise 39 : (1AB4D)16 = (?)2
Exercise 40 : (15)16 = (?)2
Exercise 41 : (F)16 = (?)2
Exercise 42 : (87B54)16 = (?)2
Exercise 43 : (1001)16 = (?)2
Exercise 44 : (234)16 = (?)2
Exercise 45 : (CAD)16 = (?)2
Exercise 46 : (7F7)16 = (?)2
Exercise 47 : (1990)16 = (?)2
Exercise 48 : (33)16 = (?)2
Summary
Prev.Page
Alberto Romano Schiesari – www.profars.com
398
(Q) Exercises 49-60 (Convert binary to decimal)
Exercise 49 : (11)2 = (?)10
Exercise 50 : (100001111111)2 = (?)10
Exercise 51 : (101010010101)2 = (?)10
Exercise 52 : (110000001111111)2 = (?)10
Exercise 53 : (11111110000011)2 = (?)10
Exercise 54 : (11110000111000)2 = (?)10
Exercise 55 : (11)2 = (?)10
Exercise 56 : (111111110)2 = (?)10
Exercise 57 : (1111100001111000111001101)2 = (?)10
Exercise 58 : (1000000000000)2 = (?)10
Exercise 59 : (11111001)2 = (?)10
Exercise 60 : (1000000000000001)2 = (?)10
Summary
Prev.Page
Alberto Romano Schiesari – www.profars.com
399
(Q) Exercises 61-72 (Convert hexadecimal to decimal)
Exercise 61 : (11)16 = (?)10
Exercise 62 : (AAF45)16 = (?)10
Exercise 63 : (1B567)16 = (?)10
Exercise 64 : (100)16 = (?)10
Exercise 65 : (1000)16 = (?)10
Exercise 66 : (FF)16 = (?)10
Exercise 67 : (FFF)16 = (?)10
Exercise 68 : (CDF)16 = (?)10
Exercise 69 : (CAFE)16 = (?)10
Exercise 70 : (FACA)16 = (?)10
Exercise 71 : (DAD0)16 = (?)10
Exercise 72 : (F1E2D3C4)16 = (?)10
Summary
Prev.Page
Alberto Romano Schiesari – www.profars.com
400
(Q) Exercises 73-84 (Add numbers in binary)
Exercise 73 : (11001100)2 + (10101010)2 = (?)2
Exercise 74 : (1111001111)2 + (1001111001)2 = (?)2
Exercise 75 : (1111)2 + (1)2 = (?)2
Exercise 76 : (1111)2 + (111)2 = (?)2
Exercise 77 : (100001)2 + (11110)2 = (?)2
Exercise 78 : (1011110011)2 + (111101111)2 = (?)2
Exercise 79 : (110011001100)2 + (101011110000)2 = (?)2
Exercise 80 : (1111100001111000)2 + (101111)2 = (?)2
Exercise 81 : (111)2 + (1111)2 + (100)2 = (?)2
Exercise 82 : (11)2 + (111)2 + (1111)2 + (11111)2 = (?)2
Exercise 83 : (1111)2 + (1001)2 + (111)2 + (101)2 + (11)2 + (1)2 = (?)2
Exercise 84 : (111)2 + (1000)2 + (1)2 + (1100)2 = (?)2
Summary
Prev.Page
Alberto Romano Schiesari – www.profars.com
401
(Q) Exercises 85-96 (Subtract numbers in binary)
Exercise 85 : (11001100)2 - (1010101)2 = (?)2
Exercise 86 : (1111001111)2 - (1111001)2 = (?)2
Exercise 87 : (1111)2 - (1)2 = (?)2
Exercise 88 : (1111)2 - (111)2 = (?)2
Exercise 89 : (100001)2 - (11110)2 = (?)2
Exercise 90 : (1011110011)2 - (111101111)2 = (?)2
Exercise 91 : (11001100)2 - (111011110000)2 = (?)2
Exercise 92 : (1111000)2 - (101010111)2 = (?)2
Exercise 93 : (111)2 - (1111)2 = (?)2
Exercise 94 : (10001)2 - (111111)2 = (?)2
Exercise 95 : (0)2 - (1)2 = (?)2
Exercise 96 : (0)2 - (10)2 = (?)2
Summary
Prev.Page
Alberto Romano Schiesari – www.profars.com
402
(Q) Exercises 97-108 (Add numbers in hexadecimal)
Exercise 97 : (F12B)16 + (321)16 = (?)16
Exercise 98 : (1100)16 + (111)2 = (?)16
Exercise 99 : (1000F)16 + (F0001)16 = (?)16
Exercise 100 : (A9B8C7)16 + (D6E5F4)16 = (?)16
Exercise 101 : (CAFE)16 + (CDF)16 = (?)16
Exercise 102 : (B001)16 + (FD)16 = (?)16
Exercise 103 : (999)16 + (111)16 = (?)16
Exercise 104 : (123456)16 + (789ABC)16 = (?)16
Exercise 105 : (FFF)16 + (EEE)16 = (?)16
Exercise 106 : (DDD)16 + (333)16 = (?)16
Exercise 107 : (987AED)16 + (CF01)16 = (?)16
Exercise 108 : (FACA)16 + (CAFE)16 = (?)16
Summary
Prev.Page
Alberto Romano Schiesari – www.profars.com
403
(Q) Exercises 109-120 (Subtract numbers in hexadecimal)
Exercise 109 : (F1C5)16 - (101)16 = (?)16
Exercise 110 : (1AD87C)16 - (FDE9)2 = (?)16
Exercise 111 : (112233)16 - (44556)16 = (?)16
Exercise 112 : (AABBCC)16 - (DDEEF)16 = (?)16
Exercise 113 : (F1E2D3)16 - (C4B5A6)16 = (?)16
Exercise 114 : (FF00001)16 - (10000F)16 = (?)16
Exercise 115 : (CAFE)16 - (FACA)16 = (?)16
Exercise 116 : (CDF)16 - (FDC)16 = (?)16
Exercise 117 : (10001)16 - (20001)16 = (?)16
Exercise 118 : (10000)16 - (FFFE)16 = (?)16
Exercise 119 : (0)16 - (9)16 = (?)16
Exercise 120 : (0)16 - (1A)16 = (?)16
Summary
Prev.Page
Alberto Romano Schiesari – www.profars.com
404
(Q) Exercises 121-126 (Representing binary numbers in bytes)
Exercise 121 : (1)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16
= (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb)2 = (xxxxxxxx)16
Exercise 122 : (-1)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16
= (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb)2 = (xxxxxxxx)16
Exercise 123 : (10)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16
= (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb)2 = (xxxxxxxx)16
Exercise 124 : (-10)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16
= (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb)2 = (xxxxxxxx)16
Exercise 125 : (17)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16
= (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb)2 = (xxxxxxxx)16
Exercise 126 : (-17)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16
= (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb)2 = (xxxxxxxx)16
Summary
Prev.Page
Alberto Romano Schiesari – www.profars.com
405
(Q) Exercises 127-132 (Representing binary numbers in bytes)
Exercise 127 : (254)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16
= (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb)2 = (xxxxxxxx)16
Exercise 128 : (-254)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16
= (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb)2 = (xxxxxxxx)16
Exercise 129 : (100000)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16
= (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb)2 = (xxxxxxxx)16
Exercise 130 : (-100000)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16
= (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb)2 = (xxxxxxxx)16
Exercise 131 : (32000)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16
= (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb)2 = (xxxxxxxx)16
Exercise 132 : (-32000)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16
= (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb)2 = (xxxxxxxx)16
Summary
Prev.Page
Alberto Romano Schiesari – www.profars.com
406
(Q) Exercises 133-138 (Representing binary numbers in bytes)
Exercise 133 : (63000)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16
= (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb)2 = (xxxxxxxx)16
Exercise 134 : (-63000)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16
= (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb)2 = (xxxxxxxx)16
Exercise 135 : (1010)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16
= (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb)2 = (xxxxxxxx)16
Exercise 136 : (-1010)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16
= (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb)2 = (xxxxxxxx)16
Exercise 137 : (4095)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16
= (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb)2 = (xxxxxxxx)16
Exercise 138 : (-4095)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16
= (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb)2 = (xxxxxxxx)16
Summary
Prev.Page
Alberto Romano Schiesari – www.profars.com
407
(Q) Exercises 139-140 (Representing binary numbers in bytes)
Exercise 139 : (4097)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16
= (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb)2 = (xxxxxxxx)16
Exercise 140 : (-4097)10 = (bbbb bbbb bbbb bbbb)2 = (xxxx)16
= (bbbb bbbb bbbb bbbb bbbb bbbb bbbb bbbb)2 = (xxxxxxxx)16
Summary
Prev.Page
Alberto Romano Schiesari – www.profars.com
408
(Q) Exercises 141-152 (Representing packed numbers in bytes)
Exercise 141 : (1)10 = (in decimal-packed format)
Exercise 142 : (-1)10 = (in decimal-packed format)
Exercise 143 : (10)10 = (in decimal-packed format)
Exercise 144 : (-10)10 = (in decimal-packed format)
Exercise 145 : (17)10 = (in decimal-packed format)
Exercise 146 : (-17)10 = (in decimal-packed format)
Exercise 147 : (254)10 = (in decimal-packed format)
Exercise 148 : (-254)10 = (in decimal-packed format)
Exercise 149 : (100000)10 = (in decimal-packed format)
Exercise 150 : (-100000)10 = (in decimal-packed format)
Exercise 151 : (32000)10 = (in decimal-packed format)
Exercise 152 : (-32000)10 = (in decimal-packed format)
Summary
Prev.Page
Alberto Romano Schiesari – www.profars.com
409
(Q) Exercises 153-160 (Representing packed numbers in bytes)
Exercise 153 : (63000)10 = (in decimal-packed format)
Exercise 154 : (-63000)10 = (in decimal-packed format)
Exercise 155 : (1010)10 = (in decimal-packed format)
Exercise 156 : (-1010)10 = (in decimal-packed format)
Exercise 157 : (4095)10 = (in decimal-packed format)
Exercise 158 : (-4095)10 = (in decimal-packed format)
Exercise 159 : (4097)10 = (in decimal-packed format)
Exercise 160 : (-4097)10 = (in decimal-packed format)
Summary
Prev.Page
Alberto Romano Schiesari – www.profars.com
410
(Q) Exercises 161-172 (Representing zoned numbers in bytes)
Exercise 161 : (1)10 = (in decimal-zoned format)
Exercise 162 : (-1)10 = (in decimal-zoned format)
Exercise 163 : (10)10 = (in decimal-zoned format)
Exercise 164 : (-10)10 = (in decimal-zoned format)
Exercise 165 : (17)10 = (in decimal-zoned format)
Exercise 166 : (-17)10 = (in decimal-zoned format)
Exercise 167 : (254)10 = (in decimal-zoned format)
Exercise 168 : (-254)10 = (in decimal-zoned format)
Exercise 169 : (100000)10 = (in decimal-zoned format)
Exercise 170 : (-100000)10 = (in decimal-zoned format)
Exercise 171 : (32000)10 = (in decimal-zoned format)
Exercise 172 : (-32000)10 = (in decimal-zoned format)
Summary
Prev.Page
Alberto Romano Schiesari – www.profars.com
411
(Q) Exercises 173-180 (Representing zoned numbers in bytes)
Exercise 173 : (63000)10 = (in decimal-zoned format)
Exercise 174 : (-63000)10 = (in decimal-zoned format)
Exercise 175 : (1010)10 = (in decimal-zoned format)
Exercise 176 : (-1010)10 = (in decimal-zoned format)
Exercise 177 : (4095)10 = (in decimal-zoned format)
Exercise 178 : (-4095)10 = (in decimal-zoned format)
Exercise 179 : (4097)10 = (in decimal-zoned format)
Exercise 180 : (-4097)10 = (in decimal-zoned format)
Summary
Prev.Page
Alberto Romano Schiesari – www.profars.com
412
(Q) Exercises 181-194 (Representing character strings in bytes)
Exercise 181 : “17“ = (in alphanumeric EBCDIC)
Exercise 182 : “-17“ = (in alphanumeric EBCDIC)
Exercise 183 : “AF$BD“ = (in alphanumeric EBCDIC)
Exercise 184 : “-AF4BD“ = (in alphanumeric EBCDIC)
Exercise 185 : “ALBERTO“ = (in alphanumeric EBCDIC)
Exercise 186 : “15-9“ = (in alphanumeric EBCDIC)
Exercise 187 : “-4095“ = (in alphanumeric EBCDIC)
Exercise 188 : “4095“ = (in alphanumeric EBCDIC)
Exercise 189 : “*&$//“ = (in alphanumeric EBCDIC)
Exercise 190 : “12+3“ = (in alphanumeric EBCDIC)
Exercise 191 : “I LOVE HER“ = (in alphanumeric EBCDIC)
Exercise 192 : “US$ 2,584.73“ = (in alphanumeric EBCDIC)
Exercise 193 : “US$ 1 MILLION“ = (in alphanumeric EBCDIC)
Exercise 194 : “PANCHO’S BAR“ = (in alphanumeric EBCDIC)
Summary
Prev.Page
Alberto Romano Schiesari – www.profars.com
413
(Q) Exercises 195-209 (Representing fields in bytes)
Exercises 195-300 must be considered as a program starting at address X’00000000’, that is, first area
(exercise 195) begins at address zero. The DS defined areas must be computed to determine the
addresses. Assume the 1st statement of the program is USING *,9.
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
195:
196:
197:
198:
199:
200:
201:
202:
203:
204:
205:
206:
207:
208:
209:
Summary
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
Prev.Page
C'123'
C'+123'
C'-123'
C'12.3'
C'1AB8'
C'01101'
C'A+B=C'
CL4'A'
CL4'ABCDEF'
3CL2'A'
2CL3'A,B'
C'ME&&YOU'
C'''S MUSIC'
C'@@OI'
CL3'*'
Alberto Romano Schiesari – www.profars.com
414
(Q) Exercises 210-225 (Representing fields in bytes)
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
210:
211:
212:
213:
214:
215:
216:
217:
218:
219:
220:
221:
222:
223:
224:
225:
Summary
Prev.Page
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
3C'*'
X'123'
X'-123'
X'1AB2C3'
X'1AB2F4G3'
XL3'12D'
XL3'AABBCCDDEE'
X'1,22,333,4444'
XL2'1,22,333'
2X'1,22,333'
2XL2'1,22'
B'01010101'
B'1'
BL2'1111'
B'1,1111111111'
BL2'1,1111111111'
Alberto Romano Schiesari – www.profars.com
415
(Q) Exercises 226-239 (Representing fields in bytes)
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
226:
227:
228:
229:
230:
230:
231:
232:
233:
234:
235:
236:
237:
238:
239:
Summary
Prev.Page
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
2B'1000'
2BL2'1000'
F'10'
F'+10'
F'-10'
F'-15,+16'
2F'22'
2F'33,44'
FL3'258'
2FL1'255'
F'128000'
H'10'
H'+10'
H'-10'
H'-15,+16'
Alberto Romano Schiesari – www.profars.com
416
(Q) Exercises 240-254 (Representing fields in bytes)
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
240:
241:
242:
243:
244:
245:
246:
247:
248:
249:
250:
251:
252:
253:
254:
Summary
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
Prev.Page
2H'22'
2H'33,44'
HL3'258'
2HL1'255'
H'128000'
P'123'
P'+123'
P'-123'
PL4'456'
PL1'789'
P'1,-22,333,-4444'
PL2'1,-22,333,-4444'
3P'0'
PL3'0'
2P'1,22,333'
Alberto Romano Schiesari – www.profars.com
417
(Q) Exercises 255-266 (Representing fields in bytes)
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
255:
256:
257:
258:
259:
260:
261:
262:
263:
264:
265:
266:
Summary
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
Prev.Page
2PL2'1,22,333'
Z'123'
Z'+123'
Z'-123'
ZL4'456'
ZL1'789'
Z'1,-22,333,-4444'
ZL3'1,-22,333,-4444'
3Z'0'
ZL3'0'
2Z'1,22,333'
2ZL3'1,22,333'
Alberto Romano Schiesari – www.profars.com
418
(Q) Exercises 267-279 (Representing fields in bytes)
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
267:
268:
269:
270:
271:
272:
273:
274:
275:
276:
277:
278:
279:
Summary
SIMBZZ
SIMBAA
SIMBBB
SIMBCC
SIMBDD
SIMBEE
SIMBFF
SIMBGG
SIMBHH
SIMBII
SIMBJJ
SIMBKK
SIMBLL
Prev.Page
DC
DC
DC
DC
DC
DC
DS
DC
DC
DC
DC
DC
DC
A(0)
A(127)
A(X'8000')
A(B'1111')
A(C'*')
A(*)
CL17
A(*)
A(SIMBGG)
A(SIMBAA+12)
A(SIMBII-SIMBBB)
AL1(*-SIMBKK)
5AL1(*-SIMBLL)
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419
(Q) Exercises 280-290 (Representing fields in bytes)
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
280:
281:
282:
283:
284:
285:
286:
287:
288:
289:
290:
Summary
SIMBMM
SIMBNN
SIMBOO
SIMBPP
SIMBQQ
SIMBRR
SIMBSS
SIMBTT
SIMBUU
SIMBVV
SIMBWW
Prev.Page
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
AL2(3,5,7)
A(SIMBII+5*2)
A(SIMBNN+X'80000000')
4AL2(*-SIMBPP)
A(SIMBVV)
A(SIMBKK,SIMBJJ)
A(SIMBTT+40)
A(SIMBUU,*,80)
2A(*-SIMBUU)
A(C'AMO')
A(X'7FFFFFFF')
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420
(Q) Exercises 291-300 (Representing fields in bytes)
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
291:
292:
293:
294:
295:
296:
297:
298:
299:
300:
Summary
YY1
YY2
YY3
SS1
SS2
SS3
SS4
SS5
SS6
LAST
Prev.Page
DC Y(SIMBWW)
DC Y(10)
DC Y(L'YY2)
DC S(SIMBAA)
DC S(SS1)
DC S(10)
DC S(*)
DC A(125),F'33',C'*',2H'6,18'
DC X'1,1',B'1,1',C'1,1'
DC 256AL1(255+LAST-*)
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421
(Q) Exercise 301 (Decoding instructions)
Exercise 301 : Decode the following set of instructions; for each one, specify:
- Operation code (machine code)
- Menmonic Assembler code
- Instruction address (suppose 1st instruction at address X’00000000’)
- Operands (register, base register, index register, displacement; if operand is in storage,
compute the operand address; to compute the operand’s addresses suppose the general
registers with the following contents:
R00=00112233
R01=00000100
R02=00000200
R03=00000300
R04=00000400
R05=00000500
R06=00000600
R07=00000700
R08=00000800
R09=00000900
R10=00000A00
R11=00000B00
R12=00000C00
R13=00000D00
R14=00000E00
R15=00000F00
Instructions to decode:
1ABB41278CF00A13980F334445E00CB490EC0D00FA82305448CCD28233445566
Summary
Prev.Page
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422
Answers
Answers
Summary
Prev.Page
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423
(A) Exercises 1-12 (Convert decimal to binary)
Exercise 1 : (987654)10 = (1111 0001 0010 0000 0110)2
Exercise 2 : (4095)10 = (1111 1111 1111)2
Exercise 3 : (7)10 = (111)2
Exercise 4 : (1023)10 = (11 1111 1111)2
Exercise 5 : (4096)10 = (1 0000 0000 0000)2
Exercise 6 : (255)10 = (1111 1111)2
Exercise 7 : (1024)10 = (100 0000 0000)2
Exercise 8 : (10010001)10 = (1001 1000 1011 1101 1001 0001)2
Exercise 9 : (256)10 = (1 0000 0000)2
Exercise 10 : (1025)10 = (100 0000 0001)2
Exercise 11 : (999888)10 = (1111 0100 0001 1101 0000)2
Exercise 12 : (65432)10 = (1111 1111 1001 1000)2
Summary
Prev.Page
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424
(A) Exercises 13-24 (Convert decimal to hexadecimal)
Exercise 13 : (987654)10 = (F1206)16
Exercise 14 : (4095)10 = (FFF)16
Exercise 15 : (7)10 = (7)16
Exercise 16 : (1023)10 = (3FF)16
Exercise 17 : (4096)10 = (1000)16
Exercise 18 : (255)10 = (FF)16
Exercise 19 : (1024)10 = (400)16
Exercise 20 : (10010001)10 = (98BD91)16
Exercise 21 : (256)10 = (100)16
Exercise 22 : (1025)10 = (401)16
Exercise 23 : (999888)10 = (F41D0)16
Exercise 24 : (65432)10 = (FF98)16
Summary
Prev.Page
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425
(A) Exercises 25-36 (Convert binary to hexadecimal)
Exercise 25 : (11111000111010100100001 )2 = (7C7521)16
Exercise 26 : (1000000111000111111110000011111110)2 = (2071FE0FE)16
Exercise 27 : (1100)2 = (C)16
Exercise 28 : (11111110001)2 = (7F1)16
Exercise 29 : (1010101010101000110011000111)2 = (AAA8CC7)16
Exercise 30 : (110011001100110011001)2 = (199999)16
Exercise 31 : (1000000000000001)2 = (8001)16
Exercise 32 : (1000000001)2 = (201)16
Exercise 33 : (111111100000001111111)2 = (1FC07F)16
Exercise 34 : (1)2 = (1)16
Exercise 35 : (1100101011111110)2 = (CAFE)16
Exercise 36 : (101011010111000111000000001111110001111)2 = (56B8E01F8F)16
Summary
Prev.Page
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426
(A) Exercises 37-48 (Convert hexadecimal to binary)
Exercise 37 : (CAFE)16 = (1100101011111110)2
Exercise 38 : (CDF)16 = (110011011111)2
Exercise 39 : (1AB4D)16 = (11010101101001101)2
Exercise 40 : (15)16 = (10101)2
Exercise 41 : (F)16 = (1111)2
Exercise 42 : (87B54)16 = (10000111101101010100)2
Exercise 43 : (1001)16 = (1000000000001)2
Exercise 44 : (234)16 = (1000110100)2
Exercise 45 : (CAD)16 = (110010101101)2
Exercise 46 : (7F7)16 = (11111110111)2
Exercise 47 : (1990)16 = (1100110010000)2
Exercise 48 : (33)16 = (110011)2
Summary
Prev.Page
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427
(A) Exercises 49-60 (Convert binary to decimal)
Exercise 49 : (11)2 = (3)10
Exercise 50 : (100001111111)2 = (2175)10
Exercise 51 : (101010010101)2 = (2709)10
Exercise 52 : (110000001111111)2 = (24703)10
Exercise 53 : (11111110000011)2 = (16259)10
Exercise 54 : (11110000111000)2 = (15416)10
Exercise 55 : (11)2 = (3)10
Exercise 56 : (111111110)2 = (510)10
Exercise 57 : (1111100001111000111001101)2 = (32567757)10
Exercise 58 : (1000000000000)2 = (4096)10
Exercise 59 : (11111001)2 = (249)10
Exercise 60 : (1000000000000001)2 = (32769)10
Summary
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428
(A) Exercises 61-72 (Convert hexadecimal to decimal)
Exercise 61 : (11)16 = (17)10
Exercise 62 : (AAF45)16 = (700229)10
Exercise 63 : (1B567)16 = (111975)10
Exercise 64 : (100)16 = (256)10
Exercise 65 : (1000)16 = (4096)10
Exercise 66 : (FF)16 = (255)10
Exercise 67 : (FFF)16 = (4095)10
Exercise 68 : (CDF)16 = (3295)10
Exercise 69 : (CAFE)16 = (51966)10
Exercise 70 : (FACA)16 = (64202)10
Exercise 71 : (DAD0)16 = (56016)10
Exercise 72 : (F1E2D3C4)16 = (4058174404)10
Summary
Prev.Page
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429
(A) Exercises 73-84 (Add numbers in binary)
Exercise 73 : (11001100)2 + (10101010)2 = (1 0111 0110)2
Exercise 74 : (1111001111)2 + (1001111001)2 = (110 0100 1000)2
Exercise 75 : (1111)2 + (1)2 = (10000)2
Exercise 76 : (1111)2 + (111)2 = (10110)2
Exercise 77 : (100001)2 + (11110)2 = (111111)2
Exercise 78 : (1011110011)2 + (111101111)2 = (100 1110 0010)2
Exercise 79 : (110011001100)2 + (101011110000)2 = (1 0111 1011 1100)2
Exercise 80 : (1111100001111000)2 + (101111)2 = (1111 1000 1010 0111)2
Exercise 81 : (111)2 + (1111)2 + (100)2 = (11010)2
Exercise 82 : (11)2 + (111)2 + (1111)2 + (11111)2 = (111000)2
Exercise 83 : (1111)2 + (1001)2 + (111)2 + (101)2 + (11)2 + (1)2 = (101000)2
Exercise 84 : (111)2 + (1000)2 + (1)2 + (1100)2 = (11100)2
Summary
Prev.Page
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430
(A) Exercises 85-96 (Subtract numbers in binary)
Exercise 85 : (11001100)2 - (1010101)2 = (111 0111)2
Exercise 86 : (1111001111)2 - (1111001)2 = (11 0101 0110)2
Exercise 87 : (1111)2 - (1)2 = (1110)2
Exercise 88 : (1111)2 - (111)2 = (1000)2
Exercise 89 : (100001)2 - (11110)2 = (11)2
Exercise 90 : (1011110011)2 - (111101111)2 = (1 0000 0100)2
Exercise 91 : (11001100)2 - (111011110000)2 = (...1111 1111 1100 1101)2
Exercise 92 : (1111000)2 - (101010111)2 = (... 1111 1111 0010 0001)2
Exercise 93 : (111)2 - (1111)2 = (... 1111 1111 1111 1000)2
Exercise 94 : (10001)2 - (111111)2 = (... 1111 1111 1101 0010)2
Exercise 95 : (0)2 - (1)2 = (... 1111 1111 1111 1111)2
Exercise 96 : (0)2 - (10)2 = (... 1111 1111 1111 1110)2
Summary
Prev.Page
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431
(A) Exercises 97-108 (Add numbers in hexadecimal)
Exercise 97 : (F12B)16 + (321)16 = (F44C)16
Exercise 98 : (1100)16 + (111)2 = (1211)16
Exercise 99 : (1000F)16 + (F0001)16 = (100010)16
Exercise 100 : (A9B8C7)16 + (D6E5F4)16 = (1809EBB)16
Exercise 101 : (CAFE)16 + (CDF)16 = (D7DD)16
Exercise 102 : (B001)16 + (FD)16 = (B0FE)16
Exercise 103 : (999)16 + (111)16 = (AAA)16
Exercise 104 : (123456)16 + (789ABC)16 = (19BBF12)16
Exercise 105 : (FFF)16 + (EEE)16 = (1EED)16
Exercise 106 : (DDD)16 + (333)16 = (1110)16
Exercise 107 : (987AED)16 + (CF01)16 = (9949EE)16
Exercise 108 : (FACA)16 + (CAFE)16 = (1C5C8)16
Summary
Prev.Page
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432
(A) Exercises 109-120 (Subtract numbers in hexadecimal)
Exercise 109 : (F1C5)16 - (101)16 = (F0C4)16
Exercise 110 : (1AD87C)16 - (FDE9)2 = (19DA93)16
Exercise 111 : (112233)16 - (44556)16 = (CDCDD)16
Exercise 112 : (AABBCC)16 - (DDEEF)16 = (9CDCDD)16
Exercise 113 : (F1E2D3)16 - (C4B5A6)16 = (2D2D2D)16
Exercise 114 : (FF00001)16 - (10000F)16 = (FDFFFF2)16
Exercise 115 : (CAFE)16 - (FACA)16 = (...FFFFD034)16
Exercise 116 : (CDF)16 - (FDC)16 = (...FFFFFD03)16
Exercise 117 : (10001)16 - (20001)16 = (...FFFF0000)16
Exercise 118 : (10000)16 - (FFFE)16 = (2)16
Exercise 119 : (0)16 - (9)16 = (...FFFFFFF7)16
Exercise 120 : (0)16 - (1A)16 = (...FFFFFFE6)16
Summary
Prev.Page
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433
(A) Exercises 121-126 (Representing binary numbers in bytes)
Exercise 121 : (1)10 = (0000 0000 0000 0001)2 = (0001)16
= (0000 0000 0000 0000 0000 0000 0000 0001)2 = (00000001)16
Exercise 122 : (-1)10 = (1111 1111 1111 1111)2 = (FFFF)16
= (1111 1111 1111 1111 1111 1111 1111 1111)2 = (FFFFFFFF)16
Exercise 123 : (10)10 = (0000 0000 0000 1010)2 = (000A)16
= (0000 0000 0000 0000 0000 0000 0000 1010)2 = (0000000A)16
Exercise 124 : (-10)10 = (1111 1111 1111 0110)2 = (FFF6)16
= (1111 1111 1111 1111 1111 1111 1111 0110)2 = (FFFFFFF6)16
Exercise 125 : (17)10 = (0000 0000 0001 0001)2 = (0011)16
= (0000 0000 0000 0000 0000 0000 0001 0001)2 = (00000011)16
Exercise 126 : (-17)10 = (1111 1111 1110 1111)2 = (FFEF)16
= (1111 1111 1111 1111 1111 1111 1110 1111)2 = (FFFFFFEF)16
Summary
Prev.Page
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434
(A) Exercises 127-132 (Representing binary numbers in bytes)
Exercise 127 : (254)10 = (0000 0000 1111 1110)2 = (00FE)16
= (0000 0000 0000 0000 0000 0000 1111 1110)2 = (000000FE)16
Exercise 128 : (-254)10 = (1111 1111 0000 0010)2 = (FF02)16
= (1111 1111 1111 1111 1111 1111 0000 0010)2 = (FFFFFF02)16
Exercise 129 : (100000)10 = (impossible to represent in 2 bytes)
= (0000 0000 0000 0001 1000 0110 1010 0000)2 = (000186A0)16
Exercise 130 : (-100000)10 = (impossible to represent in 2 bytes)
= (1111 1111 1111 1110 0111 1001 0110 0000)2 = (FFFE7960)16
Exercise 131 : (32000)10 = (0111 1101 0000 0000)2 = (7D00)16
= (0000 0000 0000 0000 0111 1101 0000 0000)2 = (00007D00)16
Exercise 132 : (-32000)10 = (1000 0011 0000 0000)2 = (8300)16
= (1111 1111 1111 1111 1000 0011 0000 0000)2 = (FFFF8300)16
Summary
Prev.Page
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435
(A) Exercises 133-138 (Representing binary numbers in bytes)
Exercise 133 : (63000)10 = (impossible to represent in 2 bytes)
= (1111 1111 1111 1111 1111 0110 0001 1000 )2 = (FFFFF618)16
Exercise 134 : (-63000)10 = (impossible to represent in 2 bytes)
= (1111 1111 1111 1111 0000 1001 1110 1000)2 = (FFFF09E8)16
Exercise 135 : (1010)10 = (0000 0011 1111 0010)2 = (03F2)16
= (0000 0000 0000 0000 0000 0011 1111 0010)2 = (000003F2)16
Exercise 136 : (-1010)10 = (1111 1100 0000 1110)2 = (FC0E)16
= (1111 1111 1111 1111 1111 1100 0000 1110)2 = (FFFFFC0E)16
Exercise 137 : (4095)10 = (0000 1111 1111 1111)2 = (0FFF)16
= (0000 0000 0000 0000 0000 1111 1111 1111)2 = (00000FFF)16
Exercise 138 : (-4095)10 = (1111 0000 0000 0001)2 = (F001)16
= (1111 1111 1111 1111 1111 0000 0000 0001)2 = (FFFFF001)16
Summary
Prev.Page
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436
(A) Exercises 139-140 (Representing binary numbers in bytes)
Exercise 139 : (4097)10 = (0001 0000 0000 0001)2 = (1001)16
= (0000 0000 0000 0000 0001 0000 0000 0001)2 = (00001001)16
Exercise 140 : (-4097)10 = (1110 1111 1111 1111)2 = (EFFF)16
= (1111 1111 1111 1111 1110 1111 1111 1111)2 = (FFFFEFFF)16
Summary
Prev.Page
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437
(A) Exercises 141-152 (Representing packed numbers in bytes)
Exercise 141 : (1)10 = [ 0001 1100 ] = [ 1C ]
Exercise 142 : (-1)10 = [ 0001 1101 } = [ 1D ]
Exercise 143 : (10)10 = [ 0000 0001 0000 1100 ] = [ 010C ]
Exercise 144 : (-10)10 = [ 0000 0001 0000 1101 ] = [ 10D ]
Exercise 145 : (17)10 = [ 0000 0001 0111 1100 ] = [ 017C ]
Exercise 146 : (-17)10 = [ 0000 0001 0111 1101 ] = [ 017D ]
Exercise 147 : (254)10 = [ 0010 0101 0100 1100 ] = [ 254C ]
Exercise 148 : (-254)10 = [0010 0101 0100 1101 ] = [ 254D ]
Exercise 149 : (100000)10 = [ 0000 0001 0000 0000 0000 0000 0000 1100 ] = [ 0100000C ]
Exercise 150 : (100000)10 = [ 0000 0001 0000 0000 0000 0000 0000 1101 ] = [ 0100000D ]
Exercise 151 : (32000)10 = [ 0011 0010 0000 0000 0000 1100 ] = [ 32000C ]
Exercise 152 : (-32000)10 = [ 0011 0010 0000 0000 0000 1101 ] = [ 32000D ]
Summary
Prev.Page
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438
(A) Exercises 153-160 (Representing packed numbers in bytes)
Exercise 153 : (63000)10 = [ 0110 0011 0000 0000 0000 1100 ] = [ 63000C ]
Exercise 154 : (-63000)10 = [ 0110 0011 0000 0000 0000 1101 ] = [ 63000D ]
Exercise 155 : (1010)10 = [ 0000 0001 0000 0001 0000 1100 ] = [ 01010C ]
Exercise 156 : (-1010)10 = [ 0000 0001 0000 0001 0000 1100 ] = [ 01010D ]
Exercise 157 : (4095)10 = [ 0000 0100 0000 1001 0101 1100 ] = [ 04095C ]
Exercise 158 : (-4095)10 = [ 0000 0100 0000 1001 0101 1101 ] = [ 04095D ]
Exercise 159 : (4097)10 = [ 0000 0100 0000 1001 0111 1100 ] = [ 04097C ]
Exercise 160 : (-4097)10 = [ 0000 0100 0000 1001 0111 1101 ] = [ 04097D ]
Summary
Prev.Page
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439
(A) Exercises 161-172 (Representing zoned numbers in bytes)
Exercise 161 : (1)10 = [ 1111 0001 ] = [ F1 ]
Exercise 162 : (-1)10 = [ 1101 0001 } = [ D1 ]
Exercise 163 : (10)10 = [ 1111 0001 1111 0000 ] = [ F1F0 ]
Exercise 164 : (-10)10 = [ 1111 0001 1101 0000 ] = [ F1D0 ]
Exercise 165 : (17)10 = [ 1111 0001 1111 0111 ] = [ F1F7 ]
Exercise 166 : (-17)10 = [ 1111 0001 1101 0111 ] = [ F1D7 ]
Exercise 167 : (254)10 = [ 1111 0010 1111 0101 1111 0100 ] = [ F2F5F4 ]
Exercise 168 : (-254)10 = [ 1111 0010 1111 0101 1101 0100 ] = [ F2F5D4 ]
Exercise 169 : (100000)10 =
[ 1111 0001 1111 0000 1111 0000 1111 0000 1111 0000 1111 0000 ] = [ F1F0F0F0F0F0 ]
Exercise 170 : (-100000)10 =
[ 1111 0001 1111 0000 1111 0000 1111 0000 1111 0000 1101 0000 ] = [ F1F0F0F0F0D0 ]
Exercise 171 : (32000)10 =
[ 1111 0011 1111 0010 1111 0000 1111 0000 1111 0000 ] = [ F3F2F0F0F0 ]
Exercise 172 : (-32000)10 =
[ 1111 0011 1111 0010 1111 0000 1111 0000 1111 0000 ] = [ F3F2F0F0D0 ]
Summary
Prev.Page
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440
(A) Exercises 173-180 (Representing zoned numbers in bytes)
Exercise 173 : (63000)10 =
[ 1111 0110 1111 0011 1111 0000 1111 0000 1111 0000 ] = [ F6F3F0F0F0 ]
Exercise 174 : (-63000)10 =
[ 1111 0110 1111 0011 1111 0000 1111 0000 1101 0000 ] = [ F6F3F0F0D0 ]
Exercise 175 : (1010)10 = [ 1111 0001 1111 0000 1111 0001 1111 0000 ] = [ F1F0F1F0 ]
Exercise 176 : (-1010)10 = [ 1111 0001 1111 0000 1111 0001 1101 0000 ] = [ F1F0F1D0 ]
Exercise 177 : (4095)10 = [ 1111 0100 1111 0000 1111 1001 1111 0101 ] = [ F4F0F9F5 ]
Exercise 178 : (-4095)10 = [ 1111 0100 1111 0000 1111 1001 1101 0101 ] = [ F4F0F9D5 ]
Exercise 179 : (4097)10 = [ 1111 0100 1111 0000 1111 1001 1111 1111 ] = [ F4F0F9F7 ]
Exercise 180 : (-4097)10 = [ 1111 0100 1111 0000 1111 1001 1101 0111 ] = [ F4F0F9D7 ]
Summary
Prev.Page
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441
(A) Exercises 181-194 (Representing character strings in bytes)
Exercise 181 : “17“ = [ F1F7 ]
Exercise 182 : “-17“ = [ 60F1F7 ]
Exercise 183 : “AF$BD“ = [ C1C66BC2C4 ]
Exercise 184 : “-AF4BD“ = [ 60C1C6F4C2C4 ]
Exercise 185 : “ALBERTO“ = [ C1D3C2C5D9E3D6 ]
Exercise 186 : “15-9“ = [ F1F560F9 ]
Exercise 187 : “-4095“ = [ 60F4F0F9F5 ]
Exercise 188 : “4095“ = [ F4F0F9F5 ]
Exercise 189 : “*&$//“ = [ 5C505B6161 ]
Exercise 190 : “12+3“ = [ F1F24EF3 ]
Exercise 191 : “I LOVE HER“ = [ C940D3D6E5C540C8C5D9 ]
Exercise 192 : “US$ 2,584.73“ = [ E4E25B40F26BF5F8F44BF7F3 ]
Exercise 193 : “US$ 1 MILLION“ = [ E4E25B40F140D4C9D3D3C9D6D5 ]
Exercise 194 : “PANCHO’S BAR“ = [ D7C1C5C3C8D67DE240C2C1D9 ]
Summary
Prev.Page
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442
(A) Exercises 195-209 (Representing fields in bytes)
Exercises 195-300 must be considered as a program starting at address X’00000000’, that is,
first area (exercise 195) begins at address zero. The DS defined areas must be computed to
determine the addresses. Assume the 1st statement of the program is USING *,9.
*
Address Contents
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
195:
196:
197:
198:
199:
200:
201:
202:
203:
204:
205:
206:
207:
208:
209:
Summary
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
Prev.Page
C'123'
C'+123'
C'-123'
C'12.3'
C'1AB8'
C'01101'
C'A+B=C'
CL4'A'
CL4'ABCDEF'
3CL2'A'
2CL3'A,B'
C'ME&&YOU'
C'''S MUSIC'
C'@@OI'
CL3'*'
0000
0003
0007
000B
000F
0013
0018
001D
0021
0025
002B
0031
0037
003F
0043
F1.F2.F3
4E.F1.F2.F3
60.F1.F2.F3
F1.F2.4B.F3
F1.C1.C2.F8
F0.F1.F1.F0.F1
C1.4E.C2.7E.C3
C1.40.40.40
C1.C2.C3.C4
C1.40.C1.40.C1.40
C1.6B.C2.C1.6B.C2
D4.C5.50.E8.D6.E4
7D.E2.40.D4.E4.E2.C9.C3
7C.7C.D6.C9
5C.40.40
Alberto Romano Schiesari – www.profars.com
443
(A) Exercises 210-225 (Representing fields in bytes)
*
Address Contents
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
210:
211:
212:
213:
214:
215:
216:
217:
218:
219:
220:
221:
222:
223:
224:
225:
Summary
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
Prev.Page
3C'*'
X'123'
X'-123'
X'1AB2C3'
X'1AB2F4G3'
XL3'12D'
XL3'AABBCCDDEE'
X'1,22,333,4444'
XL2'1,22,333'
2X'1,22,333'
2XL2'1,22'
B'01010101'
B'1'
BL2'1111'
B'1,1111111111'
BL2'1,1111111111'
0046 5C.5C.5C
0049 01.23
*** error ***
004B 1A.B2.C3
*** error ***
004E 00.01.2D
0051 CC.DD.EE
0054 01.22.03.33.44.44
005A 00.01.00.22.03.33
0060 01.22.03.33.01.22.03.33
0068 00.01.00.22.00.01.00.22
0070 55
0071 01
0072 00.0F
0074 01.03.FF
0077 00.01.03.FF
Alberto Romano Schiesari – www.profars.com
444
(A) Exercises 226-239 (Representing fields in bytes)
*
Address Contents
Exercise 226:
Exercise 227:
DC
DC
2B'1000'
2BL2'1000'
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
228:
229:
230:
230:
231:
232:
DC
DC
DC
DC
DC
DC
F'10'
F'+10'
F'-10'
F'-15,+16'
2F'22'
2F'33,44'
Exercise 233:
Exercise 234:
DC
DC
FL3'258'
2FL1'255'
Exercise
Exercise
Exercise
Exercise
Exercise
DC
DC
DC
DC
DC
F'128000'
H'10'
H'+10'
H'-10'
H'-15,+16'
235:
236:
237:
238:
239:
Summary
Prev.Page
007B
007D
0081
0084
0088
008C
0090
0098
00A0
00B0
00B3
00B5
00B8
00BC
00BE
00C0
00C2
08.08
00.08.00.08
00.00.00 (align)
00.00.00.0A
00.00.00.0A
FF.FF.FF.F6
FF.FF.FF.F1.00.00.00.10
00.00.00.16.00.00.00.16
00.00.00.21.00.00.00.2C
00.00.00.21.00.00.00.2C
00.01.02
FF.FF
00.00.00 (align)
00.01.F4.00
00.0A
00.0A
FF.F6
FF.F1.00.10
Alberto Romano Schiesari – www.profars.com
445
(A) Exercises 240-254 (Representing fields in bytes)
*
Address Contents
Exercise
Exercise
Exercise
Exercise
240:
241:
242:
243:
DC
DC
DC
DC
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
244:
245:
246:
247:
248:
249:
250:
251:
252:
253:
254:
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
DC
Summary
2H'22'
2H'33,44'
HL3'258'
2HL1'255'
00C6 00.16.00.16
00CA 00.21.00.2C.00.21.00.2C
00D2 00.01.02
00D5 FF.FF
00D7 00 (align)
H'128000'
00D8 F4.00
P'123'
00DA 12.3C
P'+123'
00DC 12.3C
P'-123'
00DE 12.3D
PL4'456'
00E0 00.00.45.6C
PL1'789'
00E4 9C
P'1,-22,333,-4444' 00E5 1C.02.2D.33.3C.04.44.4D
PL2'1,-22,333,-4444' 00ED 00.1C.02.2D.33.3C.44.4D
3P'0'
00F5 0C.0C.0C
PL3'0'
00F8 00.00.0C
2P'1,22,333'
00FB 1C.02.2C.33.3C.1C.02.2C.33.3C
Prev.Page
Alberto Romano Schiesari – www.profars.com
446
(A) Exercises 255-266 (Representing fields in bytes)
*
Address Contents
Exercise 255:
DC
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
DC
DC
DC
DC
DC
DC
DC
256:
257:
258:
259:
260:
261:
262:
2PL2'1,22,333'
0105 00.1C.02.2C.33.3C
00.1C.02.2C.33.3C
Z'123'
0111 F1.F2.C3
Z'+123'
0114 F1.F2.C3
Z'-123'
0117 F1.F2.D3
ZL4'456'
011A F0.F4.F5.C6
ZL1'789'
011E C9
Z'1,-22,333,-4444'
011F F1.F2.D2.F3.F3.C3.F4.F4.F4.D4
ZL3'1,-22,333,-4444' 0129 F0.F0.C1.F0.F2.D2.F3.F3.C3
F4.F4.F4.D4
Exercise 263:
Exercise 264:
Exercise 265:
DC
DC
DC
3Z'0'
ZL3'0'
2Z'1,22,333'
Exercise 266:
DC
2ZL3'1,22,333'
0135 C0.C0.C0
0138 F0.F0.F0
013B C1.F2.C2.F3.F3.C3
C1.F2.C2.F3.F3.C3
0147 F0.F0.C1.F0.F2.C2.F3.F3.C3
F0.F0.C1.F0.F2.C2.F3.F3.C3
Summary
Prev.Page
Alberto Romano Schiesari – www.profars.com
447
(A) Exercises 267-279 (Representing fields in bytes)
*
Address Contents
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
267:
268:
269:
270:
271:
272:
273:
SIMBZZ
SIMBAA
SIMBBB
SIMBCC
SIMBDD
SIMBEE
SIMBFF
DC
DC
DC
DC
DC
DC
DS
A(0)
A(127)
A(X'8000')
A(B'1111')
A(C'*')
A(*)
CL17
0159
015C
0160
0164
0168
016C
0170
0174
00.00.00 (align)
00.00.00.00
00.00.00.7F
00.00.80.00
00.00.00.0F
00.00.00.5C
00.00.01.70
??.??.??.??.??.??.??.??.??
??.??.??.??.??.??.??.??
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
274:
275:
276:
277:
278:
279:
Summary
SIMBGG
SIMBHH
SIMBII
SIMBJJ
SIMBKK
SIMBLL
Prev.Page
DC
DC
DC
DC
DC
DC
0185
A(*)
0188
A(SIMBGG)
018C
A(SIMBAA+12)
0190
A(SIMBII-SIMBBB) 0194
AL1(*-SIMBKK)
0198
5AL1(*-SIMBLL)
0199
00.00.00 (align)
00.00.01.88
00.00.01.88
00.00.01.6C
00.00.00.2C
00
00.01.02.03.04
Alberto Romano Schiesari – www.profars.com
448
(A) Exercises 280-290 (Representing fields in bytes)
*
Endereço Conteúdo
Exercise
Exercise
Exercise
Exercise
280:
281:
282:
283:
SIMBMM
SIMBNN
SIMBOO
SIMBPP
DC
DC
DC
DC
AL2(3,5,7)
A(SIMBII+5*2)
A(SIMBNN+X'80000000')
4AL2(*-SIMBPP)
019E
01A4
01A8
01AC
Exercise 284: SIMBQQ
Exercise 285: SIMBRR
DC
DC
A(SIMBVV)
A(SIMBKK,SIMBJJ)
01B4
01B8
Exercise 286: SIMBSS
Exercise 287: SIMBTT
DC
DC
A(SIMBTT+40)
A(SIMBUU,*,80)
01C0
01C4
Exercise 288: SIMBUU
DC
2A(*-SIMBUU)
01D0
Exercise 289: SIMBVV
Exercise 290: SIMBWW
DC
DC
A(C'AMO')
A(X'7FFFFFFF')
01D8
01DC
Summary
Prev.Page
00.03.00.05.00.07
00.00.01.9A
80.00.01.A4
00.00.00.02.00.04
00.06
00.00.01.D8
00.00.01.98
00.00.01.94
00.00.01.EC
00.00.01.D0
00.00.01.C8
00.00.00.50
00.00.00.00
00.00.00.04
00.C1.D4.D6
7F.FF.FF.FF
Alberto Romano Schiesari – www.profars.com
449
(A) Exercises 291-299 (Representing fields in bytes)
*
Address Contents
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
Exercise
291:
292:
293:
294:
295:
296:
297:
YY1
YY2
YY3
SS1
SS2
SS3
SS4
DC
DC
DC
DC
DC
DC
DC
Exercise 298: SS5
DC
01E0
01E2
01E4
01E6
01E8
01EA
01EC
01EE
A(125),F'33',C'*',2H'6,18' 01F0
Exercise 299: SS6
DC
X'1,1',B'1,1',C'1,1'
Summary
Prev.Page
Y(SIMBWW)
Y(10)
Y(L'YY2)
S(SIMBAA)
S(SS1)
S(10)
S(*)
01.DC
00.0A
00.02
91.60
91.E6
00.0A
91.EC
00.00 (align)
00.00.00.7D
00.00.00.21
5C
00 (align)
00.06.00.12
00.06.00.12
0202 01.01.01.01
F1.6B.F1
Alberto Romano Schiesari – www.profars.com
450
(A) Exercise 300 (Representing fields in bytes)
*
Endereço Conteúdo
Exercise 300:
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
LAST DC 256AL1(255+LAST-*)
Summary
Prev.Page
0209
0219
0229
0239
0249
0259
0269
0279
0289
0299
02A9
02B9
02C9
02D9
02E9
02F9
FF.FE.FD.FC.FB.FA.F9.F8.F7.F6.F5.F4.F3.F2.F1.F0
EF.EE.ED.EC.EB.EA.E9.E8.E7.E6.E5.E4.E3.E2.E1.E0
DF.DE.DD.DC.DB.DA.D9.D8.D7.D6.D5.D4.D3.D2.D1.D0
CF.CE.CD.CC.CB.CA.C9.C8.C7.C6.C5.C4.C3.C2.C1.C0
BF.BE.BD.BC.BB.BA.B9.B8.B7.B6.B5.B4.B3.B2.B1.B0
AF.AE.AD.AC.AB.AA.A9.A8.A7.A6.A5.A4.A3.A2.A1.A0
9F.9E.9D.9C.9B.9A.99.98.97.96.95.94.93.92.91.90
8F.8E.8D.8C.8B.8A.89.88.87.86.85.84.83.82.81.80
7F.7E.7D.7C.7B.7A.79.78.77.76.75.74.73.72.71.70
6F.6E.6D.6C.6B.6A.69.68.67.66.65.64.63.62.61.60
5F.5E.5D.5C.5B.5A.59.58.57.56.55.54.53.52.51.50
4F.4E.4D.4C.4B.4A.49.48.47.46.45.44.43.42.41.40
3F.3E.3D.3C.3B.3A.39.38.37.36.35.34.33.32.31.30
2F.2E.2D.2C.2B.2A.29.28.27.26.25.24.23.22.21.20
1F.1E.1D.1C.1B.1A.19.18.17.16.15.14.13.12.11.10
0F.0E.0D.0C.0B.0A.09.08.07.06.05.04.03.02.01.00
Alberto Romano Schiesari – www.profars.com
451
(A) Exercise 301 (Decoding instructions)
Exercise 301 : Decode the following set of instructions
1ABB41278CF00A13980F334445E00CB490EC0D00FA82305448CCD28233445566
----////////----////////--------////////------------////////////
Suppose the general registers with the following values:
R00=00112233
R01=00000100
R02=00000200
R03=00000300
Summary
R04=00000400
R05=00000500
R06=00000600
R07=00000700
Prev.Page
R08=00000800
R09=00000900
R10=00000A00
R11=00000B00
R12=00000C00
R13=00000D00
R14=00000E00
R15=00000F00
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452
(A) Exercise 301 (Decoding instructions)
Exercise 301 : Decode the following set of instructions
1ABB41278CF00A13980F334445E00CB490EC0D00FA82305448CCD28233445566
----////////----////////--------////////------------////////////
1ABB
- Operation code (machine code) = 1A
- Mnemonic Assembler code = AR (add register)
- Instruction address = X’00000000’
- Operands = 1st operand = register 11; 2nd operand = register 11
41278CF0
- Operation code (machine code) = 41
- Mnemonic Assembler code = LA (load address)
- Instruction address = X’00000002’
-Operands = 1st operand = register 2;
2nd operand : index register = register 7
2nd operand : base register = register 8
2nd operand : displacement = X’CF0’
2nd operand address = X’ 00000700’+X’00000800’+X’CF0’= X’00001BF0’
Continues...
Summary
Prev.Page
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453
(A) Exercise 301 (Decoding instructions)
Exercise 301 : Decode the following set of instructions
1ABB41278CF00A13980F334445E00CB490EC0D00FA82305448CCD28233445566
----////////----////////--------////////------------////////////
0A13
- Operation code (machine code) = 0A
- Mnemonic Assembler code = SVC (supervisor call)
- Instruction address = X’00000006’
- Operands = supervisor call code = X’13’ = (19)10 = open
980F3344
- Operation code (machine code) = 98
- Mnemonic Assembler code = LM (load multiple)
- Instruction address = X’00000008’
-Operands = 1st operand = register 0;
3rd operand : register = register 15 (X’F’)
2nd operand : base register = register 3
2nd operand : displacement = X’344’
2nd operand address = X’00000300’+X’344’= X’00000644’
Continues...
Summary
Prev.Page
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454
(A) Exercise 301 (Decoding instructions)
Exercise 301 : Decode the following set of instructions
1ABB41278CF00A13980F334445E00CB490EC0D00FA82305448CCD28233445566
----////////----////////--------////////------------////////////
45E00CB4
- Operation code (machine code) = 45
- Mnemonic Assembler code = BAL (branch and link)
- Instruction address = X’0000000C’
-Operands = 1st operand = register 14 (X’E’);
2nd operand : index register = register 0
2nd operand : base register = register 0; 2nd operand : displacement = X’CB4’
2nd operand address = X’CB4’= X’00000CB4’
90EC0D00
- Operation code (machine code) = 90
- Mnemonic Assembler code = STM (store multiple)
- Instruction address = X’00000010’
-Operands = 1st operand = register 14 (X’E’); 3rd operand : register = register 12 (X’C’)
2nd operand : base register = register 0; 2nd operand : displacement = X’D00’
2nd operand address = X’D00’= X’00000D00’
Continues...
Summary
Prev.Page
Alberto Romano Schiesari – www.profars.com
455
(A) Exercise 301 (Decoding instructions)
Exercise 301 : Decode the following set of instructions
1ABB41278CF00A13980F334445E00CB490EC0D00FA82305448CCD28233445566
----////////----////////--------////////------------////////////
FA82305448CC
- Operation code (machine code) = FA
- Mnemonic Assembler code = AP (add packed)
- Instruction address = X’00000014’
- 1st operand length = 9 bytes; 1st operand base register = register 3;
1st operand displacement= X’054’; 1st operand address= X’00000300’+X’054’ = X’00000354’
- 2nd operand length = 3 bytes; 2nd operand base register = register 4; 2nd operand
displacement = X’8CC’; 2nd operand address= X’00000400’+X’8CC’ = X’00000CCC’
D28233445566
- Operation code (machine code) = D2
- Mnemonic Assembler code = MVC (move character)
- Instruction address = X’0000001A’
- 1st operand length = 131 bytes; 1st operand base register = register 3;
1st operand displacement= X’344’; 1st operand address= X’00000300’+X’344’ = X’00000644’
- 2nd operand length = 131 bytes; 2nd operand base register = register 5; 2nd operand
displacement = X566’; 2nd operand address= X’00000500’+X’566’ = X’00000A66’
Summary
Prev.Page
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456
Programming Hints
Programming Hints
Summary
Prev.Page
Alberto Romano Schiesari – www.profars.com
457
Programming Hints
Interesting things,
useful things, awful
but used things, etc...
Summary
Prev.Page
Alberto Romano Schiesari – www.profars.com
458
Programming Hints
Let’s figure out an 11K program, with only one base register
PROG
START
USING
LR
...
0
*,3
3,15
USING specified when Location Counter has zero (assembly time)
Load 1st and only base register (run time)
4K
Part of the program that is within
the range of the base register R3;
any symbol herein declared, which
must be converted to
Base+Displacement has R3 as base
register.
Summary
Prev.Page
4K
3K
This part of rhe program is outside from the range
of the base register.
Any symbol herein declared, which must be
converted to Base+Displacement : ERROR
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459
Programming Hints
Let’s figure out an 11K program, with 2 base registers
PROG
START
USING
LR
LA
LA
...
0
*,3,7
USING specified when Loc. Counter has zero (assembly time)
3,15
Load 1st base register (run time)
7,2048(3)
Begin loading 2nd base register (run time)
7,2048(3,7)
Complete loading 2nd base register (run time)
4K
Part of the program that is within
the range of the base register R3;
any symbol herein declared, which
must be converted to
Base+Displacement has R3 as base
register.
Summary
Prev.Page
4K
Part of the program that is within
the range of the base register R7;
any symbol herein declared, which
must be converted to
Base+Displacement has R7 as base
register.
3K
This part of the programt is
outside the range of both base
registers; any symbol herein
declared, which must be
converted to
Base+Displacement: ERROR
Alberto Romano Schiesari – www.profars.com
460
Programming Hints
Let’s figure out an 11K program, with 3 base registers
PROG
START
USING
LR
LA
LA
LA
LA
...
0
*,3,7,6
USING specified when Loc. Counter has zero (assembly time)
3,15
Load 1st base register (run time)
7,2048(3)
Begin loading 2nd base register (run time)
7,2048(3,7)
Complete loading 2nd base register (run time)
6,1
Begin loading 2nd base register (run time)
6,4095(6,7)
Complete loading 2nd base register (run time)
4K
Part of the program
within the range of the
base register R3
Summary
Prev.Page
4K
3K
Part of the program
within the range of the
base register R7
Part of the
program within
the range of the
base register R6
“Part in
excess”
for base
reg R7
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461
Programming Hints
Let’s figure out a 1000K program, with only one base register
PROG
START
USING
LR
...
0
*,3
3,15
4K
996K
Part of the program
within the range of the
base register R3
Summary
USING specified when Location Counter has zero (assembly time)
Load 1st and only base register (run time)
Prev.Page
This part of the programt is outside the range of the base register;
any symbol herein declared, which must be converted to
Base+Displacement: ERROR
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462
Programming Hints
Let’s figure out a 1000K program, with only one base register
4K
996K
Instructions
Areas
Part of the program
within the range of the
base register R3
Summary
Prev.Page
This part of the programt is outside the range of the base register;
any symbol herein declared, which must be converted to
Base+Displacement: ERROR
Alberto Romano Schiesari – www.profars.com
463
Programming Hints
Let’s figure out a 1000K program, with only one base register
Instrutions
Areas
(with
base
reg.)
Areas
(WITHOUT
base register)
END
(source program
finish)
Implicit
(END)
LTORG
Part of the program
within the range of the
base register R3
Summary
Prev.Page
LITERALS
declared by
LTORG
(without base)
This part of the programt is outside the range of the base register;
any symbol herein declared, which must be converted to
Base+Displacement: ERROR
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464
Programming Hints
Let’s figure out a 1000K program, with only one base register
Instruction
Areas
(with
base)
Explicitly
declared (by
programmer)
LTORG
Areas
(WITHOUT
base)
LITERALS
declared by
LTORG
(with base)
Part of the program
within the range of the
base register R3
Summary
Prev.Page
END
(source program
finish)
Areas still
WITH
base
This part of the programt is outside the range of the base register;
any symbol herein declared, which must be converted to
Base+Displacement: ERROR
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465
Programming Hints
Let’s figure out a 1000K program, with only one base register
Instruction
Areas
(with
base)
Explicitly
declared (by
programmer)
LTORG
Areas
(WITHOUT
base)
LITERALS
declared by
LTORG
(with base)
END
(source program
finish)
Areas still
WITH
base
Let’s take
a good
and
detailed
look
Summary
Prev.Page
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466
Programming Hints
Let’s figure out a 1000K program, with only one base register
Instructions
Areas
L
T
O
R
G
Literals
(with
base)
Início das áreas
“grandes” (supor: 1os
100 bytes de uma área
de 500000 bytes, por
ex. TABXX)
TABXX DS 1000CL500
Restante da área
(499900 bytes) +
uma 2ª área grande
TABYY
+
Uma pequena área
de 4 bytes (XYZ)
- instructions,
- areas before LTORG,
- literals and
- the beginning of the “big” areas (specifically the first 100 bytes from TABXX)
Are within the range of the base register.
Summary
Prev.Page
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467
Programming Hints
Let’s figure out a 1000K program, with only one base register
Instruções
Áreas
L
T
O
R
G
TABXX
Literais
(com
base)
DS
1000CL500
100 1os bytes de
TABXX
Demias 499900 bytes de
TABXX
TABYY DS CL 1000CL52
XYZ
DS CL4
- 1st 100 bytes of TABXX
Are within the range of the base register
- Next 499900 bytes of TABXX
- All 520000 bytes of TABYY
- 4 bytes of XYZ
Are outside the range of the base register
Summary
Prev.Page
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468
Programming Hints
Let’s figure out a 1000K program, with only one base register
Instructions
Areas
L
T
O
R
G
TABXX
Literals
(with
base)
DS
1000CL500
1st 100 bytes of
TABXX
Demias 499900 bytes de
TABXX
TABYY DS CL 1000CL52
XYZ
DS CL4
LA R9,TABXX
OK! TABXX (TABXX address ís the address of the leftmost byte of TABXX) is within
the range of the base register
L R9,=A(TABXX)
OK! The literal with TABXX address is within the range of the base register
LA R9,TABXX+1
L
OK! TABXX+1 is na address within the range of the base register
R9,=A(TABXX+1) OK! The literal with TABXX+1 address is within the range of the base register
LA R9,TABXX+99
OK! TABXX+99 is an address within the range of the base register
L R9,=A(TABXX+99) OK! The literal with TABXX+99 address is within the range of the base register
Summary
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469
Programming Hints
Let’s figure out a 1000K program, with only one base register
Instruções
Áreas
L
T
O
R
G
TABXX
Literais
(com
base)
DS
1000CL500
100 1os bytes de
TABXX
Demias 499900 bytes de
TABXX
TABYY DS CL 1000CL52
XYZ
DS CL4
LA R9,TABXX+100 ERROR!!! TABXX+100 é o 101º. Byte de TABXX, e, portanto, o primeiro a NÃO ser
servido pelo registrador base.
L R9,=A(TABXX+100)
OK! A literal que tem o endereço de TABXX+100 está dentro do alcance do
registrador base
LA R9,TABYY
base
L R9,=A(TABYY)
base
LA R9,XYZ
L R9,=A(XYZ)
base
Summary
ERROR!! TABYY é um endereço que NÃO está dentro do alcance do registrador
OK! A literal que tem o endereço de TABYY está dentro do alcance do registrador
ERROR!!! XYZ é um endereço que NÃO está dentro do alcance do registrador base
OK! A literal que tem o endereço de XYZ está dentro do alcance do registrador
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470
Programming Hints
Programs with 1 base register
Assembler specification
and
runtime load
Summary
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471
Programming Hints
Loading base register with entry point address with LR
PROG
START
USING
LR
0
*,3
3,15
LOAD FIRST AND ONLY BASE REGISTER
*
REG 3 CONTAINS THE ENTRY POINT ADDRESS
* THIS TYPE OF LOAD (WITH LR) IS OFTEN USED IN MVS
Loading base register with entry point address with BALR+BCTR+BCTR
PROG
START
USING
BALR
BCTR
BCTR
0
*,3
3,0
3,0
3,0
*
*
Summary
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LOAD INTO R3 THE ADDRESS JUST AFTER BALR
SUBTRACTS 1
SUBTRACTS 1 ONCE MORE
HERE REGISTER 3 IS OK;
IT HAS THE ENTRY POINT ADDRESS
Alberto Romano Schiesari – www.profars.com
472
Programming Hints
Programs with 2 base registers
Assembler specification
and
runtime load
Summary
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Alberto Romano Schiesari – www.profars.com
473
Programming Hints
Loading 1st base register with entry point address with LR
and
2nd with entry point address + 4096 with LA
PROG
START
USING
LR
*
LA
0
*,3,4
3,15
LOAD FIRST BASE REGISTER
REG 3 CONTENTS = ENTRY POINT ADDRESS
4,4096(4) LOAD INTO R4 THE VALUE OF R3 + 4096
NO! Why not? Because maximum displacement is 4095 (X’FFF’) !!!
Assembly error !
Summary
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Alberto Romano Schiesari – www.profars.com
474
Programming Hints
Loading 1st base register with entry point address with LR
and
2nd with entry point address + 4096 with LA+LA+AR
PROG
START
USING
LR
*
LA
LA
*
AR
*
*
*
OK
Summary
0
*,3,4
3,15
LOAD FIRST BASE REGISTER
REG 3 CONTENTS = ENTRY POINT ADDRESS
4,1
LOAD NUMBER 1 INTO REG 4
4,4095(4) ADD 4095
RESULT = 4096
4,3
ADD ENTRY POINT.
R4 CONTENTS = ENTRY POINT + 4096
OR ENTRY POINT + X’001000’
! R3 AND R4 PROPERLY LOADED !
Prev.Page
Alberto Romano Schiesari – www.profars.com
475
Programming Hints
Loading 1st base register with entry point address with LR
and
2nd with entry point address + 4096 with LA+LA+AR
PROG
START
USING
LR
*
LA
LA
*
AR
*
*
*
OK
Summary
0
*,3,4
3,15
LOAD FIRST BASE REGISTER
REG 3 CONTENTS = ENTRY POINT ADDRESS
4,4095 LOAD NUMBER 4095 INTO REG 4
4,1(4) ADD 1
RESULT = 4096
4,3
ADD ENTRY POINT.
R4 CONTENTS = ENTRY POINT + 4096
OR ENTRY POINT + X’001000’
! R3 AND R4 PROPERLY LOADED !
Prev.Page
Alberto Romano Schiesari – www.profars.com
476
Programming Hints
Loading 1st base register with entry point address with LR
and
2nd with entry point address + 4096 with LA+LA
PROG
*
*
*
*
START
USING
LR
0
*,3,4
3,15
LOAD FIRST BASE REGISTER
REG 3 CONTENTS = ENTRY POINT ADDRESS
LA
4,1
LOAD NUMBER 1 INTO REG 4
LA
4,4095(3,4) ADD 4095 + ENTRY POINT
R4 CONTENTS = ENTRY POINT + 4096
OR ENTRY POINT + X’001000’
OK ! R3 AND R4 PROPERLY LOADED !
Summary
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Alberto Romano Schiesari – www.profars.com
477
Programming Hints
Loading 1st base register with entry point address with LR
and
2nd with entry point address + 4096 with LA+LA
PROG
*
*
*
*
START
USING
LR
0
*,3,4
3,15
LOAD FIRST BASE REGISTER
REG 3 CONTENTS = ENTRY POINT ADDRESS
LA
4,2048
LOAD NUMBER 1 INTO REG 4
LA
4,2048(3,4) ADD 2048 + ENTRY POINT
R4 CONTENTS = ENTRY POINT + 4096
OR ENTRY POINT + X’001000’
OK ! R3 AND R4 PROPERLY LOADED !
Summary
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Alberto Romano Schiesari – www.profars.com
478
Programming Hints
Loading 1st base register with entry point address with LR
and
2nd with entry point address + 4096 with LA+LA
PROG
*
*
*
*
START
USING
LR
0
*,3,4
3,15
LOAD FIRST BASE REGISTER
REG 3 CONTENTS = ENTRY POINT ADDRESS
LA
4,1000
LOAD R4 WITH # 1000
LA
4,3096(3,4) ADD 3096 + ENTRY POINT
R4 CONTENTS = ENTRY POINT + 4096
OR ENTRY POINT + X’001000’
OK ! R3 AND R4 PROPERLY LOADED !
Summary
Prev.Page
Alberto Romano Schiesari – www.profars.com
479
Programming Hints
Loading 1st base register with entry point address with LR
and
2nd with entry point address + 4096 with LA
PROG
START
USING
LR
*
LA
0
*,3,4
3,15
LOAD FIRST BASE REGISTER
REG 3 CONTENTS = ENTRY POINT ADDRESS
4,PROG+4096 LOAD “DIRECTLY” ENTRY POINT + 4096
NO!
Why not?
Because the address PROG+40096 isn’t in the range of first base register
(R3), so far the only one correctly loaded. Assembly error.
Summary
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Alberto Romano Schiesari – www.profars.com
480
Programming Hints
Loading 1st base register with entry point address with LR
and
2nd with entry point address + 4096 with L
PROG
START
USING
LR
*
L
0
*,3,4
3,15
LOAD FIRST BASE REGISTER
REG 3 CONTENTS = ENTRY POINT ADDRESS
4,=A(PROG+4096) LOAD “DIRECTLY” ENTRY POINT + 4096
IT DEPENDS ON ... !
The contents of the literal is being loaded into R4.
If the literal is outside the range of the FIRST BASE REGISTER (R3)
(THE ONLY ONE CORRECTLY LOADED SO FAR), THEN this is
INVALID to prepare the second base register. Assembly error. (case 1)
ELSE, this way (using the literal) is VALID. (case 2)
Summary
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Alberto Romano Schiesari – www.profars.com
481
Programming Hints
Loading 1st base register with entry point address with LR and
2nd with entry point address + 4096 with L
CASE 1 : Literal is outside range of the 1st base register (R3), and it is
the only one prepared so far. You can’t do this way ! Assembly error.
PROG
START
USING
LR
L
...
0
*,3,4
3,15
4,=A(PROG+4096)
This part is
served by 1st
base register
( L needs the 2nd base register prepared, but... L prepares the
2nd base register! Execution time error!)
Program = 8k
END
...
( literals are declared after END)
=A(PROG+4096)
Summary
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This part is
served by
2nd base
register
Alberto Romano Schiesari – www.profars.com
482
Programming Hints
Loading 1st base register with entry point address with LR and
2nd with entry point address + 4096 with L
CASE 2 : Literal is in the range of the first base register (R3), and it is
the only one prepared so far, so you can do this way.
PROG
SKIP
START 0
USING *,3,4
LR
3,15
L
4,=A(PROG+4096)
B
SKIP
LTORG
=A(PROG+4096)
...
This part is
served by 1st
base register
Forces the
literal to be
defined here.
Program = 8k
END
...
(other literals declared here)
=...
=...
Summary
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This part is
served by
2nd base
register
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483
THE END
Summary
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484
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